CN106033752B - 半导体衬底及具有半导体衬底的半导体封装结构 - Google Patents

半导体衬底及具有半导体衬底的半导体封装结构 Download PDF

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CN106033752B
CN106033752B CN201510120701.3A CN201510120701A CN106033752B CN 106033752 B CN106033752 B CN 106033752B CN 201510120701 A CN201510120701 A CN 201510120701A CN 106033752 B CN106033752 B CN 106033752B
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pad
conductive
width
conductive projection
insulating barrier
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CN106033752A (zh
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廖国成
陈家庆
丁权
丁一权
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本发明涉及一种半导体封装结构，其包含半导体衬底、半导体芯片及导电材料。所述半导体衬底包含绝缘层、导电电路层及导电凸块。所述导电电路层从所述绝缘层的顶表面凹入，且包含至少一个衬垫。所述导电凸块安置在所述至少一个衬垫上。所述导电凸块的侧表面、所述至少一个衬垫的顶表面及所述绝缘层的侧表面一起界定容置空间。所述导电材料电连接所述导电凸块与所述半导体芯片，且所述导电材料的一部分安置在所述容置空间中。

Description

半导体衬底及具有半导体衬底的半导体封装结构
技术领域
本发明涉及半导体衬底及具有半导体衬底的半导体封装结构。明确地说，本发明涉及用于倒装芯片接合/互连的半导体衬底及具有半导体衬底的半导体封装结构。
背景技术
随着电子行业的快速发展及半导体处理技术的进展，半导体芯片与越来越多的电子元件集成以实现更好的电气性能。因此，半导体芯片具备更多的输入/输出(I/O)连接。为了使半导体封装小型化同时使用具有增加的数目个I/O连接的半导体芯片，用于携载半导体芯片的半导体衬底的接合垫密度应相对应地增加。
然而，半导体封装的小型化还减少半导体衬底上在半导体芯片周围的空间，从而导致进一步需要较高密度的接合垫/焊料。
半导体芯片的电路与半导体衬底的电路之间的互连可借助于凸块/焊料来进行，所述凸块/焊料附接到半导体芯片的接合垫，且接合到半导体衬底的接合垫上的相对应的互连凸块/支柱。然而，对于倒装芯片封装，当接合垫密度高时，可能难以在半导体芯片与半导体衬底之间执行接合工艺。可能容易在邻近的导电迹线与半导体衬底的互连凸块/支柱之间发生短路，这是因为焊料可形成桥接器且产品可由此出故障。
发明内容
本发明的一方面涉及一种半导体封装结构。在一实施例中，所述半导体封装结构包括半导体衬底、半导体芯片及导电材料。所述半导体衬底包括绝缘层、导电电路层及导电凸块。所述绝缘层具有顶表面。所述导电电路层从所述绝缘层的所述顶表面凹入。所述导电电路层包括至少一个衬垫及连接到所述至少一个衬垫的导电迹线。所述导电凸块安置在所述至少一个衬垫上。所述导电凸块的侧表面、所述至少一个衬垫的顶表面及所述绝缘层的侧表面一起界定容置空间。所述导电材料电连接到所述导电凸块及所述半导体芯片。所述导电材料的一部分安置在所述容置空间中。
本发明的另一方面涉及一种半导体衬底。在一实施例中，所述半导体衬底包括绝缘层、导电电路层及第一导电凸块。所述绝缘层具有顶表面。所述导电电路层从所述绝缘层的所述顶表面凹入。所述导电电路层包括至少一个第一衬垫及连接到所述第一衬垫的第一导电迹线。所述第一导电凸块安置在所述第一衬垫上，其中所述第一导电凸块的宽度小于所述第一衬垫的宽度，且所述第一导电凸块的侧表面、所述第一衬垫的顶表面及所述绝缘层的侧表面一起界定第一容置空间。
本发明的另一方面涉及一种半导体封装结构。在一实施例中，所述半导体封装结构包括半导体衬底、半导体芯片及导电材料。所述半导体衬底包括绝缘层、导电电路层及第一导电凸块。所述绝缘层具有顶表面。所述导电电路层从所述绝缘层的所述顶表面凹入。所述导电电路层包括至少一个第一衬垫及连接到所述第一衬垫的第一导电迹线。所述第一导电凸块安置在所述第一衬垫上。所述导电材料电连接到所述第一导电凸块及所述半导体芯片。所述导电材料的一部分低于所述绝缘层的所述顶表面。
附图说明
图1为根据本发明的一实施例的半导体衬底的透视图；
图2为沿着图1的半导体衬底的线2-2截取的截面图；
图3为根据本发明的一实施例的半导体封装结构的部分截面图；
图4为根据本发明的另一实施例的半导体封装结构的部分截面图；
图5为根据本发明的另一实施例的半导体封装结构的部分截面图；
图6为根据本发明的另一实施例的半导体衬底结构的截面图；
图7为根据本发明的另一实施例的半导体封装结构的部分截面图；
图8为根据本发明的另一实施例的半导体衬底的截面图；
图9A、9B、9C、9D、9E、9F、9G、9H、9I及9J说明根据本发明的一实施例的制造半导体封装结构的方法。
贯穿图式及详细描述使用共同参考数字以指示相同或类似元件。本发明的实施例将从结合附图进行的以下详细描述更显而易见。
具体实施方式
图1展示根据本发明的一实施例的半导体衬底1的透视图。半导体衬底1包括第一导电凸块141、第二导电凸块142、第一衬垫221、第二衬垫222、第一导电迹线111、第二导电迹线112、第三导电迹线321及第四导电迹线322。第一导电凸块141安置在形成于绝缘层16(图2)中的第一衬垫221上，且第二导电凸块142安置在形成于绝缘层16(图2)中的第二衬垫222上。第一导电凸块141及第二导电凸块142的材料可与第一衬垫221及第二衬垫222的材料相同或不同。第一导电凸块141、第二导电凸块142、第一衬垫221及第二衬垫222中的每一者包含铜，且还可包含另一金属或金属合金或其它导电材料。如图1中所展示，第一导电凸块141的形状实质上与第一衬垫221的形状相同，且第二导电凸块142的形状实质上与第二衬垫222的形状相同。
第一导电迹线111连接到第一衬垫221，且第二导电迹线112连接到第二衬垫222。在此实施例中，第三导电迹线321及第四导电迹线322安置在第一衬垫221与第二衬垫222之间。在另一实施例中，可存在安置在第一衬垫221与第二衬垫222之间的仅一个导电迹线(第三导电迹线321或第四导电迹线322)。
图2展示沿着图1的半导体衬底1的线2-2截取的截面图。半导体衬底1包括绝缘层16、第一导电电路层12、第一导电凸块141、第二导电凸块142、第二导电电路层14，及多个导电通孔(例如，第一导电通孔441及第二导电通孔442)。
绝缘层16的材料包含绝缘材料或介电材料，例如聚丙烯。绝缘层16具有顶表面161、底表面162及多个通孔163。第一导电电路层12邻近于绝缘层16的顶表面161而安置，且从绝缘层16的顶表面161凹入。第一导电电路层12包括第一衬垫221、第三导电迹线321、第二衬垫222、第四导电迹线322、第一导电迹线111(图1)及第二导电迹线112(图1)。第一导电电路层12为经图案化的导电电路层。第一导电电路层12包含(例如)通过电镀工艺形成的铜，但可包含其它金属或金属合金。
在图2的实施例中，第一导电凸块141包括主要部分143、金属层部分641及突起部分223。突起部分223从第一衬垫221突出，金属层部分641安置在突起部分223上，且主要部分143安置在金属层部分641上。主要部分143、金属层部分641及突起部分223的宽度实质上相同。在此实施例中，突起部分223及第一衬垫221是一体地形成。也就是说，突起部分223及第一衬垫221是在蚀刻工艺之后同时形成。突起部分223的顶表面实质上与绝缘层16的顶表面161共平面，且高于第一衬垫221的顶表面221a。金属层部分641是(例如)通过蚀刻铜箔而形成。主要部分143为(例如)通过电镀工艺形成的铜，但可包含其它金属或金属合金。
第一导电凸块141的侧表面141a、第一衬垫221的顶表面221a及绝缘层16的侧表面16a一起界定第一容置空间151。因而，当安置在第一导电凸块141上的导电材料(例如，焊料)由于回焊工艺或由于其它原因而熔融且溢出时，第一容置空间151可提供缓冲器及容纳溢出导电材料的一部分。因此，导电材料将不会接触邻近的第三导电迹线321且造成短路。
而且在图2的实施例中，第二导电凸块142包括主要部分144、金属层部分642及突起部分224。突起部分224从第二衬垫222突出，金属层部分642安置在突起部分224上，且主要部分144安置在金属层部分642上。主要部分144、金属层部分642及突起部分224的宽度实质上相同。在此实施例中，突起部分224及第二衬垫222是一体地形成。也就是说，突起部分224及第二衬垫222是在蚀刻工艺之后同时形成。突起部分224的顶表面实质上与绝缘层16的顶表面161共平面，且高于第二衬垫222的顶表面222a。金属层部分642是(例如)通过蚀刻铜箔而形成。主要部分144为(例如)通过电镀工艺形成的铜，但可包含其它金属或金属合金。
第二导电凸块142的侧表面142a、第二衬垫222的顶表面222a及绝缘层16的侧表面16b一起界定第二容置空间152。因而，当安置在第二导电凸块142上的导电材料(例如，焊料)由于回焊工艺或由于其它原因而熔融且溢出时，第二容置空间152可提供缓冲器及容纳溢出导电材料的一部分。因此，导电材料将不会接触邻近的第四导电迹线322且造成短路。
金属层部分641及金属层部分642为第一金属层的一部分。
第二导电电路层14位于绝缘层16的底表面162上。在图2的实施例中，第二导电电路层14并不嵌入于绝缘层16的底表面162中。在此实施例中，第二导电电路层14为经图案化的导电电路层，其包含第二金属层18及第三金属层19或替代地由第二金属层18及第三金属层19组成。第二金属层18位于绝缘层16的底表面162上，且第三金属层19位于第二金属层18上。第二金属层18是(例如)通过蚀刻铜箔而形成。第三金属层19为(例如)通过电镀工艺形成的铜，但可包含其它金属或金属合金。第二导电电路层14包含第一焊球衬垫145及第二焊球衬垫146。
第一导电通孔441及第二导电通孔442位于通孔163中，延伸穿过绝缘层16，且电连接到第一导电电路层12及第二导电电路层14。在图2的实施例中，通孔163进一步延伸跨越第二金属层18的一部分。第一导电通孔441及第二导电通孔442可与第三金属层19同时形成。
在图2的实施例中，第一导电凸块141的宽度W131小于第一衬垫221的宽度W111，且第二导电凸块142的宽度W132小于第二衬垫222的宽度W112。在此实施例中，第一导电凸块141完全安置在第一衬垫221的顶表面221a上，且第二导电凸块142完全安置在第二衬垫222的顶表面22a上。也就是说，第一导电凸块141及第二导电凸块142并不接触绝缘层16的顶表面161。
在图2的实施例中，第一导电凸块141的宽度W131在约10微米到约40微米的范围内，且第一衬垫221的宽度W111在约20微米到约50微米的范围内。第一导电凸块141的宽度W131与第一衬垫221的宽度W111的比率为约0.5到约0.8，以补偿当第一导电凸块141形成于第一衬垫221上时的偏移。在此实施例中，第一导电凸块141的宽度W131与第一衬垫221的宽度W111之间的差为约10微米。另外，第二导电凸块142的宽度W132在约10微米到约40微米的范围内，且第二衬垫222的宽度W112在约20微米到约50微米的范围内。第二导电凸块142的宽度W132与第二衬垫222的宽度W112的比率为约0.5到约0.8，以补偿当第二导电凸块142形成于第二衬垫222上时的偏移。在此实施例中，第二导电凸块142的宽度W132与第二衬垫222的宽度W112之间的差近似地为约10微米。
另外，在图2的实施例中，第三导电迹线321与第一衬垫221之间的间隙G1在约5微米到约15微米的范围内，且第四导电迹线322与第二衬垫222之间的间隙G2在约5微米到约15微米的范围内。在此实施例中，第一衬垫221的宽度W111大于邻近的第三导电迹线321的宽度W141，且第二衬垫222的宽度W112大于邻近的第四导电迹线322的宽度W142。在此实施例中，第三导电迹线321的宽度W141的范围与第四导电迹线322的宽度W142的范围大致相同，在约8微米到约14微米的范围内。
在图2的实施例中，将高度H1界定为从绝缘层16的顶表面161到第一衬垫221的顶表面221a的距离，且将高度H2界定为从绝缘层16的顶表面161到第二衬垫222的顶表面222a的距离。高度H1及高度H2分别为第一容置空间151及第二容置空间152的深度。高度H1的范围与高度H2的范围大致相同，在约5微米到约10微米的范围内。将高度H11界定为从第一导电凸块141的顶表面到绝缘层16的顶表面161的距离，且将高度H12界定为从第二导电凸块142的顶表面到绝缘层16的顶表面161的距离。高度H11及高度H12的范围大致相同，在约10微米到约18微米的范围内。
图3展示根据本发明的一实施例的半导体封装结构3的部分截面图。半导体封装结构3包括半导体衬底1、半导体芯片2、导电材料271、272及模制化合物28。此实施例的半导体衬底1与图1及2的半导体衬底1相同。
半导体芯片2包括基底衬底21、第一I/O连接衬垫281、第二I/O连接衬垫282、保护层23、第一凸块下金属层(UBM)291、第二UBM 292、第一支柱261及第二支柱262。第一I/O连接衬垫281、第二I/O连接衬垫282及保护层23安置在基底衬底21的表面上。保护层23具有第一开口231及第二开口232以分别暴露第一I/O连接衬垫281及第二I/O连接衬垫282。第一UBM 291安置在保护层23上及第一开口231内以接触第一I/O连接衬垫281，且第二UBM 292安置在保护层23上及第二开口232内以接触第二I/O连接衬垫282。第一支柱261安置在第一UBM 291上，且第二支柱261安置在第二UBM 292上。
导电材料(例如，焊料)271安置在第一支柱261与第一导电凸块141之间以便电连接第一导电凸块141与半导体芯片2，且导电材料(例如，焊料)272安置在第二支柱262与第二导电凸块142之间以便电连接第二导电凸块142与半导体芯片2。在图3的实施例中，导电材料271、272分别沿着第一导电凸块141及第二导电凸块142的侧表面流动，且分别进入第一容置空间151及第二容置空间152中，使得导电材料271、272的一部分低于绝缘层16的顶表面161。也就是说，导电材料271、272被阻止流动跨越绝缘层16的顶表面161，因此将减少由于电连接到邻近的导电迹线而造成的短路的风险。在另一实施例中，精确地控制导电材料271及导电材料272的量，使得导电材料271不会接合到第一衬垫221的顶表面221a，且导电材料272不会接合到第二衬垫222的顶表面222a。模制化合物28安置在半导体衬底1与半导体芯片2之间以便保护第一支柱261及第二支柱262。
在图3的实施例中，第一衬垫221的宽度W111与第一UBM 291的宽度W121的比率在约1到约0.9的范围内，且第二衬垫222的宽度W112与第二UBM 292的宽度W122的比率在约1到约0.9的范围内。
在图3的实施例中，存在形成于第一导电凸块141与导电材料271之间的第一金属间化合物(IMC)层341，且还存在形成于第二导电凸块142与导电材料272之间的第二IMC层342。在此实施例中，第一IMC层341及第二IMC层342的材料包含铜，且优选为铜锡合金(例如，Cu6Sn5)。
图4展示根据本发明的一实施例的半导体封装3a的部分截面图。除了以下情形以外，半导体封装3a类似于图3中所说明的半导体封装3：更多的导电材料271安置在第一容置空间151中且更多的导电材料272安置在第二容置空间152中，这是因为溢出发生在焊料回焊工艺期间。也就是说，包含导电材料271、272的过量的材料，且导电材料271、272的过量材料将溢出到第一容置空间151及第二容置空间152中。然而，第一容置空间151及第二容置空间152提供缓冲器以容纳溢出材料，使得导电材料271、272将不会接触邻近的导电迹线(例如，第三导电迹线321或第四导电迹线322)且造成短路。另外，导电材料271接合到第一衬垫221的顶表面221a，且因此在第一衬垫221与导电材料271之间形成增加的大小的第一IMC层341。类似地，导电材料272接合到第二衬垫222的顶表面222a，且在第二衬垫222与导电材料272之间形成第二IMC层342。理论上，形成于导电材料271与第一衬垫221之间的第一IMC层341的较大区域(或类似地，形成于导电材料272与第二衬垫222之间的第二IMC层342的较大区域)改善接合强度。在另一实施例中，第一衬垫221的顶表面221a的一部分与导电材料271接合，而其另一部分暴露，且第二衬垫222的顶表面222a的一部分与导电材料272接合，而其另一部分暴露：也就是说，整个顶表面221a并不是被导电材料271覆盖且整个顶表面222a并不是被导电材料272覆盖。
图5展示根据本发明的一实施例的半导体封装结构3b的部分截面图。除了半导体芯片2经展示为移位达近似等于宽度G1的量以外，半导体封装3b类似于图4中所说明的半导体封装3a。在此实施例中，第一UBM 291的侧表面实质上与第三导电迹线321的侧表面共平面。这种情形归因于：第一导电凸块141及第二导电凸块142分别导引导电材料271、272沿着第一导电凸块141及第二导电凸块142的侧表面流动，且第一容置空间151及第二容置空间152在焊料回焊工艺期间分别为流动的导电材料271、272提供空间。因此，即使半导体芯片2的衬垫并未确切地与第一导电凸块141及第二导电凸块142对准，导电材料271、272也将不会接触邻近的导电迹线(例如，第三导电迹线321及第四导电迹线322)且造成短路。
图6为根据本发明的另一实施例的半导体衬底1a的截面图。除了第一导电凸块141及第二导电凸块142经移位以外，半导体衬底1a类似于图2中所说明的半导体衬底1。第一导电凸块141及第二导电凸块142覆盖绝缘层16的顶表面161的一部分。在此实施例中，金属层部分641、642覆盖绝缘层16的顶表面161的一部分。
第一衬垫221具有几何中心轴线221b，第一导电凸块141具有几何中心轴线141b，且在第一衬垫221的几何中心轴线221b与第一导电凸块141的几何中心轴线141b之间存在偏移O1。第二衬垫222具有几何中心轴线222b，第二导电凸块142具有几何中心轴线142b，且在第二衬垫222的几何中心轴线222b与第二导电凸块142的几何中心轴线142b之间存在偏移O2。第一容置空间151的宽度W151大于第一导电凸块141的宽度W131与第一衬垫221的宽度W111之间的差，且第二容置空间152的宽度W152大于第二导电凸块142的宽度W132与第二衬垫222的宽度W112之间的差。也就是说，归因于第一导电凸块141及第二导电凸块142的偏移，增加了第一容置空间151及第二容置空间152的宽度。
图7为根据本发明的另一实施例的半导体封装结构3c的部分截面图。半导体封装结构3c的半导体衬底1a与图6中所说明的半导体衬底1a相同。除了半导体衬底1a的第一导电凸块141及第二导电凸块142经移位以外，半导体结构3c类似于图4中所说明的半导体结构3a，且因此第一导电凸块141在绝缘层16的顶表面161的一部分之上延伸，且第二导电凸块142在绝缘层16的顶表面161的另一部分之上延伸。相对应地，金属层部分641、642还在绝缘层16的顶表面161的数部分之上延伸。如上文所陈述，第一容置空间151及第二容置空间152的宽度越大，越多的导电材料271、272将分别保持在第一容置空间151及第二容置空间152内。因此，导电材料271、272将不容易流动到邻近的导电迹线且造成短路，即使导电凸块141、142偏移且接触绝缘层16的顶表面161也如此。在一实施例中，导电材料271、272将不会覆盖全部第一导电凸块141及第二导电凸块142，且第一导电凸块141及第二导电凸块142的侧表面的数部分保持暴露。
图8为根据本发明的另一实施例的半导体衬底1b的截面图。除了在半导体衬底1b中不存在金属层641、642或突起部分223、224以外，半导体衬底1b类似于图2中所说明的半导体衬底1。也就是说，第一导电凸块141为直接安置在第一衬垫221上的单个元件，且第二导电凸块142为直接安置在第二衬垫222上的单个元件。
图9A、9B、9C、9D、9E、9F、9G、9H、9I及9J为制造期间的半导体封装的截面图，其说明根据本发明的一实施例的用于制造半导体封装的方法。参看图9A，提供载体10，且载体10具有第一表面101及第二表面102。接下来，在载体10的第二表面102上形成第一金属层64。在此实施例中，第一金属层64为铜箔，其具有第一表面643及第二表面644。将第一金属层64的第一表面643按压在载体10的第二表面102上或粘附到载体10的第二表面102。
参看图9B，在第一金属层64上形成第一导电电路层12。在此实施例中，第一导电电路层12可由电镀铜制成，其通过电镀工艺形成于第一金属层64的第二表面644上。第一导电电路层12为经图案化的导电电路层，其包含第一衬垫221、第三导电迹线321、第二衬垫222、第四导电迹线322。在此实施例中，第一衬垫221与第二衬垫222之间的距离小于25微米。
参看图9C，在第一导电电路层12及第一金属层64上形成绝缘层16。绝缘层16是由绝缘材料或介电材料制成，例如聚丙烯，其通过使用按压技术而附接到第一导电电路层12及第一金属层64。在按压之后，绝缘层16具有顶表面161及底表面162，其中绝缘层16的顶表面161接触第一金属层64的第二表面644，且第一导电电路层12嵌入于绝缘层16的顶表面161中。接下来，在绝缘层16的底表面162上形成第二金属层18。第二金属层18可为(例如)铜箔，其被按压到绝缘层16的底表面162或粘附到绝缘层16的底表面162。
参看图9D，形成多个通孔163以延伸穿过第二金属层18及绝缘层16，以便暴露第一导电电路层12的一部分。举例来说，使用激光钻孔形成通孔163，且暴露第一衬垫221及第二衬垫222。
参看图9E，对通孔163填充金属以形成第一导电通孔441及第二导电通孔442，且将第三金属层19(包含第一焊球衬垫145及第二焊球衬垫146)形成为第二金属层18、第一导电通孔441及第二导电通孔442上的经图案化的金属层。可在相同的工艺步骤期间形成第三金属层19、第一导电通孔441及第二导电通孔442。因此，第一导电通孔441及第二导电通孔442延伸穿过绝缘层16及第二金属层18，且接触第一导电电路层12。第三金属层19覆盖第二金属层18的一部分且暴露第二金属层18的另一部分。在此实施例中，第三金属19可为以电镀方式形成的电镀铜。
参看图9F，例如，通过蚀刻移除未被第三金属层19覆盖的第二金属层18以形成第二导电电路层14(图2)。第二导电电路层14包含第一焊球衬垫145及第二焊球衬垫146。在此实施例中，第二导电电路层14并不嵌入于绝缘层16的底表面162中。
参看图9G，例如，通过剥离移除载体10，以暴露第一金属层64。此时，第一金属层64、绝缘层16、第一导电电路层12、导电通孔221、第二金属层18及第三金属层19形成嵌入式电路衬底。
参看图9H，在第一金属层64上形成第一光致抗蚀剂层82，且在第三金属层19及绝缘层16的底表面162上形成第二光致抗蚀剂层83。在此实施例中，第一光致抗蚀剂层82可为干膜。在此实施例中，第二光致抗蚀剂层83可为干膜，并不具有任何开口，且完全覆盖第三金属层19及绝缘层16的底表面162。接下来，在第一光致抗蚀剂层82中形成多个开口821以暴露第一金属层64的一部分。在此实施例中，开口821的位置对应于第一衬垫221及第二衬垫222，也就是说，开口821的位置并不对应于第三导电迹线321及第四导电迹线322。
参看图9I，直接在第一金属层64上在开口821中形成多个主要部分143、144。在此实施例中，主要部分143、144可由电镀铜制成，以电镀的方式直接形成于暴露的第一金属层64上。在此实施例中，主要部分143、144中的每一者经定位以使得主要部分143、144分别位于通过第一衬垫221及第二衬垫222的圆周界定的侧向区域内。也就是说，主要部分143、144分别位于第一衬垫221及第二衬垫222的正上方。另外，主要部分143、144的形状(并非表面积)实质上分别与第一衬垫221及第二衬垫222的形状相同。
参看图9J，移除第一光致抗蚀剂层82及第二光致抗蚀剂层83。接下来，图9J中未展示，移除第一金属层64的暴露部分，从而留下金属层部分641及642。另外，例如，通过蚀刻移除分别未被主要部分143、144覆盖的第一衬垫221及第二衬垫222的部分，以形成突起部分223及224、第一容置空间151及第二容置空间152(图2)。现在，第一导电凸块141包括主要部分143、金属层部分641及突起部分223；且第二导电凸块142包括主要部分144、金属层部分642及突起部分224。因此，获得如图1及2中所展示的半导体衬底1。
如本文中所使用，术语“大致”、“实质上”、“实质”及“大约”用以描述及考虑小变化。当与事件或情形结合使用时，所述术语可以指其中事件或情形精确地发生的情况以及其中事件或情形极近似于发生的情况。举例来说，所述术语可以指小于或等于±10％，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或小于或等于±0.05％。
另外，有时在本文中按范围格式呈现量、比率及其它数值。应理解，此类范围格式是用于便利及简洁起见，且应灵活地理解，不仅包含明确地指定为范围限制的数值，而且包含涵盖于所述范围内的所有个别数值或子范围，如同明确地指定每一数值及子范围一般。
如果两个表面之间的位移仅为5微米、仅为10微米或仅为15微米，那么可认为所述两个表面为共平面的或实质上共平面的。
虽然已参考本发明的特定实施例描述及说明本发明，但这些描述及说明并不限制本发明。所属领域的技术人员应理解，在不脱离如通过所附权利要求书界定的本发明的真实精神及范围的情况下，可做出各种改变且可取代等效物。所述说明可能未必按比例绘制。归因于制造工艺及公差，本发明中的艺术再现与实际设备之间可存在区别。可存在并未特定说明的本发明的其它实施例。应将本说明书及图式视为说明性的而非限制性的。可做出修改，以使特定情况、材料、物质组成、方法或工艺适应于本发明的目标、精神及范围。所有此类修改希望属于所附权利要求书的范围内。虽然本文揭示的方法已参考按特定次序执行的特定操作加以描述，但应理解，可在不脱离本发明的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此，除非本文中特别指示，否则操作的次序及分组并非本发明的限制。

Claims (18)

1.一种半导体封装结构，其包括：
衬底，其包括：
绝缘层，其具有顶表面；
导电电路层，其从所述绝缘层的所述顶表面凹入，其中所述导电电路层包括至少一个衬垫及迹线，且所述迹线暴露于所述绝缘层；以及
导电凸块，其安置在所述至少一个衬垫上，其中所述导电凸块的侧表面、所述至少一个衬垫的顶表面及所述绝缘层的侧表面一起界定容置空间；
半导体芯片；以及
导电材料，其电连接所述导电凸块与所述半导体芯片；
其中所述导电材料的一部分安置在所述容置空间中，且
其中所述导电凸块包括主要部分、金属层部分及突起部分，所述突起部分从所述至少一个衬垫突出，所述金属层部分安置在所述突起部分上，所述主要部分安置在所述金属层部分上，且所述主要部分、所述金属层部分及所述突起部分的宽度相同。
2.根据权利要求1所述的半导体封装结构，其中所述导电凸块的宽度与所述至少一个衬垫的宽度的比率为0.5至0.8之间。
3.根据权利要求1所述的半导体封装结构，其中所述迹线安置在邻近于所述至少一个衬垫，所述半导体芯片包括凸块下金属UBM，且所述UBM的侧表面与所述迹线的侧表面共平面。
4.根据权利要求1所述的半导体封装结构，其中所述导电凸块安置在所述至少一个衬垫的圆周内。
5.根据权利要求1所述的半导体封装结构，其中所述导电凸块覆盖所述绝缘层的一部分。
6.根据权利要求1所述的半导体封装结构，其中所述容置空间的宽度大于所述导电凸块的宽度与所述至少一个衬垫的宽度之间的差。
7.根据权利要求1所述的半导体封装结构，其中所述导电凸块的宽度小于所述至少一个衬垫的宽度。
8.根据权利要求1所述的半导体封装结构，其中所述至少一个衬垫具有几何中心轴线，所述导电凸块具有几何中心轴线，且在所述至少一个衬垫的所述几何中心轴线与所述导电凸块的所述几何中心轴线之间存在偏移。
9.根据权利要求1所述的半导体封装结构，其中所述突起部分与所述至少一个衬垫是一体地形成。
10.一种半导体封装结构，其包括：
衬底，其包括：
绝缘层，其具有顶表面；
导电电路层，其从所述绝缘层的所述顶表面凹入，其中所述导电电路层包括至少一个第一衬垫及迹线，且所述迹线暴露于所述绝缘层；以及
第一导电凸块，其安置在所述第一衬垫上；
半导体芯片；以及
导电材料，其电连接到所述第一导电凸块及所述半导体芯片，
其中所述导电材料的一部分低于所述绝缘层的所述顶表面，且
其中所述第一导电凸块包括主要部分、金属层部分及突起部分，所述突起部分从所述第一衬垫突出，所述金属层部分安置在所述突起部分上，所述主要部分安置在所述金属层部分上，且所述主要部分、所述金属层部分及所述突起部分的宽度相同。
11.根据权利要求10所述的半导体封装结构，其中所述第一导电凸块的宽度小于所述第一衬垫的宽度，且所述第一导电凸块的侧表面、所述第一衬垫的顶表面及所述绝缘层的侧表面界定第一容置空间。
12.根据权利要求10所述的半导体封装结构，其中所述第一导电凸块的宽度与所述第一衬垫的宽度的比率为0.5至0.8之间。
13.根据权利要求10所述的半导体封装结构，其中所述衬底进一步包括第二导电凸块，且所述导电电路层进一步包括第二衬垫，其中所述第二导电凸块安置在所述第二衬垫上，所述第二导电凸块的宽度小于所述第二衬垫的宽度，所述第二导电凸块的侧表面、所述第二衬垫的顶表面及所述绝缘层的侧表面界定第二容置空间，且所述迹线安置在所述第一衬垫与所述第二衬垫之间。
14.根据权利要求10所述的半导体封装结构，其中所述第一导电凸块定位于所述第一衬垫的圆周内。
15.根据权利要求10所述的半导体封装结构，其中所述第一导电凸块覆盖所述绝缘层的一部分。
16.根据权利要求10所述的半导体封装结构，其中所述第一导电凸块的宽度小于所述第一衬垫的宽度。
17.根据权利要求10所述的半导体封装结构，其中所述第一衬垫具有几何中心轴线，所述第一导电凸块具有几何中心轴线，且在所述第一衬垫的所述几何中心轴线与所述第一导电凸块的所述几何中心轴线之间存在偏移。
18.根据权利要求10所述的半导体封装结构，其中所述突起部分与所述第一衬垫是一体地形成。
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