CN109390306A - 电子封装件 - Google Patents

电子封装件 Download PDF

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Publication number
CN109390306A
CN109390306A CN201710753942.0A CN201710753942A CN109390306A CN 109390306 A CN109390306 A CN 109390306A CN 201710753942 A CN201710753942 A CN 201710753942A CN 109390306 A CN109390306 A CN 109390306A
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China
Prior art keywords
electronic component
layer
route
electronic
clad
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Pending
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CN201710753942.0A
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English (en)
Inventor
何祈庆
蔡瀛洲
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN109390306A publication Critical patent/CN109390306A/zh
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    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/20641—Length ranges larger or equal to 100 microns less than 200 microns
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    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Abstract

一种电子封装件，包括有电子件、形成于该电子元件上的线路重布结构、结合至该线路重布结构上的导电柱以及供该导电柱接置的线路重布层，以供该电子元件透过该线路重布结构与导电柱而电性连接该线路重布层，使符合微小化需求的电子元件能进一步电性连接至外部装置。

Description

电子封装件
技术领域
本发明有关一种封装结构，尤指一种符合微小化需求的电子封装件。
背景技术
随着电子产业的发达，现今的电子产品已趋向轻薄短小与功能多样化的方向设计，半导体封装技术亦随之开发出不同的封装型态。为满足半导体装置的高集成度(Integration)、微型化(Miniaturization)以及高电路效能等需求，遂而发展出覆晶(Flipchip)接合封装技术。
覆晶接合封装技术为一种以晶片(或其他半导体结构)的作用面上形成多个金属凸块，以通过该些金属凸块使该晶片的作用面得电性连接至外部电子装置或封装基板，此种设计可大幅缩减整体封装件的体积。
如图1A及图1B所示，于现有覆晶式半导体封装件1的制程中，先将一半导体晶片11通过多个焊锡凸块13结合至一封装基板10上，再形成底胶12于该半导体晶片11与该封装基板10之间，以包覆该些焊锡凸块13。之后，于该封装基板10下侧植设多个焊球14以接置于电子产品的运算主板(major board)9上。
此外，目前在摩尔定律的驱策下，该半导体晶片11的尺寸朝微小化发展，且其线路更精细(fine pitch)。
惟，现有半导体封装件1中，用以电性连接该半导体晶片11与该运算主板9的封装基板10，其上线路尺寸及用以电性外接的焊球14的尺寸因制程限制无法依据摩尔定律的规划进行同于晶片尺寸等级的缩小。
此外，现有覆晶式半导体封装件1中，该半导体晶片11的侧面11c裸露于外界，使该半导体晶片11的结构强度较低，故于取放该半导体封装件1至适合位置以进行表面贴焊技术(Surface Mount Technology，简称SMT)时，易使该半导体晶片11产生裂损(Crack)，进而降低产品的良率。
另外，现有覆晶式半导体封装件1中，该封装基板10为一般有机基板或核心基板，其受限于制程，而无法制作线宽线距(pitch)小于130微米(um)的线路。
因此，如何克服上述现有技术的种种问题，实已成为目前业界亟待克服的难题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种电子封装件，使符合微小化需求的电子元件能进一步电性连接至外部装置。
本发明的电子封装件，包括：电子元件，其具有相对的作用面与非作用面；线路重布结构，其形成于该电子元件的作用面上，且电性连接该电子元件；多个导电柱，其结合并电性连接该线路重布结构；线路重布层，其结合并电性连接该多个导电柱，以令该导电柱一端连接该线路重布结构，且该导电柱的另一端连接该线路重布层；包覆层，其结合至该电子元件上；以及封装层，其结合至该包覆层上。
本发明亦提供一种电子封装件，包括：电子元件，其具有相对的作用面、非作用面及邻接该作用面与非作用面的侧面；包覆层，其结合于该电子元件的侧面；线路重布结构，其形成于该电子元件的作用面及该包覆层上，并电性连接该电子元件；多个导电柱，其结合并电性连接该线路重布结构；线路重布层，其结合并电性连接该多个导电柱，以令该导电柱一端连接该线路重布结构，且该导电柱的另一端连接该线路重布层；以及封装层，其形成于该线路重布层上且包覆该包覆层、线路重布结构与该多个导电柱。
前述的电子封装件中，该线路重布层还结合多个导电元件，以外接电子装置。例如，该线路重布层用以结合该导电元件的线距至少为150um。
前述的电子封装件中，该线路重布结构包含有一电性连接该电子元件的线路层，且该线路层结合该些导电柱，其中，该线路层用以结合该导电柱的线距至少为100um。
前述的电子封装件中，该电子元件还具有邻接该作用面与非作用面的侧面，且于该电子元件的侧面上接触形成有包覆层。例如，该包覆层直接接触该线路重布结构，以令该线路重布结构结合于该电子元件的作用面及该包覆层上；或者，该包覆层还形成于该电子元件的非作用面上。进一步，还包括形成于该线路重布层上以包覆该包覆层的封装层，且于一实施例中，该封装层还形成于该电子元件的非作用面上，又于一实施例中，该封装层直接接触该包覆层，或于一实施例中，该电子元件的非作用面或该包覆层的顶面外露出该封装层的上表面。
由上可知，本发明的电子封装件，主要通过两次扇出型(fan out)的线路重布层(RDL)的设计(即形成于电子元件上的线路重布结构及供该导电柱接置的线路重布层)，使具精细(fine pitch)线路而符合微小化需求的电子元件能通过该线路重布层接置及电性连接至外部电子装置。
此外，通过该包覆层与该封装层包覆该电子元件的外侧，以提升该电子元件的结构强度，故相较于现有技术，于后续进行表面贴焊技术或运送该电子封装件时，能避免该电子元件产生裂损，因而能提升产品的良率。
附图说明
图1A至图1B为现有覆晶式半导体封装件的制法的剖视示意图；
图2A至图2H为本发明的电子封装件的制法的剖视示意图；
图3A至图3C为对应图2H的不同实施例的剖视示意图；以及
图4A至图4C为本发明的线路重布层的制程的剖视示意图。
符号说明：
1 半导体封装件 10 封装基板
11 半导体晶片 12 底胶
13 焊锡凸块 14 焊球
2 电子封装件 2a 整版面基板
20 电子元件 20’ 间隔部
20a 作用面 20b 非作用面
20c 侧面 200 电极垫
201 钝化层 21 线路重布层
210 介电层 211 第一线路层
212 第二线路层 213 导电孔
214 保护层 22,32 封装层
23 导电元件 24 沟道
25,35 包覆层 26 切割路径
27 线路重布结构 271 线路层
273 保护保护层 28 导电体
280 导电材 281 导电柱
30 承载板 300 离形层
31 导电层 8 支撑件
80 离型层 9 运算主板。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、“第一”、“第二”、及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2A至图2H为本发明的电子封装件2的制法的剖视示意图。
如图2A所示，提供一整版面基板2a，该整版面基板2a包含多个电子元件20与位于相邻两电子元件20之间的间隔部20’。
于本实施例中，该电子元件20具有作用面20a与相对该作用面20a的非作用面20b，该作用面20a上具有多个电极垫200，并于该作用面20a与该些电极垫200上形成有一钝化层201，且令该些电极垫200外露出该钝化层201。
此外，该电子元件20为主动元件、被动元件或其组合者，且该主动元件为例如半导体晶片，而该被动元件为例如电阻、电容及电感。具体地，于本实施例中，该整版面基板2a为硅晶圆，且该电子元件20为半导体晶片。
如图2B所示，结合一支撑件8于该钝化层201上。于本实施例中，该钝化层201与该支撑件8之间可形成有离型层80，以利于后续剥离该支撑件8制程时避免造成损害，而能提升产品良率。
如图2C所示，以例如切割或蚀刻等方式形成沟道24于该间隔部20’上，使各该电子元件20形成有侧面20c，且该侧面20c邻接该作用面20a与非作用面20b。
于本实施例中，移除该间隔部20’的全部材质，以形成该沟道24，且可选择性执行研磨该电子元件20的非作用面20b的薄化制程。
如图2D所示，形成一包覆层25于该沟道24中与各该电子元件20上，以覆盖该电子元件20的侧面20c与非作用面20b。
于本实施例中，该包覆层25填满该沟道24，使该包覆层25环设于该电子元件20的侧面20c，且该包覆层25为绝缘材，如可固化的液态模封材(liquid molding compound)、干膜材(dry film)、光阻材(photoresist)或防焊层(solder mask)。
如图2E所示，移除该支撑件8与该离型层80，以外露该些电极垫200、该钝化层201及该包覆层25。
如图2F所示，进行线路重布层(Redistribution layer，简称RDL)制程，以接触形成一扇出型(fan out)的线路重布结构27于该钝化层201与该包覆层25上，且令该线路重布结构27电性连接该些电极垫200。接着，形成多个导电体28于该线路重布结构27上。
于本实施例中，该线路重布结构27包括一形成于该钝化层201上且电性连接该些电极垫200的线路层271、及一覆盖该线路层271且外露部分该线路层271的绝缘保护层273，以供该些导电体28形成于该线路层271的外露表面上而电性连接该线路层271。应可理解地，该线路重布结构27的层数可依需求设定，例如可形成至少一介电层(图略)于该钝化层201与该线路层271上，再形成其它线路层于该介电层上，之后才形成该绝缘保护层273于该介电层与最外侧线路层上。因此，可依实际需求设计该线路重布结构27的态样，并不限于上述。
此外，该线路层271用以结合该导电体28的线距(pitch)至少为100um。
又，于本实施例中，该导电体28为例如包含有如铜柱的导电柱281及设于该导电柱281端部上如焊锡的导电材280，或其它适合构造态样。
另外，该导电柱281的熔点与该导电材280的熔点不同，使该导电柱281的高度于回焊后保持不变，而该导电材280的高度于回焊后会改变。
具体地，一般覆晶式结构所用的焊锡材，如图1A所示的现有焊锡凸块13，因现有焊锡凸块13的体积及高度的平均值与公差控制不易，将难以达到细间距的要求。更详言之，当现有焊锡凸块13的体积平均值偏小或高度平均值偏低时，不利于封装的底胶(underfill)填充，易导致爆板；另一方面，当现有焊锡凸块13的体积平均值偏大或高度平均值偏高时，容易发生造成短路的接点桥接(bridge)现象，故当现有焊锡凸块13的体积及高度的公差大时，不仅接点容易产生缺陷，导致电性连接品质不良，且现有焊锡凸块13所排列成的栅状阵列(grid array)容易产生共面性(coplanarity)不良，导致接点应力(stress)不平衡而容易造成半导体晶片11损坏。
因此，本发明的导电体28通过铜材或熔点高于焊锡的材质制作该导电柱281，由于该导电柱281不会于回焊制程中改变形状，可控制该导电体28的高度与体积，故能避免上述现有焊锡凸块13所产生的缺失，有效达到细间距的要求。
如图2G所示，进行切单制程，沿切割路径26切割该整版面基板2a，以分离各该电子元件20。
于本实施例中，该切割路径26对应该沟道24的路径，且该切割路径26的宽度小于该沟道24的宽度，使该包覆层25保留于该电子元件20的侧面20c上。
如图2H所示，将该电子元件20以其作用面20a通过多个导电体28结合至一线路重布层21上，再形成一封装层22于该线路重布层21上以包覆该包覆层25与该些导电体28，使该封装层22直接接触该线路重布结构27的侧面与底面、该导电体28及该线路重布层21。
于本实施例中，该线路重布层21为扇出型(fan out)，且其上下侧分别用以结合及电性连接该些导电体28与多个导电元件23，以于后续制程中，通过该些导电元件23结合至一如电路板(如图1B所示的运算主板9)的电子装置上，其中，该线路重布层21用以结合该导电元件23的线距至少为150um。
此外，该些导电元件23可包含有焊锡凸块、铜柱、或其它适合构造态样。
又，于其它实施例中，如图3A所示，可通过移除部分封装层，使该包覆层25的顶面外露于该封装层32上表面，例如，该包覆层25的顶面齐平该封装层32上表面。或者，如图3B所示，可通过移除部分封装层与包覆层，使该电子元件20的非作用面20b外露于该封装层32上表面与该包覆层35的顶面，例如，该电子元件20的非作用面20b齐平该包覆层35的顶面及该封装层32上表面。
另外，如图3C所示，亦可先通过移除部分包覆层，使该电子元件20的非作用面20b外露于该包覆层35的顶面(例如，该电子元件20的非作用面20b齐平该包覆层35的顶面)，再以该封装层22包覆该电子元件20的非作用面20b与该包覆层35的顶面，使该电子元件20的非作用面20b接触该封装层22。
另一方面，该线路重布层21的制程如图3A至图3C所示。首先，于一承载板30的相对两侧上通过导电层31电镀形成第一线路层211，再以压合方式形成介电层210(或以光阻方式形成钝化层)于该承载板30上以覆盖该第一线路层211，之后形成第二线路层212于该介电层210上，并形成多个导电孔213于该介电层210中，使该些导电孔213电性连接该第一线路层211与该第二线路层212。接着，通过离形层300分离该承载板30两侧上的线路结构，并移除该导电层31。最后，于该介电层210的两侧上分别形成保护层214(或电性绝缘层)，并外露部分该第一线路层211与部分该第二线路层212，以完成该线路重布层21的制作。
本发明的电子封装件2透过两次扇出型(fan out)的线路重布层(RDL)制程(即该线路重布层21与该线路重布结构27的线路层271)，使微小化晶片(即符合微小化的规格需求的电子元件20)能通过该线路重布层21接置及电性连接至电子装置(如图1B所示的运算主板9)。
此外，通过该包覆层25与该封装层22包覆该电子元件20的双层保护设计，以提升该电子元件20的强度，故于后续进行表面贴焊技术或运送该电子封装件2时，能避免该电子元件20产生裂损，因而提升产品的良率。
本发明还提供一种电子封装件2，包括：一线路重布层21、一电子元件20、一包覆层25,35以及一封装层22,32。
所述的线路重布层21用以结合多个导电元件23。
所述的电子元件20具有相对的作用面20a与非作用面20b、及邻接该作用面20a与该非作用面20b的侧面20c。
所述的包覆层25,35直接接触地形成于该电子元件20的侧面20c上。
该电子元件20的作用面20a及包覆层25,35上形成有线路重布结构27，以令该电子元件20得以通过该线路重布结构27并透过多个导电体28结合至该线路重布层21上。
所述的封装层22,32形成于该线路重布层21上以包覆该包覆层25,35与该些导电体28。
于一实施例中，该线路重布层21通过该些导电元件23外接一电子装置，且该线路重布层21用以结合该导电元件23的线距至少为150um。
于一实施例中，该线路重布结构27包括一电性连接该电子元件20的线路层271，且该线路层271用以结合该导电体28的线距至少为100um。
于一实施例中，该包覆层25,35直接接触该线路重布结构27。
于一实施例中，该包覆层25还形成于该电子元件20的非作用面20b上。
于一实施例中，该封装层22还形成于该电子元件20的非作用面20b上。
于一实施例中，该封装层22,32直接接触该包覆层25,35。
综上所述，本发明的电子封装件，通过两次扇出型(fan out)的线路重布层(RDL)的设计(即形成于电子元件上的线路重布结构及供导电柱接置的线路重布层)，使具精细(fine pitch)线路而符合微小化需求的电子元件能通过该线路重布层接置及电性连接至外部电子装置。
此外，通过该包覆层与封装层的设计，以提升该电子元件的结构强度，因而能避免该电子元件产生裂损，故能提升该电子封装件之良率。
上述实施例仅用以例示性说明本发明之原理及其功效，而非用于限制本发明。任何所属领域技术人员均可在不违背本发明之精神及范畴下，对上述实施例进行修改。因此本发明之权利保护范围，应如权利要求书所列。

Claims (13)

1.一种电子封装件，其特征在于，该电子封装件包括：
电子元件，其具有相对的作用面与非作用面；
线路重布结构，其形成于该电子元件的作用面上，且电性连接该电子元件；
多个导电柱，其结合并电性连接该线路重布结构；
线路重布层，其结合并电性连接该多个导电柱，以令该导电柱一端连接该线路重布结构，且该导电柱的另一端连接该线路重布层；
包覆层，其结合至该电子元件上；以及
封装层，其结合至该包覆层上。
2.一种电子封装件，其特征在于，该电子封装件包括：
电子元件，其具有相对的作用面、非作用面及邻接该作用面与非作用面的侧面；
包覆层，其结合于该电子元件的侧面；
线路重布结构，其形成于该电子元件的作用面及该包覆层上，并电性连接该电子元件；
多个导电柱，其结合并电性连接该线路重布结构；
线路重布层，其结合并电性连接该多个导电柱，以令该导电柱一端连接该线路重布结构，且该导电柱的另一端连接该线路重布层；以及
封装层，其形成于该线路重布层上且包覆该包覆层、线路重布结构与该多个导电柱。
3.根据权利要求1或2所述的电子封装件，其特征在于，该线路重布层结合多个导电元件，以外接电子装置。
4.根据权利要求3所述的电子封装件，其特征在于，该线路重布层用以结合该导电元件的线距至少为150um。
5.根据权利要求1或2所述的电子封装件，其特征在于，该线路重布结构包含有电性连接该电子元件的线路层，且该线路层结合该些导电柱。
6.根据权利要求5所述的电子封装件，其特征在于，该线路层用以结合该导电柱的线距至少为100um。
7.根据权利要求1或2所述的电子封装件，其特征在于，该电子元件还具有邻接该作用面与非作用面的侧面，且于该电子元件的侧面上接触形成有包覆层。
8.根据权利要求7所述的电子封装件，其特征在于，该包覆层直接接触该线路重布结构，以令该线路重布结构结合于该电子元件的作用面及该包覆层上。
9.根据权利要求7所述的电子封装件，其特征在于，该包覆层还形成于该电子元件的非作用面上。
10.根据权利要求7所述的电子封装件，其特征在于，该封装层还形成于该线路重布层上以包覆该包覆层。
11.根据权利要求10所述的电子封装件，其特征在于，该封装层还形成于该电子元件的非作用面上。
12.根据权利要求10所述的电子封装件，其特征在于，该封装层直接接触该包覆层。
13.根据权利要求10所述的电子封装件，其特征在于，该电子元件的非作用面或该包覆层的顶面外露出该封装层的上表面。
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