CN110164781A - 电子封装件的制法 - Google Patents

电子封装件的制法 Download PDF

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CN110164781A
CN110164781A CN201810178827.XA CN201810178827A CN110164781A CN 110164781 A CN110164781 A CN 110164781A CN 201810178827 A CN201810178827 A CN 201810178827A CN 110164781 A CN110164781 A CN 110164781A
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scolding tin
preparation
bearing structure
tin end
packing piece
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CN110164781B (zh
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罗育民
郑子企
林长甫
余国华
黄祥华
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种电子封装件的制法，用于将电子元件借由导电凸块及形成于该导电凸块上的焊锡端结合于承载结构上，其中，该焊锡端不经回焊作业而接触该承载结构，使该导电凸块上能形成足量的焊锡端，以避免该焊锡端发生破裂或焊锡崩塌的问题。

Description

电子封装件的制法
技术领域
本发明有关一种封装结构的制法，尤指一种覆晶式电子封装件的制法。
背景技术
随着电子产业的发达，现今的电子产品已趋向轻薄短小与功能多样化的方向设计，半导体封装技术也随之开发出不同的封装型态。为满足半导体装置的高集成度(Integration)、微型化(Miniaturization)以及高电路效能等需求，遂而发展出覆晶(Flipchip)接合封装技术。
覆晶接合封装技术是在芯片(或其他半导体结构)的作用面上形成多个金属凸块，以借由该些金属凸块使该芯片的作用面得电性连接至外部电子装置或封装基板，此种设计可大幅缩减整体封装件的体积。
图1A至图1C为现有覆晶式半导体封装件1的制法的剖视示意图。
如图1A所示，于一半导体芯片11的作用面上设置如铜柱(Cu pillar)的金属凸块12，再于该金属凸块12上形成焊锡端(solder tip)，并回焊(reflow)该焊锡端，使该焊锡端熔融呈焊锡球13。接着，将该半导体芯片11及一封装基板10分别进行预热，此时，该封装基板10会呈翘曲(warpage)状态，如左右两侧上翘(如图1A所示的箭头方向A)。
如图1B所示，将该半导体芯片11借由该些焊锡球13结合至该封装基板10上。
如图1C所示，进行冷却作业，以于冷却过程中减缓该封装基板10的翘曲程度，使该封装基板10逐渐恢复为平坦状。
然而，现有半导体封装件1的制法中，于冷却过程中，若该焊锡球13的用量不足(如位于翘曲程度较大之处的焊锡球13)，会导致该焊锡球13发生破裂(crack)，如图1C所示的裂痕处k。
此外，若增加该焊锡球13的用量，该焊锡球13会于回焊该焊锡端时发生焊锡崩塌(solder collapse)的情况，导致焊锡材料包覆该金属凸块12的侧壁，致使于后续制程中会增加应力(stress)不平衡的可能性，因而提高该金属凸块12或该焊锡球13破裂的风险。
因此，如何克服上述现有技术的种种问题，实已成为目前业界亟待克服的难题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种电子封装件的制法，以避免该焊锡端发生破裂或焊锡崩塌的问题。
本发明的电子封装件的制法包括：提供一电子元件及一承载结构，其中，该电子元件上形成有多个导电凸块，且该导电凸块上形成有焊锡端；以及将该电子元件借由该焊锡端结合于该承载结构上，且该焊锡端不经回焊作业而接触该承载结构。
前述的制法中，该电子元件为覆晶式半导体芯片。
前述的制法中，还包括于该焊锡端接触该承载结构前，该承载结构进行预热作业，且该承载结构呈翘曲状态。进一步，于该焊锡端接触该承载结构后，进行冷却作业。
前述的制法中，还包括于该焊锡端接触该承载结构前，供热予该电子元件，使该焊锡端呈熔融状。
前述的制法中，还包括于该焊锡端接触该承载结构后，供热予该电子元件，使该焊锡端呈熔融状。
前述的制法中，该导电凸块或该焊锡端采用电镀或网印方式形成。
前述的制法中，该焊锡端的厚度大于或等于15um。
前述的制法中，该焊锡端的形状为圆柱形或立方体，且其表面可呈平面、弧面或不规则表面。
前述的制法中，该承载结构为包含有核心层与线路结构的封装基板、无核心层的线路结构、导线架或硅中介板。
由上可知，本发明的电子封装件的制法，主要令该焊锡端不经回焊作业即接触该承载结构，使该导电凸块上能形成足量的焊锡端，且可避免该焊锡端发生焊锡崩塌的问题，因而该焊锡端不会包覆该导电凸块的侧壁，故相比于现有技术，本发明的制法于后续制程中能避免应力不平衡的情况，因而能避免该导电凸块或该焊锡端破裂的情况发生。
此外，足量的焊锡端也能于热循环的过程中(如预热作业或加热作业)提供较佳的结合性，以避免该焊锡端于冷却过程中因焊锡量太少而发生破裂的问题。
附图说明
图1A至图1C为现有覆晶式半导体封装件的制法的剖视示意图；
图2A至图2C为本发明的电子封装件的制法的剖视示意图；以及
图2B’为图2A的后续步骤的另一实施例的剖视示意图。
符号说明：
1 半导体封装件
10 封装基板
11 半导体芯片
12 金属凸块
13 焊锡球
2 电子封装件
20 承载结构
200 电性接触垫
21 电子元件
21a 作用面
21b 非作用面
22 导电凸块
23,23’ 焊锡端
A,B 箭头方向
k 裂痕处
t 厚度。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、“第一”、“第二”、及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
请参阅图2A至图2C，其为本发明的电子封装件2的制法的剖视示意图。
如图2A所示，提供一电子元件21及一具有多个电性接触垫200的承载结构20，其中，该电子元件21上形成有多个导电凸块22，且该导电凸块22上形成有焊锡端23，并将该承载结构20进行预热作业，且该承载结构20于加热后呈翘曲(warpage)状态，如左右两侧上翘(如图2A所示的箭头方向B)。
于本实施例中，该电子元件21为主动元件、被动元件或其组合者，且该主动元件例如为半导体芯片，而该被动元件例如为电阻、电容及电感。本实施例中，该电子元件21为半导体芯片，其具有作用面21a与相对该作用面21a的非作用面21b，该作用面21a上具有多个电极垫，并于该些电极垫上形成有如铜柱的导电凸块22，且该些焊锡端23未进行回焊作业。
此外，其采用如电镀或网印(screen printing)形成该导电凸块22或该焊锡端23，且该焊锡端23的厚度t大于或等于15um。
又，该焊锡端23的形状可例如为圆柱形、立方体或其它各种形状，其表面可大致呈平面、弧面或不规则表面。
另外，该承载结构20例如为具有核心层与线路结构的封装基板(substrate)或无核心层(coreless)的线路结构，其于介电材上形成线路层，如扇出(fan out)型重布线路层(redistribution layer，简称RDL)。应可理解地，该承载结构20也可为其它可供承载如芯片等电子元件的承载单元，例如导线架(leadframe)或硅中介板(silicon interposer)，并不限于上述。
如图2B所示，供热予该电子元件21(如预热作业)，使该焊锡端23’呈熔融状，以令该熔融状的焊锡端23’直接接合于该承载结构20上的电性接触垫200，其中，该焊锡端23’不经回焊作业而接触该承载结构20(或该电性接触垫200)。
于本实施例中，该电子元件21与该承载结构20能于同一时间于不同处(或同处)进行预热作业。
如图2C所示，进行冷却作业，该承载结构20逐渐恢复为平坦状。
于另一实施例中，该电子元件21及该承载结构20均不先进行预热作业，而直接将该焊锡端23接触该电性接触垫200(如图2B’所示)，再供热予该电子元件21(如加热作业)，使该焊锡端23’呈熔融状以固接于该些电性接触垫200上(如图2C所示)。
因此，考量悉知焊锡端的电镀厚度有能力上限制，当焊锡端的厚度小于15um时，经回焊成弹头型(焊锡球)时会产生无法承受承载结构变形所导致焊锡球破裂问题，而当焊锡端的厚度大于或等于15um，经回焊成焊锡球时则会有倒塌风险；相对地，本发明的电子封装件2的制法令该焊锡端23不经回焊作业即接触该承载结构20，使该导电凸块22上能形成足量的焊锡端23，且可避免该焊锡端23发生焊锡崩塌的问题，因而该焊锡端23不会包覆该导电凸块22的侧壁，故相比于现有技术，本发明的制法于后续制程中能避免应力不平衡的情况，因而能避免该导电凸块22或该焊锡端23’破裂的情况发生。
此外，足量的焊锡端23也能于热循环(thermal cycling)的过程中(如预热作业或加热作业)提供较佳的结合性(bonding)，以避免该焊锡端23于冷却过程中因焊锡量太少而发生破裂的问题。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何所属领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (10)

1.一种电子封装件的制法，其特征为，该制法包括：
提供一电子元件及一承载结构，其中，该电子元件上形成有多个导电凸块，且该导电凸块上形成有焊锡端；以及
将该电子元件借由该焊锡端结合于该承载结构上，且该焊锡端不经回焊作业而接触该承载结构。
2.根据权利要求1所述的电子封装件的制法，其特征为，该电子元件为覆晶式半导体芯片。
3.根据权利要求1所述的电子封装件的制法，其特征为，该制法还包括于该焊锡端接触该承载结构前，对该承载结构进行预热作业，且该承载结构呈翘曲状态。
4.根据权利要求3所述的电子封装件的制法，其特征为，该制法还包括于该焊锡端接触该承载结构后，进行冷却作业。
5.根据权利要求1所述的电子封装件的制法，其特征为，该制法还包括于该焊锡端接触该承载结构前，供热予该电子元件，使该焊锡端呈熔融状。
6.根据权利要求1所述的电子封装件的制法，其特征为，该制法还包括于该焊锡端接触该承载结构后，供热予该电子元件，使该焊锡端呈熔融状。
7.根据权利要求1所述的电子封装件的制法，其特征为，该导电凸块或该焊锡端采用电镀或网印方式形成。
8.根据权利要求1所述的电子封装件的制法，其特征为，该焊锡端的厚度大于或等于15um。
9.根据权利要求1所述的电子封装件的制法，其特征为，该焊锡端的形状为圆柱形或立方体，且其表面可呈平面、弧面或不规则表面。
10.根据权利要求1所述的电子封装件的制法，其特征为，该承载结构为包含有核心层与线路结构的封装基板、无核心层的线路结构、导线架或硅中介板。
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