TWI485814B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI485814B
TWI485814B TW100137176A TW100137176A TWI485814B TW I485814 B TWI485814 B TW I485814B TW 100137176 A TW100137176 A TW 100137176A TW 100137176 A TW100137176 A TW 100137176A TW I485814 B TWI485814 B TW I485814B
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alignment mark
semiconductor device
semiconductor
electrode
electronic component
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TW100137176A
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TW201250944A (en
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Satoru Wakiyama
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Sony Corp
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Description

半導體裝置及其製造方法
本發明係關於一種其中形成用於覆晶連接之對準標記之半導體裝置及一種製造該半導體裝置之方法。
在相關技術中，在其中藉由焊料凸塊安裝半導體晶片之覆晶安裝中，藉由在半導體晶片上使用金屬線形成對準標記。此外，在覆晶安裝中，安裝半導體晶片，並用一側填滿樹脂填充所安裝半導體晶片之下部部分以改良可靠性。此外，為防止在電極(例如形成於安裝板或半導體裝置上之線接合墊)上發生由側填滿樹脂的流動所引起的樹脂污染，已研究出在用側填滿樹脂填充之一區域中形成一屏障之一技術(舉例而言，參考日本未經審查專利申請公開案第2005-276879號)。
在覆晶安裝中，提出一種在預先安裝半導體晶片之表面上形成覆蓋焊料凸塊之側填滿樹脂之方法。在此方法中，側填滿樹脂亦形成於半導體晶片之對準標記上。因此，在安裝時，必需透過側填滿樹脂來檢查對準標記之位置。然而，由於用一填料及類似物填充之側填滿樹脂的光學透明度頗低，因此難以識別形成於側填滿樹脂之下部側上之對準標記。
為此，難以在安裝半導體晶片時精確地對準其位置，且因此在彼連接錯誤中出現一問題，例如在凸塊之間發生短路。
根據本發明之實施例，期望提供能夠容易地辨識對準標記並使用對準標記精確地對準位置之一種半導體裝置及一種製造該半導體裝置之方法。
根據本發明之一項實施例，提供一種半導體裝置，其包含：一半導體元件；一墊電極，其形成於該半導體元件上；一對準標記，其形成於該半導體元件上；一連接電極，其形成於該墊電極上；及一側填滿樹脂，其經形成以覆蓋該連接電極。另外，該對準標記距該半導體元件之高度係大於該連接電極之高度。
此外，根據本發明之另一項實施例，提供一種半導體裝置，其包含：一第一電子組件，其具有上文所提及之半導體裝置之組態；一第二電子組件，其上安裝該第一電子組件。
此外，根據本發明之另一實施例，一種製造該半導體裝置之方法包含提供其上形成一半導體元件之一晶圓之一製程，及在該晶圓上形成一障壁層之一製程。另外，該方法亦包含在該障壁層上形成具有位於一經形成對準標記之一位置處之一開口部分之一第一抗蝕劑圖案之一製程，及藉由使用一電解電鍍方法在該第一抗蝕劑圖案之該開口部分中形成該對準標記之一製程。此外，該方法亦包含在移除該第一抗蝕劑圖案之後，形成具有位於該半導體元件之一連接電極之一位置處之一開口部分之一第二抗蝕劑圖案以便覆蓋該障壁層及該對準標記之一製程。該方法亦包含藉由使用該電解電鍍方法在該第二抗蝕劑圖案之該開口部分中形成該連接電極之一製程，及在該半導體元件上提供一側填滿樹脂以便覆蓋該連接電極之一製程。
此外，根據本發明之另一實施例，一種製造一半導體裝置之方法包含形成一第一電子組件之一製程，及提供具有一對準標記及一墊電極之一第二電子組件之一製程。另外，該方法亦包含藉由使用該對準標記將該第一電子組件之一位置與該第二電子組件之一位置對準，使該連接電極與該墊電極彼此電連接並將該第一電子組件安裝於該第二電子組件上之一製程。
在製造根據本發明之實施例之半導體裝置之該方法中，對準標記之高度設定為大於連接電極之高度。藉此，即使在其中形成側填滿樹脂以覆蓋連接電極之一狀態下，亦變得透過側填滿樹脂容易辨識對準標記。藉由執行具有對準標記之半導體裝置之覆晶連接，可精確地對準安裝位置，且因此可抑制連接錯誤。
此外，在製造根據本發明之實施例之半導體裝置之該方法中，藉由形成其高度大於連接電極之高度的對準標記，即使在形成側填滿樹脂以覆蓋連接電極之後，亦變得容易辨識該對準標記。因此，可製造能夠抑制連接錯誤之半導體裝置。
根據本發明之實施例，即使在形成側填滿樹脂以覆蓋連接電極時，亦可提供能夠容易辨識對準標記並容易執行精確位置對準之一半導體裝置。
在下文中，將闡述實施本發明之最佳模式之實例，但本發明之實施例並不限於以下實例。
另外，將按以下次序給出闡述。
1.　半導體裝置之第一實施例
2.　製造根據第一實施例之半導體裝置之方法
3.　半導體裝置之第二實施例
4.　製造根據第二實施例之半導體裝置之方法
5.　對準標記之經修改實例
1.　半導體裝置之第一實施例
將闡述根據本發明之一第一實施例之一半導體裝置。圖1展示根據本發明之第一實施例之該半導體裝置。將參考圖解說明其中凸塊電極19係形成於半導體元件11之墊電極12上之一部分之一剖視圖闡述圖1中所展示之半導體裝置10。
半導體裝置10在半導體元件11上具有墊電極12。此外，一鈍化層13係形成於整個表面上，除了半導體元件11上墊電極12之開口以外。
凸塊電極19係形成為連接至墊電極12上之外部裝置之電極。在每一凸塊電極19中，障壁層14係形成於墊電極12上。另外，一底凸塊金屬(UBM)16係提供於障壁層14上。此外，對應於墊電極12之一凸塊17係形成於UBM 16上。
此外，在半導體裝置10上，對準標記15係形成於鈍化層13上。另外，一側填滿樹脂18係形成於半導體元件11之整個表面上以便覆蓋凸塊電極19、對準標記15及鈍化層13。
每一墊電極12係由(例如)鋁製成且連接至半導體元件11中一晶圓之一電子電路(未展示)。此外，鈍化層13係形成於墊電極12之表面周圍，且障壁層14及UBM 16係形成於其中心中。
障壁層14經形成以覆蓋每一墊電極12之中心部分。此外，障壁層14係在形成於墊電極12之表面周圍的鈍化層上形成為其中形成UBM 16之部分的下部層。
此外，同樣地，障壁層14係形成於對準標記15之下部部分與鈍化層13之間，就像墊電極12之上部部分一樣。
舉例而言，障壁層14係由Ti、Cu或類似材料製成。
每一UBM 16係穿過上文所提及之障壁層14形成於墊電極12之中心部分中。此外，凸塊17係形成於UBM 16上。同樣地，凸塊電極19係形成於墊電極12上以便包含障壁層14、UBM 16及凸塊17。
UBM 16經形成以具有等於或大於由形成凸塊17之焊料腐蝕之某一位準之一厚度。舉例而言，UBM 16係由Ni、Ti、TiW、W、Cu及類似材料形成。通常，UBM 16形成為厚於障壁層14之厚度或墊電極12之厚度以防止形成於UBM 16上之一焊料合金(例如SnAg)擴散至由AlCu、Cu或類似材料製成之墊電極12中。
每一凸塊17係以自墊電極12突出之一球形形狀形成於UBM 16上。舉例而言，凸塊17係由一焊料合金(例如SnAg)形成。此外，該焊料合金可不形成為UBM 16上之凸塊17，且可在UBM 16上執行使用Ni/Au或類似材料之抗氧化處理。
對準標記15係形式化於半導體元件11上之預定位置處。複數個對準標記15經形成以便當半導體裝置10設定於一不同半導體裝置或一安裝板上時對準其位置，且係形成於半導體元件11上以校正半導體裝置10之變形等。
一般而言，形成於半導體元件及類似物上之該等對準標記係在針對墊電極12之相同製程中形成。因此，每一對準標記係形成於墊電極12之相同平面上以便具有與墊電極12之厚度相同的一厚度。
另一方面，根據該實施例之半導體裝置10之對準標記15係以一柱形形狀形成於鈍化層13上。對準標記15經形成以使得其距半導體元件11之表面的高度大於形成於墊電極12上之凸塊電極19。
此外，對準標記15之高度可等於側填滿樹脂18之高度。此外，較佳地，對準標記15之高度應形成為等於或小於側填滿樹脂18之高度。另外，即使在形成側填滿樹脂18之後，亦可容易地辨識對準標記15。因此，對準標記15之高度僅必須為在安裝半導體裝置10時並不引起一缺陷之高度。
在安裝半導體裝置10時，側填滿樹脂18經形成以具有在其處側填滿樹脂18覆蓋凸塊17之連接部分(亦即，半導體裝置10之安裝表面)之一厚度。舉例而言，較佳地，該側填滿樹脂距半導體元件11之表面的厚度應設定為等於或大於所安裝半導體裝置10之安裝表面與其上安裝半導體裝置10之半導體裝置或安裝板之安裝表面之間的距離。
藉由採用其中用側填滿樹脂18填充半導體裝置10與安裝板之間的間隙之一組態，可保證安裝可靠性。藉由形成其高度大於凸塊電極19之高度的對準標記15，即使在其表面塗佈有具有低透明度之側填滿樹脂18之半導體裝置10中亦變得容易識別對準標記15。
較佳地，對準標記15應由與底凸塊金屬(UBM) 16相同的材料形成，例如Ni、Ti、TiW、W及Cu。此外，該對準標記可由不同於UBM 16之材料的一材料形成。
另外，半導體裝置10中之對準標記15係形成於鈍化層13上，但可形成於墊電極12之相同平面上。在此情形下，對準標記15可由與墊電極12之材料相同的一材料形成
2.　製造根據第一實施例之半導體裝置之方法
接著，將闡述製造根據第一實施例之半導體裝置之方法。另外，在其中圖1中所展示之上文所提及之共同元件存在之情形下，將用相同元件符號及符號參考彼等元件，且將省略其詳細闡述。
另外，將參考形成於半導體晶圓上之複數個半導體元件之中的一個半導體元件之剖視圖給出以下闡述。
首先，如圖2A中所展示，提供其上形成具有墊電極12及鈍化層13之半導體元件11之一晶圓。然後，藉由在該晶圓之半導體元件11之表面上執行逆向濺鍍，移除墊電極12之表面上之氧化物膜及類似物。
接著，如圖2B中所展示，藉由使用該濺鍍方法，覆蓋墊電極12及鈍化層13，且在半導體元件11之整個表面上形成障壁層14。舉例而言，在障壁層14之形成中，藉由使用該濺鍍方法在墊電極12及鈍化層13上形成一Ti層。然後，同樣地，藉由使用該濺鍍方法，形成一Cu層以覆蓋該Ti層。
接著，如圖2C中所展示，在障壁層14上形成一光阻劑層21。藉由以(例如)一旋塗方法形成一經塗佈膜以便覆蓋晶圓之表面且隨後乾燥該經塗佈膜來形成光阻劑層21。此外，形成光阻劑層21以具有等於或大於形成於半導體元件11上之每一對準標記15之高度的一厚度。
接著，如圖2D中所展示，透過光罩22在光阻劑層21上執行曝光處理。光罩22採用一圖案來將曝光光照射在其中形成對準標記之區域上。然後，如圖2F中所展示，藉由在光阻劑層21上執行顯影處理，移除光阻劑層21之曝露部分，藉此在光阻劑層21上形成開口部分23。在半導體元件11上形成開口部分23以便對應於對準標記之形成位置。
接著，如圖3A中所展示，藉由使用該電解電鍍方法，在光阻劑層21之開口部分23上形成一鍍覆層，藉此形成對準標記15。藉此，在半導體元件11及障壁層14上形成對準標記15。
對準標記15係由一鍍覆層形成，例如Ni、Ti、TiW、W及Cu。形成對準標記15以具有等於或大於形成於半導體元件11之墊電極上之凸塊電極19之高度的一高度。
接著，如圖3B中所展示，自半導體元件11移除光阻劑層21。然後，如圖3C中所展示，在障壁層14上形成光阻劑層24。藉由以(例如)旋塗方法中形成一經塗佈膜以便覆蓋晶圓及對準標記15之表面且隨後乾燥該經塗佈膜膜來形成光阻劑層24。
接著，如圖3D中所展示，透過光罩25在光阻劑層24上執行曝光處理。光罩25採用一圖案來將曝光光照射在墊電極12之中心部分上。然後，藉由在曝光之後在光阻劑層24上執行顯影處理，移除曝露部分，藉此在光阻劑層24上形成開口部分26。
隨後，如圖4A中所展示，藉由使用該電解電鍍方法，在每一開口部分26中形成底凸塊金屬(UBM) 16。此外，如圖4B中所展示，藉由使用該電解電鍍方法在開口部分26中之UBM 16上形成一焊料層17A。類似於對準標記15，UBM 16係在電解電鍍中由Ni、Ti、TiW、W、Cu及類似材料形成。此外，焊料層17A係藉由電解電鍍使用焊料合金(例如SnAg)形成。
接著，在移除光阻劑層24之後，藉由濺鍍蝕刻移除曝露於半導體元件11之表面上之障壁層14。然後，如圖4C中所展示，藉由透過回銲熔化半導體層形成凸塊17。在障壁層14之移除中，藉由使用UBM 16及焊料層17A作為一遮罩，而使障壁層14在整個表面各處保留在UBM 16之下。此外，由於每一對準標記15充當一蝕刻遮罩，因此障壁層14亦保留在對準標記15之下。此外，藉由透過回銲將焊料層17A形成為球形凸塊17，每一凸塊電極19係由墊電極12上之UBM 16及凸塊17形成。
接著，如圖4D中所展示，在半導體元件11側上之晶圓之表面上形成側填滿樹脂18。側填滿樹脂18係使用含有(例如)側填滿樹脂之一應用液體藉由旋塗方法或藉由層壓側填滿樹脂之一乾燥膜形成。然後，藉由將半導體元件11切離晶圓且切割成單獨片來製造半導體裝置10。
如上文所闡述，藉由使用微影及電解電鍍，在其上形成半導體元件11之晶圓之表面上形成對準標記15、UBM 16及焊料凸塊17。形成每一對準標記15以使得其上表面之高度大於凸塊電極19距半導體元件11之形成表面之高度。此外，當半導體元件11之凸塊電極19之形成表面塗佈有側填滿樹脂18時，亦同時與其一起塗佈對準標記15。此時，形成側填滿樹脂18以具有等於或大於對準標記15之高度的一厚度。
另外，在根據上文所提及之實施例之製造方法中，在形成UBM 16及焊料層17A之製程之前形成對準標記15。然而，不特別限制形成UBM 16及焊料層17A之製程與形成對準標記15之製程的次序。若形成對準標記15、UBM 16及焊料層17A之製程在形成障壁層14之製程之後且在蝕刻障壁層14之製程之前，則可形成該等製程而不管其次序。
3.　半導體裝置之第二實施例
接著，將闡述根據本發明之一第二實施例之一半導體裝置。圖5A及5B展示根據本發明之第二實施例之該半導體裝置。圖5A及5B中所展示之半導體裝置包含一第一電子組件及一第二電子組件。該第一電子組件具有與圖1中所展示之根據第一實施例之半導體裝置相同的一組態。此外，該第二電子組件包含其上安裝根據第一實施例之半導體裝置之一半導體裝置。在下文中，將根據如下假設給出一闡述：根據第二實施例之半導體裝置係一半導體裝置30、形成為第一電子組件之半導體裝置係一第一半導體裝置10、且形成為第二電子組件之半導體裝置係一第二半導體裝置31。
將參考圖解說明其中用於電極連接之對準標記36及底凸塊金屬(UBM) 37係形成於半導體元件32上之一部分之一剖視圖闡述圖5A及5B中所展示之第二半導體裝置31。
第一半導體裝置10具有與上文所提及之第一實施例之組態相同的組態。另外，圖5A及5B僅展示必需闡述根據第二實施例之半導體裝置之一組態，其中省略形成於半導體元件11、鈍化層及類似物上之墊電極之組態。
如圖5A中所展示，在第一半導體裝置10中，對準標記15係形成於半導體元件11上之預定位置處。此外，每一凸塊電極19係由對應於半導體元件11之墊電極之位置處之UBM 16及凸塊17形成。此外，對準標記15之高度係大於半導體元件11上凸塊電極19之高度。然後，側填滿樹脂18經形成以覆蓋凸塊電極19及對準標記15。
此外，如圖5A中所展示，在第二半導體裝置31中，對準標記36係形成於半導體元件32之預定位置處。每一對準標記係藉由使用半導體元件32之佈線及類似物而形成於與墊電極相同的層上且位於大致等於半導體元件32之表面之高度的一高度處。此外，UBM 37係在對應於半導體元件32之墊電極之位置處形成為一連接墊。UBM 37可像第一半導體裝置10之UBM 16一樣組態且係由(例如)Ni、Ti、TiW、W、Cu及類似材料形成。
線接合墊39係形成於第二半導體裝置31之端部部分處。在每一線接合墊39中，第二半導體裝置31及外部電子器件係透過線接合電連接。
另外，在第二半導體裝置31中，類似於上文所提及之第一半導體裝置10，墊電極及鈍化層係形成於半導體元件32上。然而，僅展示必需闡述根據第二實施例之半導體裝置之組態，且將省略對其他組態之闡述。
如圖5A中所展示，在半導體裝置30中，第一半導體裝置10係安裝於第二半導體裝置31上。在半導體裝置30中，第一半導體裝置10及第二半導體裝置31經安置以使得其電極形成表面彼此相對。此外，在半導體裝置30中，第一半導體裝置10及第二半導體裝置31經安置以使得第一半導體裝置10之對準標記15的位置係與第二半導體裝置31之對準標記36的位置對準。
此外，第一半導體裝置10之每一凸塊17與第二半導體裝置31之UBM 37進行接觸，藉此電連接第一半導體裝置10與第二半導體裝置31。然後，透過側填滿樹脂18，機械連接第一半導體裝置10與第二半導體裝置31，且在側填滿樹脂18中形成凸塊電極19與UBM 37之間的連接。如上文所闡述，在半導體裝置30中，藉由填充第一半導體裝置10與第二半導體裝置31之間的間隙，藉由側填滿樹脂18形成一填料。
接著，將闡述根據第二實施例之半導體裝置中對準標記之高度。
在根據第二實施例之半導體裝置中，形成於第一半導體裝置中之墊電極與對準標記之間的高度差設定為小於形成於第二半導體裝置中之連接墊之高度。
在圖5B中所展示之半導體裝置30中，第一半導體裝置10之對準標記15之高度係大於第一半導體裝置10之凸塊電極19之高度。此處，凸塊電極19與對準標記15之間的高度差係由高度A表示。
此外，形成為第二半導體裝置31中之連接墊之UBM 37距元件表面之高度係由高度B表示。
在此情形下，對準標記15經形成以使得高度A等於高度B或高度A小於高度B。
由於高度A等於或小於高度B，因此即使在安裝時第一半導體裝置10與第二半導體裝置31之間平行時，亦可防止由凸塊之片所引起的連接錯誤發生。因此，當第一半導體裝置10安裝於第二半導體裝置31上時，凸塊電極19與UBM 37之間的連接可靠性得以改良。
此外，在其中高度A大於高度B之情形下，當第一半導體裝置10安裝於第二半導體裝置31上時，對準標記15與對準標記36在凸塊電極19與UBM 37之間連接之前彼此進行接觸。因此，連接錯誤發生。
另外，在其中每一凸塊形成為UBM 37上之第二半導體裝置31之一連接墊之情形下，自第二半導體裝置31之半導體元件表面至凸塊之高度設定為上文所提及之高度B。此外，類似於其中連接墊僅形成於墊電極上之情形，在其中第二半導體裝置31之連接墊係形成於與半導體元件表面大致相同的表面上之情形下，第一半導體裝置10之對準標記15及凸塊電極19係以大致相同高度形成。藉此，對準標記15經形成以使得高度A等於高度B，如上文所闡述。
此外，在上文所提及之實施例，使用半導體裝置31作為第二電子組件。然而，作為第二電子組件，舉例而言，可使用其上形成一佈線圖案以安裝半導體裝置之一安裝板。作為第一電子組件，可使用根據第一實施例之具有對準標記之上文所提及之半導體裝置，且作為第二電子組件，可提供與根據第一實施例之半導體裝置相容的對準標記及連接墊。在根據第二實施例之半導體裝置中，可適用該第二電子組件，而並不限於半導體裝置、安裝板及類似物。
此外，在根據第二實施例之上文所提及之半導體裝置中，高於連接電極之對準標記及側填滿樹脂係形成於第一半導體裝置之側上作為第一電子組件。然而，高於連接電極之對準標記及側填滿樹脂可形成於第二電子組件側上。藉由將側填滿樹脂提供於第一電子組件側上，在於形成於其中安裝形成於第二半導體裝置中之線接合墊之部分周圍的電極上形成側填滿樹脂時不存在由樹脂所引起的污染。因此，較佳地，高於連接電極之對準標記及側填滿樹脂應形成於第一電子組件側上。
4.　製造根據第二實施例之半導體裝置之方法
接著，將闡述製造根據第二實施例之半導體裝置之方法。另外，在對以下製造方法之闡述中，在其中圖1至5中所展示之上文所提及之共同元件存在之情形下，將用相同元件符號及符號參考彼等元件，且將省略其詳細闡述。
另外，將給出對藉由使用藉由第一實施例製造之上文所提及之半導體裝置製造根據第二實施例之半導體裝置之方法之以下闡述。
首先，如圖6A中所展示，提供藉由第一實施例製造之上文所提及之第一半導體裝置10作為第一電子組件。
此外，如圖6B中所展示，提供其上連接墊及對準標記36係形成於半導體元件32上之第二半導體裝置作為第二電子組件。第二半導體裝置31在半導體元件32上具有墊電極33及對準標記36。然後，在整個表面上形成一鈍化層34，除了半導體元件32上對準標記36及墊電極33之開口部分以外。此外，透過障壁層35在墊電極33上形成每一UBM 37。在UBM 37上形成凸塊38。亦即，在圖6B中所展示之第二半導體裝置31中，由墊電極33、障壁層35、UBM 37及凸塊38形成用於安裝第一半導體裝置10之連接墊。此外，在第二半導體裝置31中，在墊電極33之相同層上形成對準標記36。
然後，對準第一半導體裝置10與第二半導體裝置31之位置。藉由使用一相機40，讀取對準標記15及對準標記36之位置。隨後，調整第一半導體裝置10之位置以便對準第一半導體裝置10及第二半導體裝置31中對準標記15與36之位置。
接著，如圖6C中所展示，使第一半導體裝置10之凸塊17與第二半導體裝置31之凸塊38進行接觸，且然後向其施加配重(weighting)。此外，在施加配重時，藉由將該等凸塊加熱升至焊料之熔點或更高溫度，舉例而言，在其中凸塊17及38係由Sn-3.5Ag製成之情形下，藉由透過接合頭或載物台將該等凸塊加熱升至221℃之熔點或更高溫度，熔化且連接該等凸塊。藉此，藉由破壞形成凸塊17及38之焊料之一表面氧化物膜，形成基於無熔接連接之一連接部分41。透過連接部分41，電連接第一半導體裝置10與第二半導體裝置31。
此外，加熱並固化用其填充第一半導體裝置10及第二半導體裝置31之側填滿樹脂。側填滿樹脂18藉由將半導體元件11按壓於第二半導體裝置31上而使半導體元件11與半導體元件32彼此接合。藉由透過側填滿樹脂18使半導體元件彼此接合，機械連接可靠性得以改良。
透過以上製程，可製造根據第二實施例之半導體裝置30。
另外，當連接第一半導體裝置10與第二半導體裝置31時，可使對準標記15與對準標記36彼此直接進行接觸且可不使其進行接觸。
此外，在對以下製造方法之闡述中，替代用作第二電子組件之半導體裝置31，可使用安裝板，其中佈線圖案用於安裝半導體裝置及類似物。作為第一電子組件，可使用根據第一實施例之具有對準標記之上文所提及之半導體裝置，且作為第二電子組件，可提供與根據第一實施例之半導體裝置相容的對準標記及連接墊。
5.　對準標記之經修改實例 經修改實例1
接著，將闡述形成於上文所提及之半導體裝置中之對準標記的形狀。
較佳地，該對準標記應經形成以使得其形成於元件表面上之一平坦形狀不同於凸塊電極之平坦形狀。舉例而言，如圖7中所展示，通常，凸塊電極19係以一圓形形狀形成於半導體元件11上。因此，該對準標記係以不同於圓形形狀之一形狀形成。像對準標記42一樣，該對準標記係以藉由組合矩形形狀形成之一十字形狀形成。此外，像對準標記43一樣，形成一正方形對準標記。另外，舉例而言，該對準標記係以一星形形狀或一三角形形狀形成。
如上文所闡述，藉由使凸塊電極之形狀不同於形成於半導體裝置中之對準標記的形狀，舉例而言，即使在其中該凸塊電極進入用於辨識覆晶接合器之對準標記之一相機之視野中之一情形下，亦可防止錯誤辨識。
經修改實例2
此外，舉例而言，如圖8A中所展示，形成於半導體裝置中之對準標記可經形成以便環繞半導體元件之外週邊部分。
在圖8A中所展示之半導體裝置中，凸塊電極19係以一圓形形狀形成於半導體元件11上。然後，對準標記44經形成以環繞半導體元件11之外週邊部分。此外，形成於半導體裝置之凸塊電極19之側上之側填滿樹脂係形成於環繞半導體元件11之外週邊部分的對準標記44之內側。
對準標記44具有形成於半導體元件11之隅角部分上之一矩形對準標記44A及形成於對準標記44A之對角隅角處之一對準標記44B。此外，對準標記44具有連續形成於半導體元件11之外週邊部分上之一對準標記44C。
如圖8B中所展示，在安裝第二半導體裝置31時，對準標記44A及44B係與第二半導體裝置31之對準標記36對準。因此，較佳地，該等對準標記應以不同於凸塊電極19之形狀的一形狀形成。
此外，藉由環繞半導體元件11之外週邊部分，可抑制側填滿樹脂之流出。
當第一半導體裝置之安裝部分接近於電極部分(例如形成於該安裝部分周圍的線接合墊)時，側填滿樹脂開始流入至該安裝部分附近的電極部分中，藉此電極被樹脂污染。當在第二半導體裝置中藉由小型化該半導體裝置而使安裝部分與電極部分之間的距離短時，此往往導致一問題。
因此，藉由環繞半導體元件11之外週邊部分，可防止側填滿樹脂污染形成於第二半導體裝置31中之線接合墊39及類似物。然後，藉由減小第一電子組件(半導體裝置10)與第二電子組件(半導體裝置31)之間的元件面積差，可小型化該半導體裝置。
另外，如圖8B中所展示，即使在對準標記44與第二半導體裝置31之元件表面隔開時，亦可抑制側填滿樹脂18之流出。因此，對準標記15可不與第二半導體裝置31之元件表面直接進行接觸。
另外，舉例而言，根據該實施例之上文所提及之半導體裝置中之對準標記可連接至下部半導體元件之電極。舉例而言，上部半導體元件之對準標記係形成於上部半導體元件之電極上，且下部半導體元件之對準標記係形成於下部半導體元件之電極上。然後，在藉由在下部半導體元件之對準標記上形成焊料層而使該等半導體元件彼此連接時，可藉由透過焊料連接該等對準標記而在該等對準標記之間形成電連接。
本申請案含有與於2010年12月17日在日本專利局提出申請之日本優先權專利申請案JP 2010-282082中所揭示之內容相關的標的物，該申請案之全部內容藉此以引用方式併入。
熟習此項技術者應理解，可視設計要求及其他因素想出各種修改、組合、子組合及變更，只要其在隨附申請專利範圍及其等效範圍之範疇內。
10．．．第一半導體裝置
11．．．半導體元件
12．．．墊電極
13．．．鈍化層
14．．．障壁層
15．．．對準標記
16．．．底凸塊金屬
17．．．凸塊
17A．．．焊料層
18．．．側填滿樹脂
19．．．凸塊電極
21．．．光阻劑層
22．．．光罩
23．．．開口部分
24．．．光阻劑層
25．．．光罩
26．．．開口部分
30．．．半導體裝置
31．．．第二半導體裝置
32．．．半導體元件
33．．．墊電極
34．．．鈍化層
35．．．障壁層
36．．．對準標記
37．．．底凸塊金屬
38．．．凸塊
39．．．線接合墊
40．．．相機
41．．．連接部分
42．．．對準標記
43．．．對準標記
44．．．對準標記
44A．．．對準標記
44B．．．對準標記
44C．．．對準標記
圖1係圖解說明根據本發明之一第一實施例之一半導體裝置之一組態之一圖示；
圖2A至2E係圖解說明一種製造根據本發明之第一實施例之半導體裝置之方法之圖示；
圖3A至3D係圖解說明製造根據本發明之第一實施例之半導體裝置之方法之圖示；
圖4A至4D係圖解說明製造根據本發明之第一實施例之半導體裝置之方法之圖示；
圖5A至5B係圖解說明根據本發明之一第二實施例之一半導體裝置之一組態之圖示；
圖6A至6C係圖解說明一種製造根據本發明之第二實施例之半導體裝置之方法之圖示；
圖7係圖解說明根據本發明之第一實施例之半導體裝置之組態之一圖示；及
圖8A及8B係圖解說明根據本發明之第二實施例之半導體裝置之組態之圖示。
10．．．第一半導體裝置
11．．．半導體元件
12．．．墊電極
13．．．鈍化層
14．．．障壁層
15．．．對準標記
16．．．底凸塊金屬
17．．．凸塊
18．．．側填滿樹脂
19．．．凸塊電極

Claims (12)

  1. 一種半導體裝置，其包括：一半導體元件，其使用覆晶安裝而被安裝；一墊電極，其係於該半導體元件上；一對準標記，其自該墊電極所位於其上之該半導體元件延展；一連接電極，其係於該墊電極上；及一側填滿樹脂(underfill)，其覆蓋該連接電極，其中該對準標記距該半導體元件之一表面之一高度係大於該連接電極距該半導體元件之該表面之一高度，及形成該對準標記，使得在以覆晶安裝而放置該半導體元件之前，該對準標記自該半導體元件延展。
  2. 如請求項1之半導體裝置，其中該連接電極包含形成於該墊電極上之一底凸塊金屬及形成於該底凸塊金屬上之一焊料凸塊。
  3. 如請求項2之半導體裝置，其中該對準標記及該底凸塊金屬係由一相同材料形成。
  4. 如請求項1之半導體裝置，其中該對準標記之一形狀係不同於該連接電極之一形狀。
  5. 如請求項1之半導體裝置，其中該對準標記經形成以環繞該半導體元件之一外週邊部分。
  6. 如請求項1之半導體裝置，其中該側填滿樹脂進一步覆蓋該對準標記，及該側填滿樹脂之一厚度係大於該對準標記之該高度。
  7. 一種製造一半導體裝置之方法，其包括：提供其上形成一半導體元件之一晶圓；在該晶圓上形成一障壁層；在該障壁層上形成具有位於一經形成對準標記之一位置處之一開口部分之一第一抗蝕劑圖案；藉由使用一電解電鍍方法在該第一抗蝕劑圖案之該開口部分中形成該對準標記；在移除該第一抗蝕劑圖案之後，形成具有位於該半導體元件之一連接電極之一位置處之一開口部分之一第二抗蝕劑圖案以便覆蓋該障壁層及該對準標記；藉由使用該電解電鍍方法在該第二抗蝕劑圖案之該開口部分中形成該連接電極；及在該半導體元件上提供一側填滿樹脂以便覆蓋該連接電極。
  8. 一種半導體裝置，其包括：一第一電子組件，其包含：(i)一使用覆晶安裝而被安裝之半導體元件；(ii)一在該半導體元件上之墊電極；(iii)一自該墊電極所位於其上之該半導體元件延展之對準標記；(iv)一在該墊電極上之連接電極；及(v)一覆蓋該連接電極之側填滿樹脂，該對準標記距該半導體元件之一表面之一高度係大於該連接電極距該半導體元件之該表面之一高度，及形成該對準標記使得在以覆晶安裝而放置該半導體元件之前，該對準標記自該半導體元件延展；及 一第二電子組件，其上安裝該第一電子組件。
  9. 如請求項8之半導體裝置，其中該第一電子組件中該對準標記與該連接電極之間的一高度差係等於或小於該第二電子組件之一連接電極之一高度。
  10. 如請求項8之半導體裝置，其中該側填滿樹脂進一步覆蓋該對準標記，及該側填滿樹脂之一厚度係大於該對準標記之該高度。
  11. 如請求項8之半導體裝置，其中一間隙存在於該對準標記與該第二電子組件之間。
  12. 一種製造一半導體裝置之方法，其包括：形成一第一電子組件；提供具有一對準標記及一墊電極之一第二電子組件；及藉由使用該對準標記將該第一電子組件之一位置與該第二電子組件之一位置對準，使一連接電極與該墊電極彼此電連接並將該第一電子組件安裝於該第二電子組件上，其中該第一電子組件之該形成包含提供其上形成一半導體元件之一晶圓，在該晶圓上形成一障壁層，在該障壁層上形成具有位於該經形成對準標記之一位置處之一開口部分之一第一抗蝕劑圖案，藉由使用一電解電鍍方法在該第一抗蝕劑圖案之該開口部分中形成該對準標記，在移除該第一抗蝕劑圖案之後，形成具有位於該半 導體元件之一連接電極之一位置處之一開口部分之一第二抗蝕劑圖案以便覆蓋該障壁層及該對準標記，藉由使用該電解電鍍方法在該第二抗蝕劑圖案之該開口部分中形成該連接電極，及在該半導體元件上提供一側填滿樹脂以便覆蓋該連接電極。
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Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6207190B2 (ja) * 2013-03-22 2017-10-04 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9343386B2 (en) * 2013-06-19 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment in the packaging of integrated circuits
US9627229B2 (en) * 2013-06-27 2017-04-18 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming trench and disposing semiconductor die over substrate to control outward flow of underfill material
US9847317B2 (en) * 2014-07-08 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of packaging semiconductor devices and packaged semiconductor devices
DE102015105752B4 (de) * 2015-04-15 2021-08-05 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Halbleiteranordnung mit Reservoir für Markermaterial
KR20160142943A (ko) * 2015-06-03 2016-12-14 한국전자통신연구원 반도체 패키지 및 반도체 패키지의 제조 방법
TWI733690B (zh) * 2015-08-14 2021-07-21 新加坡商Ｐｅｐ創新私人有限公司 半導體加工方法
JP6786781B2 (ja) * 2015-09-25 2020-11-18 日亜化学工業株式会社 発光装置の製造方法
FR3041625B1 (fr) * 2015-09-29 2021-07-30 Tronics Microsystems Dispositif de fixation de deux elements tels qu'une puce, un interposeur et un support
KR102466959B1 (ko) * 2015-12-31 2022-11-11 엘지디스플레이 주식회사 유기 발광 표시 장치
US9633925B1 (en) * 2016-03-25 2017-04-25 Globalfoundries Inc. Visualization of alignment marks on a chip covered by a pre-applied underfill
CN110678958A (zh) * 2017-05-26 2020-01-10 夏普株式会社 半导体模块及其制造方法
US10636757B2 (en) * 2017-08-29 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit component package and method of fabricating the same
US11417569B2 (en) * 2017-09-18 2022-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure having integrated circuit component with conductive terminals of different dimensions
US10998480B2 (en) * 2018-09-19 2021-05-04 Facebook Technologies, Llc Light-emitting structure alignment preservation in display fabrication
US11171108B2 (en) * 2018-10-04 2021-11-09 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for manufacturing the same
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
KR102689648B1 (ko) * 2020-02-03 2024-07-30 삼성전자주식회사 댐 구조물을 갖는 반도체 패키지
DE102020135087A1 (de) 2020-03-27 2021-09-30 Samsung Electronics Co., Ltd. Halbleitergehäuse
JP7007607B2 (ja) * 2020-04-16 2022-01-24 日亜化学工業株式会社 発光装置の製造方法
CN113594119B (zh) * 2021-06-25 2024-05-14 苏州汉天下电子有限公司 半导体封装及其制造方法
CN113471061B (zh) * 2021-06-30 2024-07-16 颀中科技（苏州）有限公司 晶圆表面介电层的制备方法、晶圆结构及凸块的成型方法
KR20230060092A (ko) * 2021-10-27 2023-05-04 삼성전자주식회사 패키지 기판 및 이를 포함하는 반도체 패키지

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI228814B (en) * 2003-06-26 2005-03-01 United Microelectronics Corp Parasitic capacitance-preventing dummy solder bump structure and method of making the same
US20050067714A1 (en) * 2003-09-30 2005-03-31 Rumer Christopher L. Method and apparatus for a dual substrate package
TWI230993B (en) * 2004-02-09 2005-04-11 Au Optronics Corp Package alignment structure
US7413928B2 (en) * 2004-01-29 2008-08-19 Micron Technology, Inc. Die-wafer package and method of fabricating same
US20090134515A1 (en) * 2007-11-26 2009-05-28 Phoenix Precision Technology Corporation Semiconductor package substrate

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03214629A (ja) * 1990-01-18 1991-09-19 Fujitsu Ltd 半導体装置の製造方法
JP2000196051A (ja) 1998-12-25 2000-07-14 Matsushita Electric Ind Co Ltd 固体撮像素子およびその製造方法
JP2004079905A (ja) * 2002-08-21 2004-03-11 Sony Corp 半導体装置及びその製造方法
JP4415717B2 (ja) 2004-03-23 2010-02-17 ソニー株式会社 半導体装置及びその製造方法
JP4632690B2 (ja) * 2004-05-11 2011-02-16 スタンレー電気株式会社 半導体発光装置とその製造方法
JP4752586B2 (ja) * 2006-04-12 2011-08-17 ソニー株式会社 半導体装置の製造方法
JP5137320B2 (ja) * 2006-04-17 2013-02-06 株式会社テラミクロス 半導体装置およびその製造方法
JP2008109009A (ja) * 2006-10-27 2008-05-08 Sony Corp 半導体装置の製造方法
JP4889464B2 (ja) * 2006-12-08 2012-03-07 パナソニック株式会社 電子部品の実装方法
KR100809726B1 (ko) * 2007-05-14 2008-03-06 삼성전자주식회사 얼라인 마크, 상기 얼라인 마크를 구비하는 반도체 칩,상기 반도체 칩을 구비하는 반도체 패키지 및 상기 반도체칩과 상기 반도체 패키지의 제조방법들
JP2009010057A (ja) * 2007-06-27 2009-01-15 Toray Ind Inc 電子素子の実装方法
KR100927120B1 (ko) * 2007-10-29 2009-11-18 옵토팩 주식회사 반도체 소자 패키징 방법
US20090127703A1 (en) * 2007-11-20 2009-05-21 Fujitsu Limited Method and System for Providing a Low-Profile Semiconductor Assembly
US8877567B2 (en) * 2010-11-18 2014-11-04 Stats Chippac, Ltd. Semiconductor device and method of forming uniform height insulating layer over interposer frame as standoff for semiconductor die

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI228814B (en) * 2003-06-26 2005-03-01 United Microelectronics Corp Parasitic capacitance-preventing dummy solder bump structure and method of making the same
US20050067714A1 (en) * 2003-09-30 2005-03-31 Rumer Christopher L. Method and apparatus for a dual substrate package
US7413928B2 (en) * 2004-01-29 2008-08-19 Micron Technology, Inc. Die-wafer package and method of fabricating same
TWI230993B (en) * 2004-02-09 2005-04-11 Au Optronics Corp Package alignment structure
US20090134515A1 (en) * 2007-11-26 2009-05-28 Phoenix Precision Technology Corporation Semiconductor package substrate

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