CN106098667A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN106098667A
CN106098667A CN201610628679.8A CN201610628679A CN106098667A CN 106098667 A CN106098667 A CN 106098667A CN 201610628679 A CN201610628679 A CN 201610628679A CN 106098667 A CN106098667 A CN 106098667A
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Prior art keywords
semiconductor device
alignment mark
semiconductor element
electrode
semiconductor
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CN201610628679.8A
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CN106098667B (zh
Inventor
胁山悟
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Sony Corp
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Sony Corp
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Abstract

本发明涉及半导体器件。所述半导体器件包括：半导体元件；位于所述半导体元件上的钝化层；位于所述半导体元件上的焊盘电极，其通过所述钝化层中的开口暴露；位于所述焊盘电极和所述钝化层上的阻挡层；位于所述焊盘电极上的连接电极；以及从所述半导体元件延伸的对准标记，其中，所述钝化层的一部分位于所述对准标记与所述半导体元件之间，且所述阻挡层的一部分位于所述对准标记与所述钝化层之间。根据本发明，能够提供能够容易辨认出对准标记并能够容易精确地对准位置的半导体器件。

Description

半导体器件
本申请是申请日为2011年12月8日、发明名称为“半导体器件及其制造方法”的申请号为201110405251.4专利申请的分案申请。
技术领域
本发明涉及形成有用于连接倒装芯片的对准标记的半导体器件，以及该半导体器件的制造方法。
背景技术
在现有技术中，在通过焊料凸块来安装半导体芯片的方式进行的倒装芯片安装中，通过使用金属布线在半导体芯片上形成对准标记。而且，在倒装芯片安装中，安装半导体芯片，并在所安装的半导体芯片的下部填充用于提高可靠性的底部填充树脂(underfillresin)。此外，为了避免形成在安装板或者半导体器件上的电极(例如，布线结合焊盘)上出现由于底部填充树脂的流动引起的树脂污染，目前已研发出在填充有底部填充树脂的区域中形成坝的技术(例如，参考日本未审查专利申请公开公布No.2005-276879)。
对于倒装芯片安装，提出了如下一种方法：该方法在预先安装有半导体芯片的表面上形成覆盖焊料凸块的底部填充树脂。在该方法中，底部填充树脂还形成在半导体芯片的对准标记上。因此，在安装时，需要透过底部填充树脂检查对准标记。然而，由于填充有填充剂等的底部填充树脂的透光性较低，所以难以辨认出形成在底部填充树脂的下侧上的对准标记。
因此，在安装半导体芯片时，难以精确地对准它们的位置，并由此出现由连接错误的发生导致的问题(例如，凸块之间的短路)。
发明内容
本发明的目的在于提供能够容易地辨认出对准标记并使用这些对准标记来精确地对准位置的半导体器件及其制造方法。
本发明的一个实施例提供了一种半导体器件，所述半导体器件包括：半导体元件；焊盘电极，其形成在所述半导体元件上；对准标记，其形成在所述半导体元件上；连接电极，其形成在所述焊盘电极上；以及底部填充树脂，其形成为覆盖所述连接电极。此外，所述对准标记从所述半导体元件开始的高度大于所述连接电极的高度。
此外，本发明的另一实施例提供了一种半导体器件，所述半导体器件包括：第一电子部件，其具有上述实施例的半导体器件的结构；第二电子部件，在所述第二电子部件上安装所述第一电子部件。
此外，本发明的又一实施例提供了一种半导体器件的制造方法，所述制造方法包括以下步骤：设置晶片，所述晶片上形成有半导体元件；在所述晶片上形成阻挡层；在所述阻挡层上形成具有开口部的第一抗蚀剂图案；通过使用电镀法，在所述第一抗蚀剂图案的所述开口部中形成对准标记；在除去所述第一抗蚀剂图案之后，形成具有开口部的第二抗蚀剂图案，所述第二抗蚀剂图案覆盖所述阻挡层和所述对准标记；通过使用电镀法，在所述第二抗蚀剂图案的所述开口部中形成连接电极；并且在所述半导体元件上设置底部填充树脂，所述底部填充树脂覆盖所述连接电极。
此外，本发明的再一实施例提供了一种半导体器件的制造方法，所述制造方法包括以下步骤：形成具有第一对准标记和连接电极的第一电子部件；设置具有第二对准标记和焊盘电极的第二电子部件；并且通过使用所述第一对准标记和所述第二对准标记将所述第一电子元件的位置与所述第二电子元件的位置对准、将所述连接电极与所述焊盘电极互相电连接、以及将所述第一电子部件安装在所述第二电子部件上。
在本发明的实施例的半导体器件的制造方法中，对准标记的高度设置成大于连接电极的高度。从而，即使底部填充树脂形成为覆盖连接电极的情况下，也容易透过底部填充树脂辨认出对准标记。通过对具有对准标记的半导体器件进行倒装芯片连接，能够精确地对准安装位置，从而能够阻止连接错误。
而且，在本发明实施例的半导体器件的制造方法中，通过形成高度大于连接电极的对准标记，即使在形成覆盖连接电极的底部填充树脂之后，仍然容易辨认出对准标记。因而，可以制造能够阻止连接错误的半导体器件。
根据本发明的实施例，即使当底部填充树脂形成为覆盖连接电极时，也能够提供能够容易辨认出对准标记并能够容易精确地对准位置的半导体器件。
附图说明
图1表示本发明第一实施例的半导体器件的结构；
图2A至图2E表示本发明第一实施例的半导体器件的制造方法；
图3A至图3D表示本发明第一实施例的半导体器件的制造方法；
图4A至图4D表示本发明第一实施例的半导体器件的制造方法；
图5A和图5B表示本发明第二实施例的半导体器件的结构；
图6A至图6C表示本发明第二实施例的半导体器件的制造方法；
图7表示本发明第一实施例的半导体器件的结构；
图8A和图8B表示本发明第二实施例的半导体器件的结构。
具体实施方式
下面，将说明用于实施本发明的最佳方式的示例，但是本发明的实施例不限于下列示例。
此外，将按如下顺序进行说明。
1.半导体器件的第一实施例
2.第一实施例的半导体器件的制造方法
3.半导体器件的第二实施例
4.第二实施例的半导体器件的制造方法
5.对准标记的修改示例
1.半导体器件的第一实施例
下面将说明本发明第一实施例的半导体器件。图1表示本发明第一实施例的半导体器件。将参照半导体元件11上的焊盘电极12上形成有凸块电极19的部分的剖面图来说明图1所示的半导体器件10。
半导体器件10在半导体元件11上具有焊盘电极12。另外，在半导体元件11上除焊盘电极12的开口之外的整个表面上形成钝化层13。
凸块电极19在焊盘电极12上形成为与外部设备相连接的电极。在每个凸块电极19中，阻挡层14形成在焊盘电极12上。此外，在阻挡层14上设置有凸块底部金属层(underbump metal，UBM)16。而且，在UBM 16上形成有与焊盘电极12相对应的凸块17。
而且，在半导体器件10中，在钝化层13上形成有对准标记15。此外，底部填充树脂18在半导体元件11的整个表面上形成为覆盖凸块电极19、对准标记15和钝化层13。
在半导体元件11中，每个焊盘电极12例如是由铝制成，并且连接到晶片的电子电路(图中未示出)。而且，钝化层13形成在焊盘电极12的表面周围，而阻挡层14和UBM 16形成在焊盘电极12的表面中部。
阻挡层14形成为覆盖每个焊盘电极12的中央部分。而且，阻挡层14形成为如下部分的下层，该部分是形成在焊盘电极12的表面周围的钝化层上形成有UBM 16的部分。
而且，如同在焊盘电极12的上部，阻挡层14也形成在对准标记15的下部与钝化层13之间。
阻挡层14例如是由Ti或Cu等制成。
每个UBM 16通过上述阻挡层14形成在焊盘电极12的中央部分。而且，在UBM 16上形成凸块17。这样，在焊盘电极12上形成凸块电极19，凸块电极19包括阻挡层14、UBM 16和凸块17。
鉴于受到用于形成凸块17的焊料的侵蚀，UBM 16形成为具有等于或大于一定级别的厚度。UBM 16例如是由Ni、Ti、TiW、W、Cu等形成。通常，UBM 16形成为厚度比阻挡层14或者焊盘电极12厚，以避免诸如形成在UBM 16上的SnAg等焊料合金扩散到由AlCu、Cu等制成的焊盘电极12中。
每个凸块17在UBM 16上形成为具有从焊盘电极12突出的球形。凸块17例如是由诸如SnAg等焊料合金形成。此外，也可不在UBM 16上形成作为凸块17的焊料合金，可以在UBM16上使用Ni/Au等进行抗氧化处理(antioxidant treatment)。
在半导体元件11上的预设位置处形成对准标记15。形成多个对准标记15是为了在将半导体器件10设置在不同的半导体器件或者安装板上时对准半导体器件10的位置，而且多个对准标记15形成在半导体元件11上，以便纠正半导体器件10的扭曲等。
通常，形成在半导体元件等元件上的对准标记与焊盘电极12在相同的过程中形成。因而，每个对准标记在与焊盘电极12相同的平面上形成为具有与焊盘电极12相同的厚度。
另一方面，本实施例中，半导体器件10的对准标记15在钝化层13上形成为柱形。对准标记15形成为其从半导体元件11表面开始的高度大于形成在焊盘电极12上的凸块电极19的高度。
而且，对准标记15高度可等于底部填充树脂18的高度。而且，优选地，对准标记15的高度应当形成为等于或小于底部填充树脂18的高度。此外，即使在形成底部填充树脂18之后，仍然能够容易地辨认出对准标记15。因此，对准标记15的高度只要在安装半导体器件10时不会导致缺陷即可。
在安装半导体器件10时，底部填充树脂18形成为一定厚度，使得具有该厚度的底部填充树脂18覆盖凸块17的连接部，即覆盖半导体器件10的安装表面。例如，优选地，底部填充树脂的从半导体元件11的表面开始的厚度应当设置成等于或大于被安装的半导体器件10的安装表面与用于上部安装半导体器件10的半导体器件或安装板的安装表面之间的距离。
通过采用在半导体器件10与安装板之间的空隙中填充有底部填充树脂18的结构，能够保证安装的可靠性。通过形成高度大于凸块电极19的对准标记15，即使在表面涂布有低透明度的底部填充树脂18的半导体器件10中，仍然能够容易辨认出对准标记15。
优选地，对准标记15应当由与凸块底部金属层(UBM)16相同的材料(例如，Ni、Ti、TiW、W和Cu)形成。此外，对准标记也可由与UBM 16不同的材料形成。
此外，半导体器件10中的对准标记15形成在钝化层13上，但也可与焊盘电极12形成在相同的平面上。在这种情况下，可以用和焊盘电极12相同的材料形成对准标记15。
2.第一实施例的半导体器件的制造方法
下面将说明第一实施例的半导体器件的制造方法。此外，在存在图1所示的上述相同元件的情况下，将用相同的附图标记表示那些元件，并省略其详细说明。
此外，将参照形成在半导体晶片上的多个半导体元件中的一个半导体元件的剖面图进行如下说明。
首先，如图2A所示，设置上面形成有半导体元件11的晶片，半导体元件11具有焊盘电极12和钝化层13。然后，通过在晶片上的半导体元件11的表面上进行逆溅射(reversesputtering)，除去焊盘电极12的表面上的氧化膜等。
接下来，如图2B所示，通过使用溅射法来覆盖焊盘电极12和钝化层13，在半导体元件11的整个表面上形成阻挡层14。在形成阻挡层14时，例如，通过使用溅射法，在焊盘电极12和钝化层13上形成Ti层。然后，同样使用溅射法，形成覆盖Ti层的Cu层。
接下来，如图2C所示，在阻挡层14上形成光致抗蚀剂层21。通过使用例如旋转涂敷法形成覆盖晶片的表面的涂膜，并随后干燥该涂膜，由此形成光致抗蚀剂层21。而且，光致抗蚀剂层21形成的厚度等于或者大于形成在半导体元件11上的每个对准标记15的高度。
接下来，如图2D所示，通过光掩模22在光致抗蚀剂层21上进行曝光处理。光掩模22采用的图案使曝光光线对待形成有对准标记的区域进行照射。然后，如图2F所示，通过在光致抗蚀剂层21上进行显影处理，除去光致抗蚀剂层21的被曝光部分，从而在光致抗蚀剂层21上形成开口部23。开口部23在半导体元件11上形成为与对准标记的形成位置相对应。
接下来，如图3A所示，通过使用电镀法，在光致抗蚀剂层21的开口部23上形成镀层，由此形成对准标记15。从而，在半导体元件11和阻挡层14上形成对准标记15。
对准标记15是由诸如Ni、Ti、TiW、W和Cu等镀层形成。对准标记15所形成的高度等于或大于形成在半导体元件11的焊盘电极上的凸块电极19的高度。
接下来，如图3B所示，从半导体元件11除去光致抗蚀剂层21。然后，如图3C所示，在阻挡层14上形成光致抗蚀剂层24。通过使用例如旋转涂敷法形成覆盖晶片的表面和对准标记15的涂膜，并随后干燥该涂膜，由此形成光致抗蚀剂层24。
接下来，如图3D所示，利用光掩模25在光致抗蚀剂层24上进行曝光处理。光掩模25所采用的图案使曝光光线对焊盘电极12的中央部分进行照射。然后，在曝光后，通过在光致抗蚀剂层24上进行显影处理，除去被曝光部分，从而在光致抗蚀剂层24上形成开口部26。
然后，如图4A所示，通过使用电镀方法，在每个开口部26中形成凸块底部金属层(UBM)16。此外，如图4B所示，通过使用电镀法，在开口部26内的UBM 16上形成焊料层17A。与对准标记15类似，UBM 16是通过电镀法并由Ni、Ti、TiW、W、Cu等形成。而且，焊料层17A是通过使用诸如SnAg等焊料合金的电镀方法形成。
接下来，在除去光致抗蚀剂层24之后，通过溅射刻蚀(sputter etching)除去暴露在半导体元件11的表面上的阻挡层14。然后，如图4C所示，通过回流(reflow)使焊料层熔融，从而形成凸块17。在除去阻挡层14时，通过使用UBM 16和焊料层17A作为掩模，使得在整个表面上仅保留UBM 16下方的阻挡层14。此外，由于每个对准标记15充当刻蚀掩模，所以阻挡层14也保留在对准标记15的下方。而且，通过回流使焊料层17A形成为球形凸块17，由焊盘电极12上形成由UBM 16和凸块17组成的每个凸块电极19。
接下来，如图4D所示，在晶片的半导体元件11一侧的表面上形成底部填充树脂18。通过使用例如含有底部填充树脂的涂覆液的旋转涂敷法，或者通过层叠底部填充树脂的干燥膜，来形成底部填充树脂18。
如上所述，使用光刻法和电镀法，在形成有半导体元件11的晶片的表面上形成对准标记15、UBM 16和焊料凸块17。每个对准标记15形成为其上表面的高度大于凸块电极19的从半导体元件11的形成表面开始的高度。而且，当半导体元件11的凸块电极19的形成表面涂布有底部填充树脂18时，对准标记15同时也涂布有底部填充树脂18。此时，底部填充树脂18所形成的厚度等于或者大于对准标记15的高度。
此外，在上述实施例的制造方法中，在UBM 16和焊料层17A的形成过程之前形成对准标记15。然而，没有特别限制UBM 16和焊料层17A的形成过程和对准标记15的形成过程的顺序。如果对准标记15、UBM 16和焊料层17A的形成过程在阻挡层14的形成过程之后并且在阻挡层14的刻蚀过程之前，可以不分先后地实施对准标记15、UBM 16和焊料层17A的形成过程。
3.半导体器件的第二实施例
下面将说明本发明第二实施例的半导体器件。图5A和图5B表示本发明第二实施例的半导体器件。图5A和图5B所示的半导体器件包括第一电子部件和第二电子部件。第一电子部件的结构与图1所示的第一实施例的半导体器件的结构相同。而且，第二电子部件包括用于上面安装第一实施例的半导体器件的半导体器件。下面，基于如下假设进行说明：第二实施例的半导体器件是半导体器件30，形成为第一电子部件的半导体器件是第一半导体器件10，形成为第二电子部件的半导体器件是第二半导体器件31。
将参照半导体元件32上形成有对准标记36和用于电极连接的凸块底部金属层(UBM)37的部分的剖面图来说明如图5A和图5B所示的第二半导体器件31。
第一半导体器件10具有与上述第一实施例相同的结构。此外，图5A和图5B仅示出了用于说明第二实施例的半导体器件所需要的结构，其中，省略了形成在半导体元件11上的钝化层和焊盘电极等的结构。
如图5A所示，在第一半导体器件10中，在半导体元件11上的预设位置处形成对准标记15。而且，在与半导体元件11的焊盘电极相对应的位置处形成由UBM 16和凸块17组成的每个凸块电极19。此外，对准标记15的高度大于半导体元件11上的凸块电极19的高度。然后，底部填充树脂18形成为覆盖凸块电极19和对准标记15。
而且，如图5A所示，在第二半导体器件31中，在半导体元件32的预设位置处形成有对准标记36。通过利用半导体元件32的布线等，在与焊盘电极相同的层上形成每个对准标记，并且每个对准标记具有与半导体元件32的表面大体相等的高度。此外，在与半导体元件32的焊盘电极相对应的位置处形成作为连接焊盘的UBM 37。UBM 37可具有与第一半导体器件10的UBM 16相同的配置，其是由Ni、Ti、TiW、W、Cu等形成。
在第二半导体器件31的端部处形成有布线结合焊盘39。在每个布线结合焊盘39中，第二半导体器件31和外部电子设备通过该布线结合相互电连接。
此外，在第二半导体器件31中，类似于上述第一半导体器件10，在半导体元件32上形成焊盘电极和钝化层。然而，只示出了用于说明第二实施例的半导体器件所需要的结构，并省略了其它结构的说明。
如图5A所示，在半导体器件30中，在第二半导体器件31上安装第一半导体器件10。在半导体器件30中，第一半导体器件10和第二半导体器件31布置成使得它们的电极形成表面互相相对。而且，在半导体器件30中，第一半导体器件10和第二半导体器件31布置成使得第一半导体器件10的对准标记15的位置与第二半导体器件31的对准标记36的位置对准。
此外，第一半导体器件10的每个凸块17与第二半导体器件31的UBM 37相接触，使得第一半导体器件10和第二半导体器件31电连接。然后，第一半导体器件10和第二半导体器件31通过底部填充树脂18机械地连接，从而在底部填充树脂18内形成凸块电极19与UBM37之间的连接。如上所述，在半导体器件30中，通过使用底部填充树脂18填充第一半导体器件10与第二半导体器件31之间的空隙，形成填充物。
接下来，将说明第二实施例的半导体器件的对准标记的高度。
在第二实施例的半导体器件中，形成在第一半导体器件中的焊盘电极与对准标记的高度差设置成小于形成在第二半导体器件中的连接焊盘的高度。
在图5B所示的半导体器件30中，第一半导体器件10的对准标记15的高度大于第一半导体器件10的凸块电极19的高度。这里凸块电极19与对准标记15之间的高度差表示为高度A。
而且，在第二半导体器件中，形成为连接焊盘的UBM 37的从元件表面开始的高度表示为高度B。
在这种情况下，对准标记15形成为使得高度A等于高度B，或者高度A小于高度B。
由于高度A等于或者小于高度B，即使在安装时的第一半导体器件10与第二半导体器件31之间的平行度低的情况下，仍然能够防止发生由多个凸块导致的连接错误。因此，当第一半导体器件10安装在第二半导体器件31上时，提高了凸块电极19与UBM 37之间的连接可靠性。
而且，在高度A大于高度B的情况下，当第一半导体器件10安装在第二半导体器件31上时，在凸块电极19与UBM 37之间连接之前，对准标记15和对准标记36互相接触。因此，发生连接错误。
此外，在每个凸块在UBM 37上形成为第二半导体器件31的连接焊盘的情况下，从第二半导体器件31的半导体元件表面到凸块的高度设置成上述高度B。而且，与仅在焊盘电极上形成连接焊盘的情形相似，在第二半导体器件31的连接焊盘形成在与半导体元件表面大致相同的表面上的情况下，第一半导体器件10的对准标记15和凸块电极19形成为具有基本相同的高度。因此，对准标记15形成为使得高度A等于高度B。
而且，上述实施例中，半导体器件31用作第二电子部件。然而，例如，可以使用上面形成有布线图案(该布线图案用于安装半导体器件)的安装板作为第二电子部件。可以使用上述第一实施例的具有对准标记的半导体器件作为第一电子部件，第二电子部件可以设置成具有与第一实施例的半导体器件相匹配的对准标记和连接焊盘。在第二实施例的半导体器件中，第二电子部件可适用于但不限于半导体器件、安装板等。
而且，在上述第二实施例的半导体器件中，高于连接电极的对准标记和底部填充树脂形成在作为第一电子部件的第一半导体器件的一侧。然而，高于连接电极的对准标记和底部填充树脂也可形成在第二电子部件一侧。通过在第一电子部件一侧设置底部填充树脂，在安装有布线结合焊盘(其形成在第二半导体器件中)的部分周围所形成的电极上形成底部填充树脂时，树脂不会造成污染。因此，优选地，高于连接电极的对准标记和底部填充树脂应当形成在第一电子部件一侧。
4.第二实施例的半导体器件的制造方法
接下来，将说明第二实施例的半导体器件的制造方法。此外，在以下制造方法的说明中，在存在上述图1至图5中所示的相同元件的情况下，将用相同的附图标记表示那些元件，并省略其详细说明。
此外，下文将通过使用由上述第一实施例制造的半导体器件来说明第二实施例的半导体器件的制造方法。
首先，如图6A所示，设置由第一实施例制造的上述第一半导体器件10，以作为第一电子部件。
而且，如图6B所示，设置第二半导体器件，以作为第二电子部件，在半导体元件32上形成有连接焊盘和对准标记36。第二半导体器件31在半导体元件32上具有焊盘电极33和对准标记36。然后，在半导体元件32上除焊盘电极33的开口部和对准标记36之外的整个表面上形成钝化层34。而且，每个UBM 37通过阻挡层35形成在焊盘电极33上。凸块38形成在UBM 37上。即，在图6B所示的第二半导体器件31中，用于安装第一半导体器件10的连接焊盘是由焊盘电极33、阻挡层35、UBM 37和凸块38形成。此外，在第二半导体器件31中，对准标记36与焊盘电极33形成在相同的层上。
然后，将第一半导体器件10和第二半导体器件31的位置对准。通过使用相机40，读取对准标记15和对准标记36的位置。然后，调整第一半导体器件10的位置，使得第一半导体器件10中的对准标记15的位置与第二半导体器件31中的对准标记36的位置对准。
接下来，如图6C所示，使第一半导体器件10的凸块17与第二半导体器件31的凸块38相接触，然后向它们施加负荷。而且，在施加负荷时，通过将凸块加热到焊料的熔点以上，例如在凸块17和38是由Sn-3.5Ag制成的情况下，通过结合头(bonding head)或者平台(stage)将凸块加热到熔点221℃以上，将凸块熔融并且连接。从而，通过破坏用于形成凸块17和38的焊料的表面氧化膜，形成基于无钎剂连接(fluxless connection)的连接部41。利用连接部41，将第一半导体器件10和第二半导体器件31电连接。
此外，第一半导体器件10和第二半导体器件31中所填充的底部填充树脂受热并且硬化。通过将半导体元件11按压在第二半导体器件31上，底部填充树脂18使半导体元件11与半导体元件32互相接合。通过底部填充树脂18使半导体元件互相接合，提高了机械连接的可靠性。
通过上述过程，能够制造出第二实施例的半导体器件30。
此外，当第一半导体器件10与第二半导体器件31连接时，对准标记15和对准标记36可以互相直接接触，或者可以不互相接触。
而且，在下述制造方法的说明中，不采用半导体器件31而采用具有用于安装半导体器件的布线图案的安装板等作为第二电子部件。可以使用上述第一实施例的具有对准标记的半导体器件作为第一电子部件，而第二电子部件设置成具有与第一实施例的半导体器件相匹配的对准标记和连接焊盘。
5.对准标记的修改示例
修改示例1
下面将说明形成在上述半导体器件中的对准标记的形状。
优选地，应当以如下方式形成对准标记：对准标记形成在元件表面上的平面形状不同于凸块电极的形状。例如，如图7所示，凸块电极19在半导体元件11上通常形成为圆形。因此，对准标记形成为具有不同于圆形的形状。如对准标记42，该对准标记形成为具有由矩形组合而成的十字形。此外，如对准标记43，该对准标记形成为正方形。此外，对准标记还形成为具有例如星形或者三角形等形状。
如上所述，通过使对准标记的形状不同于形成在半导体器件中的凸块电极的形状，例如，即使在凸块电极进入照相机(其用于辨认倒装芯片接合器(flip-chip bonder)的对准标记)的视野的情况下，仍然能够防止误辨认。
修改示例2
此外，例如图8A所示，形成在半导体器件中的对准标记可以形成为围绕半导体元件的外周部。
在图8A所示的半导体器件中，凸块电极19在半导体元件11上形成为圆形。然后，对准标记44形成为围绕半导体元件11外周部。此外，形成在半导体器件的凸块电极19一侧的底部填充树脂形成在对准标记44的内部，对准标记44围绕半导体元件11的外周部。
对准标记44包括矩形对准标记44A和对准标记44B，矩形对准标记44A形成在半导体元件11的角部，对准标记44B形成在对准标记44A的对角处。此外，对准标记44还包括对准标记44C，对准标记44C连续形成在半导体元件11的外周部上。
如图8B所示，在安装第二半导体器件31时，对准标记44A及44B与第二半导体器件31的对准标记36相对准。因此，优选地，对准标记应当形成为与凸块电极19具有不同的形状。
而且，通过围绕半导体元件11的外周部，能够抑制底部填充树脂向外流出。
当第一半导体器件的安装部靠近诸如形成在安装部周围的布线结合焊盘等电极部时，底部填充树脂开始流入该安装部附近的电极部，从而导致电极受到树脂的污染。在将半导体器件小型化使得第二半导体器件中的安装部和电极部之间的距离变短时，这容易导致问题。
因此，通过围绕半导体元件11的外周部，能够防止底部填充树脂污染形成在第二半导体器件31中的布线结合焊盘39等。然后，通过减小第一电子部件(半导体器件10)与第二电子部件(半导体器件31)之间的元件面积差异，能够将半导体器件小型化。
此外，如图8B所示，即使当对准标记44与第二半导体器件31的元件表面的间隔开时，仍然能够抑制底部填充树脂18向外流出。因此，对准标记15可以不直接接触第二半导体器件31的元件表面。
此外，上述实施例的半导体器件中的对准标记可以连接到例如下部半导体元件的电极。例如，上部半导体元件的对准标记形成在上部半导体元件的电极上，而下部半导体元件的对准标记形成在下部半导体元件的电极上。然后，当通过在下部半导体元件的对准标记上形成焊料层将半导体元件互相连接时，通过焊料将对准标记连接，能够在对准标记之间形成电连接。
本领域技术人员应当理解，只要设计要求以及其它因素在本发明所附权利要求或者其等同物的范围内，就可以根据这些设计要求以及其它因素进行各种修改、组合、次组合以及替换。
本发明包含与2010年12月17日向日本专利局提交的日本在先专利申请JP 2010-282082的公开内容相关的主题，在此将该在先申请的全部内容以引用的方式并入本文。

Claims (11)

1.一种半导体器件，其包括：
半导体元件；
位于所述半导体元件上的钝化层；
位于所述半导体元件上且通过所述钝化层中的开口暴露的焊盘电极；
位于所述焊盘电极和所述钝化层上的阻挡层；
位于所述焊盘电极上的连接电极；以及
从所述半导体元件延伸的对准标记，
其中，所述钝化层的一部分位于所述对准标记与所述半导体元件之间，且
所述阻挡层的一部分位于所述对准标记与所述钝化层之间。
2.如权利要求1所述的半导体器件，其中，所述连接电极包括处于所述焊盘电极上的凸块底部金属层。
3.如权利要求1所述的半导体器件，其中，所述连接电极包括形成在所述焊盘电极上的凸块底部金属层和形成在所述凸块底部金属层上的焊料凸块。
4.如权利要求1所述的半导体器件，其中，所述阻挡层包括金属层。
5.如权利要求4所述的半导体器件，其中，所述金属层包含铜和钛中的至少一者。
6.如权利要求3所述的半导体器件，其中，所述对准标记和所述凸块底部金属层由相同的材料形成。
7.如权利要求1所述的半导体器件，其中，所述对准标记的形状不同于所述连接电极的形状。
8.如权利要求1所述的半导体器件，其还包括：
位于所述钝化层上的阻挡层，所述阻挡层的一部分位于所述对准标记与所述钝化层之间。
9.如权利要求1所述的半导体器件，其中，所述对准标记从所述半导体元件的表面开始的高度大于所述连接电极从所述第二半导体元件的所述表面开始的高度。
10.一种半导体器件，其包括：
第一半导体元件，其具有(a)位于所述第一半导体元件上的第一钝化层、(b)位于所述第一半导体元件上且通过所述第一钝化层中的开口暴露的第一焊盘电极、(c)位于所述第一焊盘电极上的第一连接电极以及(d)位于所述第一半导体元件上的第一对准标记；以及
第二半导体元件，其具有(a)位于所述第二半导体元件上的第二钝化层、(b)位于所述第二半导体元件上且通过所述第二钝化层中的开口暴露的第二焊盘电极、(c)位于所述第二半导体元件上的第二对准标记、(d)位于所述第二焊盘电极上的第二连接电极、(e)直接位于所述第二钝化层上的阻挡层以及(f)覆盖所述第二连接电极的底部填充树脂，
其中，所述第二对准标记从所述第二半导体元件的表面开始的高度大于所述第二连接电极从所述第二半导体元件的所述表面开始的高度。
11.如权利要求10所述的半导体器件，其还包括位于所述第一连接电极和所述第二连接电极之间的无钎剂连接部，所述第一连接电极和所述第二连接电极均包括凸块底部金属层。
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