CN111048485B - 一种半导体芯片器件 - Google Patents
一种半导体芯片器件 Download PDFInfo
- Publication number
- CN111048485B CN111048485B CN201911292334.XA CN201911292334A CN111048485B CN 111048485 B CN111048485 B CN 111048485B CN 201911292334 A CN201911292334 A CN 201911292334A CN 111048485 B CN111048485 B CN 111048485B
- Authority
- CN
- China
- Prior art keywords
- pads
- chip
- layer
- semiconductor chip
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
本发明提供了一种半导体芯片器件,本发明在焊盘周围形成的是光固化树脂,其由于在光固化后形成的固化树脂层可以有效的减小底部填充树脂侧向展开面积,保证其他焊盘的可靠连接;并且,本发明采用镍硅镀层来实现凸块焊接可靠性的同时,可以利用其弱润湿性来进一步减小底部填充树脂侧向展开面积;此外,更进一步的,本发明的凹形结构(或者环形凹形)作为一个围障,也能够减小底部填充树脂侧向展开面积。
Description
技术领域
本发明涉及半导体封装测试领域,具体涉及一种半导体芯片器件。
背景技术
对于衬底上芯片结构(即COB结构),往往是在衬底上形成多个焊盘,由于集成度的需要,该多个焊盘往往需要集成多个芯片,该多个芯片在每次焊接至所述多个焊盘的一部分时,需要对其进行底部填充,以保护焊接。底部填充的液态填充胶会由于重力作用而在衬底上流动,往往会覆盖到周边的其他焊盘,该些被覆盖的焊盘在后续焊接其他芯片,其电连接是不可靠的,往往会导致虚焊,因而影响了最终封装的良品率。
发明内容
基于解决上述问题,本发明提供了一种半导体芯片器件,包括:
衬底结构,所述衬底结构包括衬底、在衬底上的再布线层以及在所述再布线层上的光固化树脂层,在所述光固化树脂层内具有至少一第一焊盘和多个第二焊盘,其中所述多个第二焊盘环绕于所述至少一第一焊盘;
芯片结构,设置于所述衬底结构上,所述芯片结构包括芯片以及电连接所述芯片的多个凸块;
所述芯片结构通过所述多个凸块电连至所述至少一第一焊盘和多个第二焊盘;
底部填充胶,填充于所述芯片与所述衬底结构之间;
其中,所述多个第二焊盘的每一个均包括焊接部和连接所述焊接部的延伸部,所述延伸部从所述芯片在所述光固化树脂层上的投影之内延伸至所述投影之外,所述底部填充胶的边缘在所述延伸部的边缘之内。
根据本发明的实施例,所述焊接部的形状与所述至少一第一焊盘的形状相同,且均位于所述投影之内。
根据本发明的实施例,所述多个第二焊盘的上表面具有镍硅镀层,所述镍硅镀层的润湿性比所述多个焊盘的润湿性差。
根据本发明的实施例,所述延伸部具有一凹形,所述凹形为弧形凹面,且所述凹形位于所述投影之外。
根据本发明的实施例,还包括在所述多个第二焊盘外侧的多个第三焊盘。
本发明还提供了另一种半导体芯片器件,包括:
衬底结构,所述衬底结构包括衬底、在衬底上的再布线层以及在所述再布线层上的光固化树脂层,在所述光固化树脂层内具有多个第一焊盘和环形金属层,其中所述环形金属层环绕于所述多个第一焊盘;
芯片结构,设置于所述衬底结构上,所述芯片结构包括芯片以及电连接所述芯片的多个凸块;
所述芯片结构通过所述多个凸块电连至所述多个第一焊盘;
底部填充胶,填充于所述芯片与所述衬底结构之间;
其中,所述环形金属层位于所述芯片在所述光固化树脂层上的投影之外,所述底部填充胶的边缘在所述环形金属层的外边缘之内。
根据本发明的实施例,所述环形金属层与所述第一焊盘的材质相同。
根据本发明的实施例,所述环形金属层的上表面具有镍硅镀层,所述镍硅镀层的润湿性比所述环形金属层的润湿性差。
根据本发明的实施例,所述环形金属层具有一环形凹形,所述环形凹形为弧形截面,且所述环形凹形环绕所述投影一周。
根据本发明的实施例,还包括在所述多个第一焊盘外侧的多个第二焊盘。
本发明在焊盘周围形成的是光固化树脂,其由于在光固化后形成的固化树脂层可以有效的减小底部填充胶侧向展开面积,保证其他焊盘的可靠连接;并且,本发明采用镍硅镀层来实现凸块焊接可靠性的同时,可以利用其弱润湿性来进一步减小底部填充胶侧向展开面积;此外,更进一步的,本发明的凹形结构(或者环形凹形)作为一个围障,也能够减小底部填充胶侧向展开面积。
附图说明
图1为第一实施例的半导体芯片器件的剖视图;
图2为第一实施例的半导体芯片器件的俯视图;
图3为第二实施例的半导体芯片器件的剖视图;
图4为第二实施例的半导体芯片器件的俯视图;
图5为第三实施例的半导体芯片器件的剖视图;
图6为第三实施例的半导体芯片器件的俯视图;
图7为第四实施例的半导体芯片器件的剖视图;
图8为第四实施例的半导体芯片器件的俯视图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
本发明的半导体芯片器件目的在于克服现有技术中底部填充胶因表面润湿性而进行外扩散导致的焊盘表面电连接不可靠问题。
第一实施例
本实施例提供了一种半导体芯片器件,如图1和2所示,包括依次设置的衬底结构和芯片结构。所述衬底结构包括衬底1、在衬底1上的第一介电层2和第二介电层5,所述第一介电层2中形成通孔4且贯穿所述第一介电层2,所述通孔4电互连所述衬底1的连接焊盘3,所述衬底1可以是PCB基板、系统板或者中介板等。
在所述第一介电层2上形成有布线层7,所述布线层7电互连至所述通孔4,所述布线层7可以采用常规的沉积或电镀方法形成,其调整焊盘的引出位置,提供封装的端子引出的灵活性。
第二介电层5覆盖所述布线层7和第一介电层2,该第二介电层5与第一介电层2的材质相同,均为无机材料,例如氧化硅、氮化硅等。所述第二介电层5中形成通孔8且贯穿所述第二介电层5。所述第一介电层2和第二介电层5均可以采用常规的形成方法形成,在此不做过多限制。
在所述第二介质层5上的光固化树脂层6,在所述光固化树脂层6内具有至少一第一焊盘(第二焊盘中间部分的焊盘)和多个第二焊盘9,其中所述多个第二焊盘9环绕于所述至少一第一焊盘。所述光固化树脂层6是必须的,其由于是树脂材料,其润湿性比例如氧化硅或氮化硅等无机材料要差,底部填充胶14在所述光固化树脂层6上的铺展面积就更小,从而可以防止其他焊盘10的虚焊。并且优选的,所述光固化树脂为UV树脂,其在光照聚合时,会使得树脂材料固化并产生非平整表面,进而可以阻止底部填充胶的流动。
所述芯片结构,设置于所述衬底结构上,所述芯片结构包括芯片12以及电连接所述芯片12的多个凸块13;所述芯片结构通过所述多个凸块13电连至所述至少一第一焊盘和多个第二焊盘9。所述多个凸块13可以是焊料凸块,其接合于所述至少一第一焊盘和多个第二焊盘9可以通过无铅焊料或者共晶焊料等形成。当然,所述多个凸块13可以是金属凸柱,其接合于所述至少一第一焊盘和多个第二焊盘9可以通过金属-金属直接键合等方法形成。此时,所述多个凸块13的数量应当等于所述至少一第一焊盘和多个第二焊盘9的数量之和,且所述多个凸块13完全位于所述芯片12之下。
在所述芯片结构和衬底结构之间填充有底部填充胶14,该底部填充胶至少应包裹所述多个凸块13;所述底部填充胶14为常规的聚合物材料,其在填充时为液体,后经固化保持稳定态,常规的材料可以选自环氧树脂、聚酰亚胺、PCB、PBO等。
参考图2,所述多个第二焊盘9的每一个均包括焊接部91和连接所述焊接部91的延伸部92,所述延伸部92从所述芯片12在所述光固化树脂层6上的投影之内延伸至所述投影之外,所述底部填充胶14的边缘在所述延伸部92的边缘之内。也就是说,底部填充胶14未流动至所述延伸部92的外侧,其有效的防止了底部填充胶的横向铺展,进而保证了其他焊盘10的电连接的可靠性。可以看到,所述焊接部91的形状与所述至少一第一焊盘的形状相同,且所述焊接部91均位于所述投影之下。
其他焊盘10为多个,包围所述至少一第一焊盘和多个第二焊盘9。该些其他焊盘10用于电连接其他电子部件,其他电子部件可以与所述芯片结构相同或者不同。
此外,在所述多个第二焊盘9的上表面具有镍硅镀层11,所述镍硅镀层11采用镍靶和硅靶的共溅射形成,其中硅的质量百分比为5wt%。该镍硅镀层11相较于多个第二焊盘9具有较差的润湿性,且其有利于凸块13的接合。此外,为了保证镍硅镀层11的弱润湿性,本发明还采用氮源对所述镍硅镀层11进行等离子体处理,以形成粗糙表面,并且该处理过的镍硅镀层11可以防止焊接时的氧化问题。
第二实施例
参见图3和4,该实施例的结构与第一实施例的结构相类似,与之区别的是,在所述光固化树脂层6中具有多个第一焊盘15、多个第二焊盘10以及位于所述多个第一焊盘15和多个第二焊盘10之间的环形金属层16,所述环形金属层16可以与所述多个第一焊盘15、多个第二焊盘10采用相同的方法、相同的材质一体形成。值得一提的是,该实施例的所述多个第一焊盘15均位于所述芯片12在所述光固化树脂层6上的投影之内,但是所述多个环形金属层16和所述第二焊盘10均位于所述投影之外。
在所述环形金属层16上还镀有一镍硅镀层17,该镍硅镀层17与第一实施例的一致,在此不再赘述。参见图4,所述底部填充胶14延伸至所述环形金属层16上,但是并未延伸出所述环形金属层16,该环形金属层16起到阻障作用。
第三实施例
参见图5和6,在该实施例中,其结构与第一实施例基本类似。区别在于在第二焊盘上没有镍硅镀层,而在延伸部形成了凹槽或凹形。本实施例中,多个第二焊盘18也同样具有焊接部81和延伸部82,其具体结构参照第一实施例。而在延伸部82位置具有凹形19,所述凹形19为弧形凹形,且所述凹形19位于所述芯片12在所述光固化树脂层6上的投影之外。参见图5,底部填充胶14部分的延伸至所述凹形19内,且所述底部填充胶14的边缘位于所述凹形19以内。其中,所述凹形19通过激光烧蚀方法形成。
第四实施例
参见图5,该实施例中,其结构与第二实施例基本类似。环形金属层20上没有设置镍硅镀层,其具有一凹形21,所述凹形21为环形,其与所述环形金属层层20的延伸一致。所述环形金属层20可以与所述多个第一焊盘15、多个第二焊盘10采用相同的方法、相同的材质一体形成。值得一提的是,该实施例的所述多个第一焊盘15均位于所述芯片12在所述光固化树脂层6上的投影之内,但是所述多个环形金属层20和所述第二焊盘10均位于所述投影之外。
在所述环形金属层20上的凹形21具有阻障作用,其中,所述凹形19通过激光烧蚀方法形成。参见图4,所述底部填充胶14延伸至所述环形金属层16上,但是并未延伸出所述环形金属层20和所述凹形21,该环形金属层20和所述凹形21同时起到阻障作用。
本发明中使用的表述“示例性实施例”、“示例”等不是指同一实施例,而是被提供来着重描述不同的特定特征。然而,上述示例和示例性实施例不排除他们与其他示例的特征相组合来实现。例如,即使在另一示例中未提供特定示例的描述的情况下,除非另有陈述或与其他示例中的描述相反,否则该描述可被理解为与另一示例相关的解释。
本发明中使用的术语仅用于示出示例,而无意限制本发明。除非上下文中另外清楚地指明,否则单数表述包括复数表述。
虽然以上示出并描述了示例实施例,但对本领域技术人员将明显的是,在不脱离由权利要求限定的本发明的范围的情况下,可做出变型和改变。
Claims (8)
1.一种半导体芯片器件,包括:
衬底结构,所述衬底结构包括衬底、在衬底上的再布线层以及在所述再布线层上的光固化树脂层,在所述光固化树脂层内具有至少一第一焊盘和多个第二焊盘,其中所述多个第二焊盘环绕于所述至少一第一焊盘;
芯片结构,设置于所述衬底结构上,所述芯片结构包括芯片以及电连接所述芯片的多个凸块;
所述芯片结构通过所述多个凸块电连至所述至少一第一焊盘和多个第二焊盘;
底部填充胶,填充于所述芯片与所述衬底结构之间;
其特征在于,所述多个第二焊盘的每一个均包括焊接部和连接所述焊接部的延伸部,所述延伸部从所述芯片在所述光固化树脂层上的投影之内延伸至所述投影之外,所述底部填充胶的边缘在所述延伸部的边缘之内;所述延伸部具有一凹形,所述凹形为弧形凹面,且所述凹形位于所述投影之外。
2.根据权利要求1所述的半导体芯片器件,其特征在于,所述焊接部的形状与所述至少一第一焊盘的形状相同,且均位于所述投影之内。
3.根据权利要求2所述的半导体芯片器件,其特征在于,所述多个第二焊盘的上表面具有镍硅镀层,所述镍硅镀层的润湿性比所述多个第二焊盘的润湿性差。
4.根据权利要求2所述的半导体芯片器件,其特征在于,还包括在所述多个第二焊盘外侧的多个第三焊盘。
5.一种半导体芯片器件,包括:
衬底结构,所述衬底结构包括衬底、在衬底上的再布线层以及在所述再布线层上的光固化树脂层,在所述光固化树脂层内具有多个第一焊盘和环形金属层,其中所述环形金属层环绕于所述多个第一焊盘;
芯片结构,设置于所述衬底结构上,所述芯片结构包括芯片以及电连接所述芯片的多个凸块;
所述芯片结构通过所述多个凸块电连至所述多个第一焊盘;
底部填充胶,填充于所述芯片与所述衬底结构之间;
其特征在于,所述环形金属层位于所述芯片在所述光固化树脂层上的投影之外,所述底部填充胶的边缘在所述环形金属层的外边缘之内;所述环形金属层具有一环形凹形,所述环形凹形为弧形截面,且所述环形凹形环绕所述投影一周。
6.根据权利要求5所述的半导体芯片器件,其特征在于,所述环形金属层与所述第一焊盘的材质相同。
7.根据权利要求5所述的半导体芯片器件,其特征在于,所述环形金属层的上表面具有镍硅镀层,所述镍硅镀层的润湿性比所述环形金属层的润湿性差。
8.根据权利要求5所述的半导体芯片器件,其特征在于,还包括在所述多个第一焊盘外侧的多个第二焊盘。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201911292334.XA CN111048485B (zh) | 2019-12-16 | 2019-12-16 | 一种半导体芯片器件 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201911292334.XA CN111048485B (zh) | 2019-12-16 | 2019-12-16 | 一种半导体芯片器件 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN111048485A CN111048485A (zh) | 2020-04-21 |
CN111048485B true CN111048485B (zh) | 2021-07-27 |
Family
ID=70236471
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201911292334.XA Active CN111048485B (zh) | 2019-12-16 | 2019-12-16 | 一种半导体芯片器件 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN111048485B (zh) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130214409A1 (en) * | 2010-09-13 | 2013-08-22 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Bond-on-Lead Interconnection for Mounting Semiconductor Die in FO-WLCSP |
CN103378040A (zh) * | 2012-04-11 | 2013-10-30 | 台湾积体电路制造股份有限公司 | 半导体器件封装件及半导体器件封装方法 |
CN103390602A (zh) * | 2012-05-11 | 2013-11-13 | 矽品精密工业股份有限公司 | 半导体封装件及其封装基板 |
CN103779283A (zh) * | 2012-10-19 | 2014-05-07 | 台湾积体电路制造股份有限公司 | 封装器件、封装器件的制造方法以及封装方法 |
-
2019
- 2019-12-16 CN CN201911292334.XA patent/CN111048485B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130214409A1 (en) * | 2010-09-13 | 2013-08-22 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Bond-on-Lead Interconnection for Mounting Semiconductor Die in FO-WLCSP |
CN103378040A (zh) * | 2012-04-11 | 2013-10-30 | 台湾积体电路制造股份有限公司 | 半导体器件封装件及半导体器件封装方法 |
CN103390602A (zh) * | 2012-05-11 | 2013-11-13 | 矽品精密工业股份有限公司 | 半导体封装件及其封装基板 |
CN103779283A (zh) * | 2012-10-19 | 2014-05-07 | 台湾积体电路制造股份有限公司 | 封装器件、封装器件的制造方法以及封装方法 |
Also Published As
Publication number | Publication date |
---|---|
CN111048485A (zh) | 2020-04-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11682651B2 (en) | Bump-on-trace interconnect | |
JP5629580B2 (ja) | 二重ポスト付きフリップチップ相互接続 | |
TWI529886B (zh) | 封裝體、裝置的封裝方法以及封裝層疊裝置 | |
US6774497B1 (en) | Flip-chip assembly with thin underfill and thick solder mask | |
US9373573B2 (en) | Solder joint flip chip interconnection | |
USRE44355E1 (en) | Method of forming a bump-on-lead flip chip interconnection having higher escape routing density | |
US8076232B2 (en) | Semiconductor device and method of forming composite bump-on-lead interconnection | |
TWI518812B (zh) | 形成導線上凸塊互連的半導體裝置及方法 | |
US9545013B2 (en) | Flip chip interconnect solder mask | |
US7087458B2 (en) | Method for fabricating a flip chip package with pillar bump and no flow underfill | |
US20140319692A1 (en) | Semiconductor Device and Method of Forming High Routing Density Interconnect Sites on Substrate | |
US8222748B2 (en) | Packaged electronic devices having die attach regions with selective thin dielectric layer | |
US8410604B2 (en) | Lead-free structures in a semiconductor device | |
US20100007015A1 (en) | Integrated circuit device with improved underfill coverage | |
US8923005B2 (en) | Electrical component having an electrical connection arrangement and method for the manufacture thereof | |
CN108962855B (zh) | 半导体结构、半导体元件及其形成方法 | |
CN111048485B (zh) | 一种半导体芯片器件 | |
USRE44500E1 (en) | Semiconductor device and method of forming composite bump-on-lead interconnection | |
KR101804568B1 (ko) | 반도체 패키지 및 그 제조방법 | |
JP4963890B2 (ja) | 樹脂封止回路装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20210625 Address after: 518000 Room 201, building A, No. 1, Qian Wan Road, Qianhai Shenzhen Hong Kong cooperation zone, Shenzhen, Guangdong (Shenzhen Qianhai business secretary Co., Ltd.) Applicant after: Milstar (Shenzhen) Information Technology Co.,Ltd. Address before: 250000 shop a-108, building 3, Wanxiang xintiansi District, Wangsheren street, Licheng District, Jinan City, Shandong Province Applicant before: Shandong Yanding Electronic Technology Co.,Ltd. |
|
TA01 | Transfer of patent application right | ||
GR01 | Patent grant | ||
GR01 | Patent grant |