JP4415717B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP4415717B2 JP4415717B2 JP2004083947A JP2004083947A JP4415717B2 JP 4415717 B2 JP4415717 B2 JP 4415717B2 JP 2004083947 A JP2004083947 A JP 2004083947A JP 2004083947 A JP2004083947 A JP 2004083947A JP 4415717 B2 JP4415717 B2 JP 4415717B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
Claims (4)
- 平面視矩形状のチップ実装領域の周囲に電極パッドが形成されるとともに、前記チップ実装領域と前記電極パッドの形成領域との間にダムが設けられた実装基板と、
前記実装基板の前記チップ実装領域にフリップチップ実装された半導体チップと、
前記実装基板と前記半導体チップとの間に充填されたアンダーフィル材とを備え、
前記チップ実装領域の所定の辺と当該所定の辺と直角をなす他の2つの辺に対応して前記ダムを平面視コ字形に形成するとともに、前記所定の辺と当該所定の辺に対応する前記ダムとの間の距離が、前記所定の辺と直角をなす他の2つの辺と当該他の2つの辺に対応する前記ダムとの間の距離よりも長い
半導体装置。 - 実装基板のチップ実装領域の周囲でかつ電極パッドの形成領域の内側にダムを形成する第1の工程と、
前記実装基板の前記チップ実装領域に半導体チップをフリップチップ実装する第2の工程と、
前記実装基板と前記半導体チップとの間にアンダーフィル材を充填する第3の工程とを有し、
前記第1の工程においては、前記実装基板の前記チップ実装領域にバンプを形成するとともに、前記バンプと前記ダムの形成材料を共に半田材料とし、前記バンプと同時に前記ダムを形成するとともに、前記チップ実装領域の所定の辺と当該所定の辺に対応する前記ダムとの間の距離が、前記チップ実装領域の他の辺と当該他の辺に対応する前記ダムとの間の距離よりも長くなるように前記ダムを形成し、
前記第3の工程においては、前記チップ実装領域の所定の辺と当該所定の辺に対応する前記ダムとの間に前記アンダーフィル材を滴下する
半導体装置の製造方法。 - 実装基板のチップ実装領域の周囲でかつ電極パッドの形成領域の内側にダムを形成する第1の工程と、
前記実装基板の前記チップ実装領域に半導体チップをフリップチップ実装する第2の工程と、
前記実装基板と前記半導体チップとの間にアンダーフィル材を充填する第3の工程とを有し、
前記第1の工程においては、前記実装基板の前記チップ実装領域にバンプを形成するとともに、前記バンプと前記ダムの形成材料を共に半田材料とし、前記バンプと同時に前記ダムを形成するとともに、前記チップ実装領域の所定の辺に対応する位置のみ、または前記所定の辺に対応する位置と当該所定の辺と直角をなす他の2つの辺に対応する位置にのみ、前記ダムを形成し、
前記第3の工程においては、前記チップ実装領域の所定の辺と当該所定の辺に対応する前記ダムとの間に前記アンダーフィル材を滴下する
半導体装置の製造方法。 - 前記第1の工程においては、前記チップ実装領域の所定の辺に対応する位置にのみ、前記ダムを形成し、
前記第3の工程においては、前記チップ実装領域の所定の辺と当該所定の辺に対応する前記ダムとの間に前記アンダーフィル材を滴下するときの滴下範囲を前記ダムの長手方向で前記所定の辺のほぼ半分の長さに相当する範囲に制限する
請求項3記載の半導体装置の製造方法。
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JP2004083947A JP4415717B2 (ja) | 2004-03-23 | 2004-03-23 | 半導体装置及びその製造方法 |
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JP2005276879A JP2005276879A (ja) | 2005-10-06 |
JP4415717B2 true JP4415717B2 (ja) | 2010-02-17 |
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Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4728079B2 (ja) * | 2005-10-07 | 2011-07-20 | ルネサスエレクトロニクス株式会社 | 半導体装置用基板および半導体装置 |
KR100691443B1 (ko) | 2005-11-16 | 2007-03-09 | 삼성전기주식회사 | 플립칩 패키지 및 그 제조방법 |
JP4792949B2 (ja) * | 2005-12-05 | 2011-10-12 | ソニー株式会社 | 半導体装置の製造方法及び半導体装置 |
JP4760361B2 (ja) * | 2005-12-20 | 2011-08-31 | ソニー株式会社 | 半導体装置 |
JP4910408B2 (ja) * | 2006-01-31 | 2012-04-04 | ソニー株式会社 | 半導体装置 |
JP4391508B2 (ja) | 2006-09-29 | 2009-12-24 | Okiセミコンダクタ株式会社 | 半導体装置、及び半導体装置の製造方法 |
JP5356647B2 (ja) | 2006-12-25 | 2013-12-04 | 新光電気工業株式会社 | 実装基板及び電子装置 |
JP5211493B2 (ja) | 2007-01-30 | 2013-06-12 | 富士通セミコンダクター株式会社 | 配線基板及び半導体装置 |
JP4438006B2 (ja) | 2007-03-30 | 2010-03-24 | Okiセミコンダクタ株式会社 | 半導体装置及び半導体装置の製造方法 |
JP4441545B2 (ja) | 2007-03-30 | 2010-03-31 | Okiセミコンダクタ株式会社 | 半導体装置 |
JP2008270518A (ja) * | 2007-04-20 | 2008-11-06 | Nec Saitama Ltd | ノイズシールドケースおよび電子部品のシールド構造 |
JP5168160B2 (ja) | 2009-01-15 | 2013-03-21 | ソニー株式会社 | 半導体装置及び半導体装置の製造方法 |
TWI458054B (zh) | 2009-01-21 | 2014-10-21 | Sony Corp | 半導體裝置及半導體裝置之製造方法 |
JP5139400B2 (ja) * | 2009-11-04 | 2013-02-06 | ラピスセミコンダクタ株式会社 | 半導体装置の製造方法 |
JP2011243612A (ja) | 2010-05-14 | 2011-12-01 | Sony Corp | 半導体装置及びその製造方法並びに電子機器 |
DE102010031945A1 (de) * | 2010-07-22 | 2012-01-26 | Osram Opto Semiconductors Gmbh | Halbleiterbauelement und Verfahren zur Herstellung eines Halbleiterbauelements |
JP5927756B2 (ja) | 2010-12-17 | 2016-06-01 | ソニー株式会社 | 半導体装置及び半導体装置の製造方法 |
CN103325694B (zh) * | 2012-03-21 | 2016-08-24 | 致伸科技股份有限公司 | 用于覆晶制程的点胶方法 |
JP6125209B2 (ja) | 2012-11-19 | 2017-05-10 | 株式会社ジェイデバイス | 半導体装置及びその製造方法 |
CN103137571A (zh) * | 2013-01-22 | 2013-06-05 | 日月光半导体制造股份有限公司 | 半导体封装构造及其制造方法 |
JP2015119077A (ja) | 2013-12-19 | 2015-06-25 | ソニー株式会社 | 半導体装置およびその製造方法 |
JP7236807B2 (ja) | 2018-01-25 | 2023-03-10 | 浜松ホトニクス株式会社 | 半導体装置、及び半導体装置の製造方法 |
JP2020047861A (ja) * | 2018-09-20 | 2020-03-26 | ソニーセミコンダクタソリューションズ株式会社 | 固体撮像装置及び電子機器 |
CN110600384A (zh) * | 2019-08-29 | 2019-12-20 | 宜特(上海)检测技术有限公司 | 用于芯片的局部封胶方法 |
CN111508854A (zh) * | 2020-04-10 | 2020-08-07 | 中国电子科技集团公司第十一研究所 | 一种混成芯片的制备方法及混成芯片 |
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