JP5018155B2 - 配線基板、電子部品の実装構造、及び半導体装置 - Google Patents
配線基板、電子部品の実装構造、及び半導体装置 Download PDFInfo
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- JP5018155B2 JP5018155B2 JP2007069346A JP2007069346A JP5018155B2 JP 5018155 B2 JP5018155 B2 JP 5018155B2 JP 2007069346 A JP2007069346 A JP 2007069346A JP 2007069346 A JP2007069346 A JP 2007069346A JP 5018155 B2 JP5018155 B2 JP 5018155B2
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- wiring board
- opening
- wiring
- electronic component
- semiconductor element
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
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- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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Description
図6は、本発明の第1の実施の形態に係る配線基板への半導体素子の実装構造の要部を示す図である。
上述の本発明の第1の実施の形態では、半導体素子32を配線基板31に搭載する際に、予め配線基板31上にアンダーフィル材42を供給しておき、アンダーフィル材42を介しながら半導体素子32を配線基板31に搭載することによりアンダーフィル材42を押し広げると共に、毛細管現象により半導体素子32の全面領域にアンダーフィル材42を流動させて充填し、同時に半導体素子32を配線基板31に搭載する際に付与される熱によりアンダーフィル材42を硬化させる方法に用いられる配線基板31について説明した。
(付記1)
複数の外部接続端子が形成された面を下向きにしたフェイスダウン状態で電子部品が実装され、接着剤を介して前記電子部品が固着される配線基板であって、
前記電子部品が実装される面には、絶縁膜が形成され、
前記電子部品の前記外部接続端子が接続される電極を備えた複数の隣接する配線パターンを共通して部分的に開口するように、開口部が前記絶縁膜に形成されており、
前記開口部の外周部分のうち当該配線基板の中心側に位置する箇所において、前記開口部の端面は、前記配線パターンが延在する方向に対して斜め方向に形成されていることを特徴とする配線基板。
(付記2)
付記1記載の配線基板であって、
前記開口部の外周部分のうち当該配線基板の中心側に位置する箇所は、所定の角度を有して折り曲がった形状を有することを特徴とする配線基板。
(付記3)
付記1記載の配線基板であって、
前記開口部の外周部分のうち当該配線基板の中心側に位置する箇所は、曲線形状を有することを特徴とする配線基板。
(付記4)
付記1記載の配線基板であって、
前記開口部の外周部分のうち当該配線基板の中心側に位置する箇所は、ステップ形状を有することを特徴とする配線基板。
(付記5)
付記1乃至4いずれか一項記載の配線基板であって、
前記開口部内で露出している前記配線パターンのそれぞれの露出面積は、互いに略等しいことを特徴する配線基板。
(付記6)
付記1乃至5いずれか一項記載の配線基板であって、
前記開口部内で露出している前記配線パターンは、直線状に延在形成されていることを特徴する配線基板。
(付記7)
付記6記載の配線基板であって、
前記電極の配列方向は、前記配線パターンの延在形成方向と略垂直の方向であることを特徴とする配線基板。
(付記8)
付記1乃至7いずれか一項記載の配線基板であって、
前記電極の幅は、前記電極以外の前記配線パターンの箇所の幅よりも幅広に形成されていることを特徴とする配線基板。
(付記9)
付記1乃至8いずれか一項記載の配線基板であって、
前記開口部は、前記絶縁膜に環状に形成され、
前記電極の列が、当該配線基板の四辺に沿って露出していることを特徴とする配線基板。
(付記10)
付記1乃至9いずれか一項記載の配線基板であって、
前記配線パターン上には導電部材が設けられ、
前記導電部材を介して、前記電子部品の前記外部接続端子と対応する当該配線基板の前記電極とが接続されることを特徴とする配線基板。
(付記11)
付記1乃至10いずれか一項記載の配線基板であって、
前記開口部の外周部分は、当該配線基板に実装される前記電子部品の外周領域よりも、当該配線基板の外周側に形成されていることを特徴とする配線基板。
(付記12)
付記1乃至10いずれか一項記載の配線基板であって、
前記開口部は、前記電子部品と当該配線基板とを固着する前記接着剤が塗布される側に対して最も遠い側に位置する当該配線基板の辺に沿って形成されていることを特徴とする配線基板。
(付記13)
付記1乃至12いずれか一項記載の配線基板であって、
前記開口部の前記外周部分を画定する前記絶縁膜の端部の断面形状は、上広がりのテーパ形状であることを特徴とする配線基板。
(付記14)
複数の外部接続端子が形成された面を下向きにしたフェイスダウン状態で電子部品が配線基板に実装され、接着剤を介して前記電子部品が前記配線基板に固着される電子部品の実装構造であって、
前記電子部品が実装される前記配線基板の面には、絶縁膜が形成され、
前記電子部品の前記外部接続端子が接続される電極を備えた複数の隣接する配線パターンを共通して部分的に開口するように、開口部が前記絶縁膜に形成されており、
前記開口部の外周部分のうち前記配線基板の中心側に位置する箇所において、前記開口部の端面は、前記配線パターンが延在する方向に対して斜め方向に形成されていることを特徴とする電子部品の実装構造。
(付記15)
付記14記載の電子部品の実装構造であって、
前記配線パターン上には導電部材が設けられ、
前記導電部材を介して前記電子部品の前記外部接続端子と対応する前記配線基板の前記電極とが接続されることを特徴とする電子部品の実装構造。
(付記16)
付記14又は15記載の電子部品の実装構造であって、
前記開口部の外周部分は、前記配線基板に実装される前記電子部品の外周領域よりも、前記配線基板の外周側に形成されていることを特徴とする電子部品の実装構造。
(付記17)
付記14又は15記載の電子部品の実装構造であって、
前記開口部は、前記電子部品と前記配線基板とを固着する前記接着剤が塗布される側に対して最も遠い側に位置する前記配線基板の辺に沿って形成されていることを特徴とする電子部品の実装構造。
(付記18)
付記14乃至17いずれか一項記載の電子部品の実装構造であって、
前記開口部の前記外周部分を画定する前記絶縁膜の端部の断面形状は、上広がりのテーパ形状であることを特徴とする電子部品の実装構造。
(付記19)
複数の外部接続端子が形成された面を下向きにしたフェイスダウン状態で電子部品が配線基板に実装され、接着剤を介して前記電子部品が前記配線基板に固着される半導体装置であって、
前記電子部品が実装される前記配線基板の面には、絶縁膜が形成され、
前記電子部品の前記外部接続端子が接続される電極を備えた複数の隣接する配線パターンを共通して部分的に開口するように、開口部が前記絶縁膜に形成されており、
前記開口部の外周部分のうち前記配線基板の中心側に位置する箇所において、前記開口部の端面は、前記配線パターンが延在する方向に対して斜め方向に形成されていることを特徴とする半導体装置。
(付記20)
付記19記載の半導体装置であって、
前記配線パターン上には導電部材が設けられ、
前記導電部材を介して前記電子部品の前記外部接続端子と対応する前記配線基板の前記電極とが接続されることを特徴とする半導体装置。
31、101 配線基板
32 半導体素子
34 配線パターン
35 凸状外部接続端子
36 ボンディング電極
37、37D ソルダーレジスト層
38、38A、38B、38C、38D、102 開口部
41 導電部材
42 アンダーフィル材
X 半導体素子32の外周領域
Claims (8)
- 複数の外部接続端子が形成された面を下向きにしたフェイスダウン状態で電子部品が実装され、接着剤を介して前記電子部品が固着される配線基板であって、
前記電子部品が実装される面には、絶縁膜が形成され、
前記電子部品の前記外部接続端子が接続される電極を備えた複数の隣接する配線パターンを共通して部分的に開口するように、開口部が前記絶縁膜に形成されており、
前記開口部の外周部分のうち当該配線基板の中心側に位置する箇所において、前記開口部の端面は、前記配線パターンが延在する方向に対して斜め方向に形成された部分を有していること、及び、前記開口部内で露出している前記配線パターンのそれぞれの露出面積が互いに等しいこと、を特徴とする配線基板。 - 請求項1記載の配線基板であって、
前記開口部内で露出している前記配線パターンは、直線状に延在形成されていることを特徴する配線基板。 - 請求項2記載の配線基板であって、
前記電極の配列方向は、前記配線パターンの延在形成方向と垂直の方向であることを特徴とする配線基板。 - 請求項1乃至3いずれか一項記載の配線基板であって、
前記開口部の前記外周部分を画定する前記絶縁膜の端部の断面形状は、上広がりのテーパ形状であることを特徴とする配線基板。 - 複数の外部接続端子が形成された面を下向きにしたフェイスダウン状態で電子部品が配線基板に実装され、接着剤を介して前記電子部品が前記配線基板に固着される電子部品の実装構造であって、
前記電子部品が実装される前記配線基板の面には、絶縁膜が形成され、
前記電子部品の前記外部接続端子が接続される電極を備えた複数の隣接する配線パターンを共通して部分的に開口するように、開口部が前記絶縁膜に形成されており、
前記開口部の外周部分のうち前記配線基板の中心側に位置する箇所において、前記開口部の端面は、前記配線パターンが延在する方向に対して斜め方向に形成された部分を有していること、及び、前記開口部内で露出している前記配線パターンのそれぞれの露出面積が互いに等しいこと、を特徴とする電子部品の実装構造。 - 請求項5記載の電子部品の実装構造であって、
前記配線パターン上には導電部材が設けられ、
前記導電部材を介して前記電子部品の前記外部接続端子と対応する前記配線基板の前記電極とが接続されることを特徴とする電子部品の実装構造。 - 複数の外部接続端子が形成された面を下向きにしたフェイスダウン状態で電子部品が配線基板に実装され、接着剤を介して前記電子部品が前記配線基板に固着される半導体装置であって、
前記電子部品が実装される前記配線基板の面には、絶縁膜が形成され、
前記電子部品の前記外部接続端子が接続される電極を備えた複数の隣接する配線パターンを共通して部分的に開口するように、開口部が前記絶縁膜に形成されており、
前記開口部の外周部分のうち前記配線基板の中心側に位置する箇所において、前記開口部の端面は、前記配線パターンが延在する方向に対して斜め方向に形成された部分を有していること、及び、前記開口部内で露出している前記配線パターンのそれぞれの露出面積が互いに等しいこと、を特徴とする半導体装置。 - 請求項7記載の半導体装置であって、
前記配線パターン上には導電部材が設けられ、
前記導電部材を介して前記電子部品の前記外部接続端子と対応する前記配線基板の前記電極とが接続されることを特徴とする半導体装置。
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JP2007069346A JP5018155B2 (ja) | 2007-03-16 | 2007-03-16 | 配線基板、電子部品の実装構造、及び半導体装置 |
TW97108468A TWI470707B (zh) | 2007-03-16 | 2008-03-11 | 佈線板及電子元件之安裝結構 |
US12/047,811 US8659168B2 (en) | 2007-03-16 | 2008-03-13 | Wiring board for flip-chip mounting, mounting structure of electronic components on wiring board, and semiconductor device including wiring board |
KR1020080023741A KR101008891B1 (ko) | 2007-03-16 | 2008-03-14 | 배선 기판, 전자 부품의 실장 구조 및 반도체 장치 |
CN2008100861753A CN101266963B (zh) | 2007-03-16 | 2008-03-17 | 布线板、电子部件的安装结构以及半导体器件 |
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JP2830853B2 (ja) | 1996-08-08 | 1998-12-02 | 松下電器産業株式会社 | バンプ付電子部品の実装方法 |
JP3390664B2 (ja) * | 1997-10-16 | 2003-03-24 | 新光電気工業株式会社 | フリップチップ実装用基板及びフリップチップ実装構造 |
JP3539177B2 (ja) | 1998-01-23 | 2004-07-07 | 松下電器産業株式会社 | 電子部品の実装方法 |
JP3420076B2 (ja) | 1998-08-31 | 2003-06-23 | 新光電気工業株式会社 | フリップチップ実装基板の製造方法及びフリップチップ実装基板及びフリップチップ実装構造 |
JP2002050833A (ja) | 2000-08-01 | 2002-02-15 | Mitsumi Electric Co Ltd | フレキシブルプリント基板 |
JP2003046213A (ja) * | 2001-07-31 | 2003-02-14 | Optrex Corp | 液晶パネル用可撓配線板 |
US7070207B2 (en) * | 2003-04-22 | 2006-07-04 | Ibiden Co., Ltd. | Substrate for mounting IC chip, multilayerd printed circuit board, and device for optical communication |
JP4175197B2 (ja) * | 2003-06-27 | 2008-11-05 | 株式会社デンソー | フリップチップ実装構造 |
KR100546346B1 (ko) * | 2003-07-23 | 2006-01-26 | 삼성전자주식회사 | 재배선 범프 형성방법 및 이를 이용한 반도체 칩과 실장구조 |
JP4308608B2 (ja) * | 2003-08-28 | 2009-08-05 | 株式会社ルネサステクノロジ | 半導体装置 |
JP4298559B2 (ja) * | 2004-03-29 | 2009-07-22 | 新光電気工業株式会社 | 電子部品実装構造及びその製造方法 |
JP3833669B2 (ja) | 2004-04-08 | 2006-10-18 | シャープ株式会社 | 半導体装置および半導体装置の製造方法 |
JP2006286818A (ja) | 2005-03-31 | 2006-10-19 | Fujinon Corp | フレキシブルプリント基板及びその接続方法 |
JP4817892B2 (ja) * | 2005-06-28 | 2011-11-16 | 富士通セミコンダクター株式会社 | 半導体装置 |
JP3115062U (ja) | 2005-07-25 | 2005-11-04 | ハリマ化成株式会社 | 回路パターン |
JP4740765B2 (ja) * | 2006-02-24 | 2011-08-03 | エルピーダメモリ株式会社 | 半導体装置及びその製造方法 |
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2007
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- 2008-03-11 TW TW97108468A patent/TWI470707B/zh not_active IP Right Cessation
- 2008-03-13 US US12/047,811 patent/US8659168B2/en active Active
- 2008-03-14 KR KR1020080023741A patent/KR101008891B1/ko active IP Right Grant
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Also Published As
Publication number | Publication date |
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US20080224325A1 (en) | 2008-09-18 |
CN101266963A (zh) | 2008-09-17 |
KR101008891B1 (ko) | 2011-01-17 |
TW200841408A (en) | 2008-10-16 |
CN101266963B (zh) | 2011-11-09 |
TWI470707B (zh) | 2015-01-21 |
JP2008235365A (ja) | 2008-10-02 |
KR20080084713A (ko) | 2008-09-19 |
US8659168B2 (en) | 2014-02-25 |
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