JP4696712B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4696712B2 JP4696712B2 JP2005177095A JP2005177095A JP4696712B2 JP 4696712 B2 JP4696712 B2 JP 4696712B2 JP 2005177095 A JP2005177095 A JP 2005177095A JP 2005177095 A JP2005177095 A JP 2005177095A JP 4696712 B2 JP4696712 B2 JP 4696712B2
- Authority
- JP
- Japan
- Prior art keywords
- opening
- semiconductor chip
- semiconductor device
- solder
- external terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Description
図5(a)は従来のCSP系パッケージの一例である半導体装置を説明するための模式的な断面図であり、ここで示す半導体装置101は、半導体チップ102がインターポーザー基板103の表面に形成されたソルダーレジスト(図示せず)上にダイボンド材104を介して接着されている。また、半導体チップ上の外部端子105はAuワイヤー106でインターポーザー基板の半導体チップの搭載領域の周辺領域に形成されたAuパッド107と接続され、Auパッドは半導体チップ搭載側の配線パターン(図示せず)に接続され、半導体チップ搭載側の配線パターンはビアにより実装基板側の配線パターン(図示せず)に接続され、実装基板側の配線パターンは実装基板側接続端子108と接続され、この実装基板側接続端子と半田バンプ109が接続されている。なお、半導体チップ、Auワイヤー及び半導体チップ側の配線パターンがモールド樹脂110によって完全に被覆されている。
また、外部端子と略垂直に導電材料から成る接続部材を形成することによって、半導体チップ上の外部端子とバンプとの電気的接続が容易になる。
図1は本発明を適用した半導体装置の一例を説明するための模式的な断面図及び斜視図であり、ここで示す半導体装置1は、外部端子2が形成された半導体チップ3と、半導体チップの外部端子の形成面にフィルムタイプやペーストタイプの接着材4で貼り合わせられた絶縁材料(例えばポリイミド材料)から成る厚みが70μm程度のボール保持材5と、外部端子からはんだバンプ側に外部端子に略垂直に接続された長さが50μm程度の金細線6と、この金細線と電気的に接続されると共に、後述するボール保持材に形成された開口部7を閉塞する直径が約300μm程度のはんだバンプ8から構成されている。
なお、ボール保持材の厚さ(ここでは70μm)よりも金細線の長さ(ここでは50μm)を短くすることによって、はんだボールの搭載時にはんだボールが金細線に接触して浮き上がることを防止することができる。
即ち、図4(c)で示す様に、接着材が開口部の非形成領域の全面に塗布された場合には、開口部内にはんだボールを引き込む際に開口部内の空気の逃げ場がないために、ボイドが発生することが考えられるが、図4(d)で示す様に、接着材が半導体チップとボール保持材を接着するのに必要最低限の領域のみに塗布された場合には、開口部内にはんだボールを引き込む際に開口部内の空気が半導体チップとボール保持材との間隙に逃げ場を有することとなり、ボイドの発生を抑制できると考えられる。なお、本実施例では、開口部と外部端子の大きさを略同一としているが、開口部内の空気が半導体チップとボール保持材との間隙に逃げ込むことができる程度の隙間はあると考えられる。
具体的には、無電解めっき法や圧着法によりボール保持材の表面全体に導電膜を形成した後に、汎用のエッチング技術を用いて導電膜のエッチング除去を行うことによって、ボール保持材に形成される開口部の周辺領域に予め導電膜を形成し、その後、開口部を形成しても良い。
即ち、本発明を適用した半導体装置では、半導体チップの外部端子を下側(はんだバンプ側)に向けて、金細線を介して最短距離で外部端子とはんだバンプとを接続しているために、半導体チップの外部端子が上側(はんだバンプとは反対側)に向けられていた従来の半導体装置の様にボンディングワイヤーを一度上方に立ち上げた後にUターンさせるといった接続方式を採用する必要がなく、ボンディングワイヤーを立ち上げるために必要だった高さ分だけ半導体装置の薄型化が実現できることとなる。
また、半導体チップの外部端子を下側に向けて、金細線を介して最短距離で外部端子とはんだバンプとを接続しているために、即ち、従来の半導体装置の様に、半導体チップの搭載領域の周辺領域にボンディングワイヤーの接続先であるAuパッドを形成し、このAuパッドから再配線を行って外部端子とはんだバンプとの電気的接続を確保するといった接続方式を採用していないために、半導体チップの周辺領域にAuパッドを形成するために必要だった領域分だけ半導体装置の小型化が実現できることとなる。
2 外部端子
3 半導体チップ
4 接着材
5 ボール保持材
6 金細線
7 開口部
8 はんだバンプ
9 導電膜
10 半導体ウェハ
11 絶縁材
Claims (3)
- 外部端子が形成された半導体チップと、
該半導体チップの前記外部端子の形成面側に設けられ、前記外部端子の形成領域に対応する領域に開口部を有する絶縁材料から成る絶縁部材と、
少なくとも前記絶縁部材表面の前記開口部の周辺領域に形成された導電膜と、
前記外部端子に垂直に設けられた導電材料から成ると共に、その長さが前記絶縁部材の厚さよりも小さく構成されることでその先端部が前記開口部内に位置する接続部材と、
前記開口部を閉塞すると共に、前記接続部材と電気的に接続されたバンプとを備える
ことを特徴とする半導体装置。 - 前記導電膜は、前記絶縁部材表面の前記開口部の周辺領域及び前記開口部の側壁に形成された
ことを特徴とする請求項1に記載の半導体装置。 - 前記半導体チップと前記絶縁部材は、前記半導体チップ若しくは前記絶縁部材の所定領域に塗布された接着材料を介して貼り合わせられた
ことを特徴とする請求項1に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005177095A JP4696712B2 (ja) | 2005-06-17 | 2005-06-17 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005177095A JP4696712B2 (ja) | 2005-06-17 | 2005-06-17 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006351886A JP2006351886A (ja) | 2006-12-28 |
JP4696712B2 true JP4696712B2 (ja) | 2011-06-08 |
Family
ID=37647406
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005177095A Expired - Fee Related JP4696712B2 (ja) | 2005-06-17 | 2005-06-17 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4696712B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5077337B2 (ja) * | 2009-12-22 | 2012-11-21 | 株式会社デンソー | モールドパッケージおよびその製造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09321168A (ja) * | 1996-03-22 | 1997-12-12 | Shinko Electric Ind Co Ltd | 半導体パッケージ及び半導体装置 |
JP2000124258A (ja) * | 1998-10-12 | 2000-04-28 | Shinko Electric Ind Co Ltd | 半導体装置とその製造方法 |
JP2002305215A (ja) * | 2001-04-05 | 2002-10-18 | Sharp Corp | 半導体装置およびこれを用いた積層構造体 |
-
2005
- 2005-06-17 JP JP2005177095A patent/JP4696712B2/ja not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09321168A (ja) * | 1996-03-22 | 1997-12-12 | Shinko Electric Ind Co Ltd | 半導体パッケージ及び半導体装置 |
JP2000124258A (ja) * | 1998-10-12 | 2000-04-28 | Shinko Electric Ind Co Ltd | 半導体装置とその製造方法 |
JP2002305215A (ja) * | 2001-04-05 | 2002-10-18 | Sharp Corp | 半導体装置およびこれを用いた積層構造体 |
Also Published As
Publication number | Publication date |
---|---|
JP2006351886A (ja) | 2006-12-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10297582B2 (en) | BVA interposer | |
KR101478875B1 (ko) | 반도체 다이를 패키징하는 패키지 온 패키지 장치 및 방법 | |
US20180114786A1 (en) | Method of forming package-on-package structure | |
JP2009506572A (ja) | 相互接続構造を含むマイクロフィーチャ組立品およびそのような相互接続構造を形成するための方法 | |
JP2011061004A (ja) | 半導体装置及びその製造方法 | |
JP2008235365A (ja) | 配線基板、電子部品の実装構造、及び半導体装置 | |
JP5358089B2 (ja) | 半導体装置 | |
US10276465B2 (en) | Semiconductor package assembly | |
KR100843705B1 (ko) | 금속 범프를 갖는 반도체 칩 패키지 및 그 제조방법 | |
JP4696712B2 (ja) | 半導体装置 | |
US20070278635A1 (en) | Microelectronic package having solder-filled through-vias | |
US8975758B2 (en) | Semiconductor package having interposer with openings containing conductive layer | |
JP3824545B2 (ja) | 配線基板、それを用いた半導体装置、それらの製造方法 | |
JP2012138394A (ja) | 半導体装置の製造方法 | |
KR100485590B1 (ko) | 솔더 페이스트 프린트를 이용한 웨이퍼 범핑 방법 | |
US8703533B2 (en) | Semiconductor package and method for manufacturing the same | |
CN107978584B (zh) | 芯片封装结构及其制造方法 | |
JP2012146882A (ja) | 半導体装置 | |
JP5838312B2 (ja) | インターポーザおよびその製造方法 | |
KR100762909B1 (ko) | 플립 칩 패키지의 제조 방법 | |
TW201546915A (zh) | 不具有迴銲連接之積體電路封裝系統及其製造方法 | |
KR100790683B1 (ko) | 플립칩 패키지 및 그 제조방법 | |
JP2012174900A (ja) | 半導体装置の製造方法 | |
CN113380752A (zh) | 半导体结构及其制造方法 | |
JP2008021710A (ja) | 半導体モジュールならびにその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080430 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100611 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100615 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100804 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20100830 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20101116 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110108 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110201 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110214 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |