JP4477966B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4477966B2 JP4477966B2 JP2004226600A JP2004226600A JP4477966B2 JP 4477966 B2 JP4477966 B2 JP 4477966B2 JP 2004226600 A JP2004226600 A JP 2004226600A JP 2004226600 A JP2004226600 A JP 2004226600A JP 4477966 B2 JP4477966 B2 JP 4477966B2
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- terminals
- solder
- main surface
- terminal
- semiconductor device
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Description
図1は本発明の実施の形態の半導体装置の製造方法で用いられる配線基板の配線パターンの一例を示す平面図、図2は図1に示すA部の構造を示す拡大部分平面図、図3は本発明の実施の形態の半導体装置の製造方法におけるフリップチップ接続までの組み立ての一例を示す組み立てフロー図、図4は本発明の実施の形態の半導体装置の製造方法におけるフリップチップ接続後の組み立ての一例を示す組み立てフロー図、図5は図3に示す組み立てフローにおける熱圧着工程の一例を示す拡大断面図、図6は本発明の実施の形態の半導体装置の製造方法における配線基板の端子列への半田形成方法の2つの例を比較して示す断面図、図7は本発明の実施の形態の半導体装置の製造方法における端子列への半田ペーストの塗布状態の一例を示す部分断面図、図8は図7に示す半田ペーストの塗布状態の洗浄後の構造と迎え半田無し領域の第2の端子の構造の一例を示す部分断面図、図9は本発明の実施の形態の半導体装置の製造方法におけるフリップチップ接続の構造の一例を示す拡大部分断面図、図10および図11はそれぞれ本発明の実施の形態の半導体装置の製造方法における変形例のフリップチップ接続の構造を示す拡大部分断面図、図12〜図14はそれぞれ図1に示すA部の構造の変形例を示す拡大部分平面図、図15は本発明の実施の形態の変形例の配線基板の構造を示す拡大部分平面図である。
1a 主面
1b 裏面
1c パッド(電極)
1d 金バンプ(突起電極)
1e チップ内配線
2 半導体チップ(他の半導体チップ)
2a 主面
2b 裏面
3 半田ペースト
4 半田層
5 パッケージ基板(配線基板)
5a 主面
5b 裏面
5c 配線部
5d ダミー端子
5e フリップチップ用端子(第1の端子)
5f ワイヤ接続用端子(第2の端子)
5g 金めっき(貴金属めっき)
5h ソルダレジスト壁部(絶縁性壁部)
5i 信号配線
5j GND配線
5k 絶縁膜
5m 接続部
6 ワイヤ
7 NCP(非導電性の樹脂接着剤)
8 粘着膜
9 半田粉末
10 フラックス
11 半田ボール
12 封止体
13 SIP(半導体装置)
14 ノズル
15 加圧ブロック
16 多点式ノズル
17 ステージ
Claims (8)
- 以下の工程を含むことを特徴とする半導体装置の製造方法:
(a)平面形状が四角形から成る主面、前記主面の辺に沿って形成された複数の第1端子、前記複数の第1端子の配列の端部に設けられたダミー端子、前記複数の第1端子のそれぞれと繋がる第1配線部、前記ダミー端子と繋がる第2配線部、前記ダミー端子及び前記複数の第1端子のそれぞれに形成された半田層、前記複数の第1端子に近接して形成された複数の第2端子、および前記ダミー端子、前記複数の第1端子及び前記複数の第2端子のそれぞれが露出し、かつ前記第1及び第2配線部のそれぞれが覆われるように、前記主面上に形成された絶縁性壁部を有する配線基板を準備する工程;
(b)前記(a)工程の後、第1主面、前記第1主面に形成された複数の第1パッド、および前記第1主面とは反対側の第1裏面を有する第1半導体チップを、前記第1主面が前記配線基板の主面と対向するように、複数の突起電極を介して前記配線基板の前記主面上に配置する工程;
(c)前記(b)工程の後、加熱することで前記半田層を溶融させ、前記複数の突起電極と前記半田層とを接続する工程;
ここで、
前記半田層は以下の工程(a1)−(a2)により形成される;
(a1)半田の粒子を含有するフラックスを、前記絶縁性壁部から露出する領域に塗布する工程;
(a2)前記(a1)工程の後、前記フラックスを加熱することにより前記半田を溶融させる工程。 - 請求項1記載の半導体装置の製造方法において、
前記(a2)工程により前記半田層を形成した後、さらに洗浄を行って隣接する前記第1端子間の前記半田を除去することを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記複数の第2端子は、貴金属めっきで覆われており、
前記(c)工程の後、第2主面、前記第2主面に形成された複数の第2パッド、および前記第2主面とは反対側の第2裏面を有する第2半導体チップを、前記第2裏面が前記第1半導体チップの前記第1裏面と対向するように、前記第1半導体チップ上に配置し、
前記第2半導体チップの前記複数の第2パッドと前記配線基板の前記複数の第2端子とを、複数のワイヤを介してそれぞれ接続することを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記ダミー端子は前記第1半導体チップと絶縁されていることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記ダミー端子は、前記複数の第1端子のうちの端部の第1端子と繋がる前記第1配線
部と、前記第2配線部を介して接続されていることを特徴とする半導体装置の製造方法。 - 請求項5記載の半導体装置の製造方法において、
前記第1端子は、GND配線、または電源配線であることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(a)工程の後、かつ前記(b)工程の前に、前記配線基板の前記主面に樹脂接着剤を配置することを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(c)工程の後、前記配線基板の主面と前記第1半導体チップの前記第1主面との間にアンダーフィル封止材を供給することを特徴とする半導体装置の製造方法。
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JP4742844B2 (ja) * | 2005-12-15 | 2011-08-10 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP4685660B2 (ja) * | 2006-02-24 | 2011-05-18 | アルプス電気株式会社 | 半導体部品の配線構造 |
JP2008205057A (ja) * | 2007-02-19 | 2008-09-04 | Matsushita Electric Ind Co Ltd | 半導体装置及び半導体装置の製造方法 |
FR2914490B1 (fr) * | 2007-03-26 | 2009-05-29 | Commissariat Energie Atomique | Procede de soudure de deux elements entre eux au moyen d'un materiau de brasure. |
KR100924552B1 (ko) * | 2007-11-30 | 2009-11-02 | 주식회사 하이닉스반도체 | 반도체 패키지용 기판 및 이를 갖는 반도체 패키지 |
JP5293147B2 (ja) | 2008-03-19 | 2013-09-18 | 富士通株式会社 | 電子部品 |
JP5378707B2 (ja) * | 2008-05-29 | 2013-12-25 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP5058144B2 (ja) * | 2008-12-25 | 2012-10-24 | 新光電気工業株式会社 | 半導体素子の樹脂封止方法 |
JP5264585B2 (ja) | 2009-03-24 | 2013-08-14 | パナソニック株式会社 | 電子部品接合方法および電子部品 |
KR101632399B1 (ko) | 2009-10-26 | 2016-06-23 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
JP5433543B2 (ja) * | 2010-09-27 | 2014-03-05 | ローム株式会社 | 半導体装置 |
US8710654B2 (en) | 2011-05-26 | 2014-04-29 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
JP5774922B2 (ja) | 2011-07-01 | 2015-09-09 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
US9426898B2 (en) * | 2014-06-30 | 2016-08-23 | Kulicke And Soffa Industries, Inc. | Thermocompression bonders, methods of operating thermocompression bonders, and interconnect methods for fine pitch flip chip assembly |
CN107426916B (zh) * | 2017-09-19 | 2019-05-31 | 北京嘉楠捷思信息技术有限公司 | Pcb的结构及设计方法 |
DE102018125901A1 (de) * | 2018-10-18 | 2020-04-23 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung eines elektronischen Bauelements, Halbleiterchip, elektronisches Bauelement und Verfahren zur Herstellung eines Halbleiterchips |
US11152328B2 (en) * | 2018-12-13 | 2021-10-19 | eLux, Inc. | System and method for uniform pressure gang bonding |
KR20220026189A (ko) * | 2020-08-25 | 2022-03-04 | 삼성전자주식회사 | 반도체 패키지 |
US12040298B2 (en) * | 2021-07-09 | 2024-07-16 | Changxin Memory Technologies, Inc. | Packaging method and packaging structure thereof |
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