JP4565931B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4565931B2 JP4565931B2 JP2004245893A JP2004245893A JP4565931B2 JP 4565931 B2 JP4565931 B2 JP 4565931B2 JP 2004245893 A JP2004245893 A JP 2004245893A JP 2004245893 A JP2004245893 A JP 2004245893A JP 4565931 B2 JP4565931 B2 JP 4565931B2
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Description
図1は本発明の実施の形態1の半導体装置の製造に用いられる配線基板の構造と接着剤の塗布位置の一例を示す平面図、図2は本発明の実施の形態1の半導体装置の製造方法におけるフリップチップ接続までの組み立ての一例を示す組み立てフロー図、図3は本発明の実施の形態1の半導体装置の製造方法におけるフリップチップ接続後の組み立ての一例を示す組み立てフロー図、図4は図2に示す組み立てフローにおける熱圧着工程の一例を示す拡大断面図、図5は図4に示すA部の構造を示す拡大部分断面図、図6は本発明の実施の形態1の変形例の配線基板の配線パターンを示す平面図、図7は図6に示すB部の構造を示す拡大部分平面図、図8は図6に示す変形例の配線基板を用いた半導体装置の製造方法におけるフリップチップ接続後の構造の一例を示す平面図、図9は図6に示す変形例の配線基板を用いた半導体装置の製造方法における2段めの半導体チップへのワイヤボンディング後の構造の一例を示す平面図である。
図10は本発明の実施の形態2の半導体装置の製造方法によって組み立てられた半導体装置の構造の一例を示す断面図、図11は図10に示す半導体装置の組み立てに用いられる配線基板の構造と接着剤の塗布位置の一例を示す平面図、図12は図10に示す半導体装置の組み立てにおけるフリップチップ接続後の構造の一例を示す平面図、図13は図10に示す半導体装置の組み立てにおける2段めの半導体チップへのワイヤボンディング後の構造の一例を示す平面図、図14は図10に示す半導体装置の組み立てにおける3段めの半導体チップへのワイヤボンディング後の構造の一例を示す平面図である。
1a 主面
1b 裏面
1c パッド(電極)
1d 金バンプ(突起電極)
1e 側面
2 半導体チップ(他の半導体チップ)
2a 主面
2b 裏面
2c パッド(電極)
3 半導体チップ
3a 主面
3b 裏面
3c パッド
4 半田層
5 パッケージ基板(配線基板)
5a 主面
5b 裏面
5c 配線
5d 溝部
5e フリップチップ用端子(端子)
5f ワイヤ接続用端子(端子)
5g 第2溝部
5h ソルダレジスト膜(絶縁膜)
6 ワイヤ
7 NCP(接着剤)
8 メモリ用チップ
9 はみ出し距離
10 SIP(半導体装置)
11 半田ボール
12 封止体
13 SIP(半導体装置)
14 ノズル
15 加圧ブロック
16 多点式ノズル
17 ステージ
Claims (9)
- (a)平面形状が、互いに対向する第1辺と、前記第1辺と交差する方向に延在し、互いに対向する第2辺を有する四角形から成り、主面と、前記第1辺に沿って前記主面に形成された複数のフリップチップ用端子と、前記第2辺に沿って前記主面に形成された複数のワイヤ接続用端子と、前記複数のフリップチップ用端子及び前記複数のワイヤ接続用端子のそれぞれを露出するように前記主面上に形成された絶縁膜と、前記複数のワイヤ接続用端子よりも内側の領域において前記第2辺に沿って前記絶縁膜に形成された複数の溝部とを有する配線基板を準備する工程、
(b)主面と、前記主面に形成された複数の電極と、前記複数の電極のそれぞれに形成された複数の突起電極と、前記主面と反対側の裏面とを有する第1半導体チップを準備する工程、
(c)前記配線基板の主面において、中央部に接着剤を配置する工程、
(d)前記第1半導体チップの前記主面を前記配線基板の前記主面に対向させて、前記第1半導体チップを前記配線基板に搭載する工程、
(e)前記第1半導体チップの前記裏面を押圧し、前記配線基板の前記複数のフリップチップ用端子と前記第1半導体チップの前記複数の突起電極とを熱圧着によって接続する工程、
(f)前記複数の電極が形成された主面と、前記主面と反対側の裏面とを有する第2半導体チップを準備する工程、
(g)前記第2半導体チップの前記裏面が前記第1半導体チップの前記裏面と対向するように、前記第2半導体チップを前記第1半導体チップ上に搭載する工程、
(h)前記第2半導体チップの前記複数の電極と前記配線基板の前記複数のワイヤ接続用端子とをそれぞれ複数のワイヤで電気的に接続する工程、
を含むことを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、前記(c)工程では、前記配線基板の主面において、前記複数のフリップチップ用端子及び前記複数の溝部に囲まれた領域にペースト状の接着剤を配置することを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記複数のフリップチップ用端子及び前記複数の溝部よりも外側で、前記複数のワイヤ接続用端子よりも内側には第2溝部が形成されていることを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記(b)工程では、平面形状が、互いに対向する第3辺と、前記第3辺と交差する方向に延在し、互いに対向する第4辺を有する四角形から成り、前記主面と、前記第3辺に沿って前記主面に形成された前記複数の電極と、前記複数の電極のそれぞれに形成された前記複数の突起電極と、前記主面と反対側の前記裏面とを有する前記第1半導体チップを準備することを特徴とする半導体装置の製造方法。
- 請求項4記載の半導体装置の製造方法において、前記(d)工程では、前記第1半導体チップの前記第4辺が前記溝部と平面的に重なるように、前記第1半導体チップの前記主面を前記配線基板の前記主面に対向させて、前記第1半導体チップを前記配線基板に搭載することを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記(h)工程の後、前記第1半導体チップ、前記第2半導体チップ、前記複数のワイヤを封止用樹脂により封止することを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記配線基板の前記主面は、前記複数の溝部のそれぞれから露出していることを特徴とする半導体装置の製造方法。
- (a)平面形状が、互いに対向する第1辺と、前記第1辺と交差する方向に延在し、互いに対向する第2辺を有する四角形から成り、主面と、前記第1辺のみに沿って前記主面に形成された複数のフリップチップ用端子と、前記第2辺に沿って前記主面に形成された複数のワイヤ接続用端子と、前記複数のフリップチップ用端子及び複数のワイヤ接続用端子のそれぞれを露出するように前記主面上に形成された絶縁膜と、前記複数のワイヤ接続用端子よりも内側の領域において前記第2辺のみに沿って前記絶縁膜に形成された複数の溝部とを有する配線基板を準備する工程、
(b)平面形状が、互いに対向する第3辺と、前記第3辺と交差する方向に延在し、互いに対向する第4辺を有する四角形から成り、主面と、前記第3辺のみに沿って前記主面に形成された複数の電極と、前記複数の電極のそれぞれに形成された複数の突起電極と、前記主面と反対側の裏面とを有する第1半導体チップを準備する工程、
(c)前記配線基板の主面において、中央部に接着剤を配置する工程、
(d)前記第1半導体チップの前記主面を前記配線基板の前記主面に対向させて、前記第1半導体チップを前記配線基板に搭載する工程、
(e)前記第1半導体チップの前記裏面を押圧し、前記配線基板の前記複数のフリップチップ用端子と前記第1半導体チップの前記複数の突起電極とを熱圧着によって接続する工程、
(f)前記複数の電極が形成された主面と、前記主面と反対側の裏面とを有する第2半導体チップを準備する工程、
(g)前記第2半導体チップの前記裏面が前記第1半導体チップの前記裏面と対向するように、前記第2半導体チップを前記第1半導体チップ上に搭載する工程、
(h)前記第2半導体チップの前記複数の電極と前記配線基板の前記複数のワイヤ接続用端子とをそれぞれ複数のワイヤで電気的に接続する工程、
を含むことを特徴とする半導体装置の製造方法。 - 請求項8記載の半導体装置の製造方法において、前記(c)工程で使用する前記接着剤は、ペースト状から成ることを特徴とする半導体装置の製造方法。
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Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05283478A (ja) * | 1991-12-23 | 1993-10-29 | Motorola Inc | ポリマーアンダーフィルの拡張を制御した半導体デバイス組立体 |
JPH07122592A (ja) * | 1993-10-27 | 1995-05-12 | Fujitsu Ltd | 半導体装置の製造方法並びにその方法に使用する接合樹脂及び樹脂形成装置 |
JPH08181166A (ja) * | 1994-12-22 | 1996-07-12 | Ibiden Co Ltd | プリント配線板 |
JPH09120975A (ja) * | 1995-10-24 | 1997-05-06 | Seiko Epson Corp | 半導体チップの実装構造 |
JPH1098077A (ja) * | 1996-09-20 | 1998-04-14 | Ricoh Co Ltd | 半導体装置の製造方法 |
JPH11186322A (ja) * | 1997-10-16 | 1999-07-09 | Fujitsu Ltd | フリップチップ実装用基板及びフリップチップ実装構造 |
JPH11219984A (ja) * | 1997-11-06 | 1999-08-10 | Sharp Corp | 半導体装置パッケージおよびその製造方法ならびにそのための回路基板 |
JPH11261044A (ja) * | 1998-03-11 | 1999-09-24 | Matsushita Electric Ind Co Ltd | 固体撮像素子付半導体装置及び該半導体装置の製造方法 |
JP2000208544A (ja) * | 1999-01-14 | 2000-07-28 | Toshiba Corp | ベアicチップおよび半導体装置 |
JP2001230274A (ja) * | 2000-02-14 | 2001-08-24 | Fujitsu Ltd | 実装基板及び実装方法 |
JP2001244384A (ja) * | 2000-02-28 | 2001-09-07 | Matsushita Electric Works Ltd | ベアチップ搭載プリント配線基板 |
JP2001267452A (ja) * | 2000-03-16 | 2001-09-28 | Hitachi Ltd | 半導体装置 |
JP2002124538A (ja) * | 2000-10-12 | 2002-04-26 | Eastern Co Ltd | 回路基板 |
JP2004063805A (ja) * | 2002-07-29 | 2004-02-26 | Sony Corp | 半導体装置 |
JP2004349399A (ja) * | 2003-05-21 | 2004-12-09 | Nec Corp | 部品実装基板 |
JP2005011978A (ja) * | 2003-06-19 | 2005-01-13 | Matsushita Electric Ind Co Ltd | 半導体装置 |
-
2004
- 2004-08-25 JP JP2004245893A patent/JP4565931B2/ja not_active Expired - Fee Related
Patent Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05283478A (ja) * | 1991-12-23 | 1993-10-29 | Motorola Inc | ポリマーアンダーフィルの拡張を制御した半導体デバイス組立体 |
JPH07122592A (ja) * | 1993-10-27 | 1995-05-12 | Fujitsu Ltd | 半導体装置の製造方法並びにその方法に使用する接合樹脂及び樹脂形成装置 |
JPH08181166A (ja) * | 1994-12-22 | 1996-07-12 | Ibiden Co Ltd | プリント配線板 |
JPH09120975A (ja) * | 1995-10-24 | 1997-05-06 | Seiko Epson Corp | 半導体チップの実装構造 |
JPH1098077A (ja) * | 1996-09-20 | 1998-04-14 | Ricoh Co Ltd | 半導体装置の製造方法 |
JPH11186322A (ja) * | 1997-10-16 | 1999-07-09 | Fujitsu Ltd | フリップチップ実装用基板及びフリップチップ実装構造 |
JPH11219984A (ja) * | 1997-11-06 | 1999-08-10 | Sharp Corp | 半導体装置パッケージおよびその製造方法ならびにそのための回路基板 |
JPH11261044A (ja) * | 1998-03-11 | 1999-09-24 | Matsushita Electric Ind Co Ltd | 固体撮像素子付半導体装置及び該半導体装置の製造方法 |
JP2000208544A (ja) * | 1999-01-14 | 2000-07-28 | Toshiba Corp | ベアicチップおよび半導体装置 |
JP2001230274A (ja) * | 2000-02-14 | 2001-08-24 | Fujitsu Ltd | 実装基板及び実装方法 |
JP2001244384A (ja) * | 2000-02-28 | 2001-09-07 | Matsushita Electric Works Ltd | ベアチップ搭載プリント配線基板 |
JP2001267452A (ja) * | 2000-03-16 | 2001-09-28 | Hitachi Ltd | 半導体装置 |
JP2002124538A (ja) * | 2000-10-12 | 2002-04-26 | Eastern Co Ltd | 回路基板 |
JP2004063805A (ja) * | 2002-07-29 | 2004-02-26 | Sony Corp | 半導体装置 |
JP2004349399A (ja) * | 2003-05-21 | 2004-12-09 | Nec Corp | 部品実装基板 |
JP2005011978A (ja) * | 2003-06-19 | 2005-01-13 | Matsushita Electric Ind Co Ltd | 半導体装置 |
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