JP5095074B2 - パッケージ積層構造 - Google Patents
パッケージ積層構造 Download PDFInfo
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- JP5095074B2 JP5095074B2 JP2004239945A JP2004239945A JP5095074B2 JP 5095074 B2 JP5095074 B2 JP 5095074B2 JP 2004239945 A JP2004239945 A JP 2004239945A JP 2004239945 A JP2004239945 A JP 2004239945A JP 5095074 B2 JP5095074 B2 JP 5095074B2
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- semiconductor chip
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- H01L2924/01—Chemical elements
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- H01L2924/01013—Aluminum [Al]
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- H01L2924/11—Device type
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- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
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- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
図2ないし図6は、本発明の第1実施例によるBGAパッケージ及びその製造方法を説明するための図面であって、図4ないし図6は、図2のA’−A”断面に対応する。そして、図7は本発明の第1実施例の変形例によるBGAパッケージの断面図である。
図8ないし図14は、本発明の第2実施例によるBGAパッケージ及びその製造方法を説明するための図面であって、図10及び図11は、図8のB’−B”断面に対応する。そして、図13及び図14は、図12のC’−C”断面に対応する。
図15ないし図17は、本発明の実施例によるパッケージを積層した構造の例を示した断面図である。特に、前の第2実施例で説明したようなBGAパッケージP3の基板ランド230を利用してパッケージを積層した構造である。
200 半導体チップ
205 チップパッド
215 ソルダーボールパッド
220 基板
225 ボンドフィンガー
230 基板ランド
250 接着材
260 ソルダーボール
270 導電性ワイヤ
280 封止材
Claims (5)
- 2つ以上積層された単位パッケージを含み、各単位パッケージは、
活性面のエッジに複数のチップパッドが形成され、前記チップパッドに連結されたリルーティング配線パターンにより活性面の中央部に複数のソルダーボールパッドが形成された半導体チップと、
前記半導体チップの非活性面に塗布された接着材を通じて前記半導体チップが接着され、上面にボンドフィンガーと下面に基板ランドとが形成された基板と、
前記チップパッドと前記ボンドフィンガー間を電気的に連結する導電性ワイヤと、
前記ソルダーボールパッドを通じて前記半導体チップに付着される複数のソルダーボールと、
前記基板上の前記半導体チップと前記導電性ワイヤとを覆うように形成されるが、前記ソルダーボールは露出させるように形成された封止材と、を含み、
上部パッケージの前記ソルダーボールと下部パッケージの前記基板ランドとが接続されたパッケージ積層構造。 - 前記基板は対応する前記半導体チップのエッジ外側に延長されたエッジを有することを特徴とする請求項1に記載のパッケージ積層構造。
- 最上部に積層された他のBGAパッケージをさらに含み、前記他のBGAパッケージのソルダーボールとその下部パッケージの基板ランドとが接続され、
前記他のBGAパッケージは、
基板と、
前記基板の上面に接着された半導体チップと、
前記半導体チップの上面に具備された複数のソルダーボールと、
前記基板上の前記半導体チップを覆うように形成されるが、前記ソルダーボールは露出させるように形成された封止材と、を含む請求項1に記載のパッケージのパッケージ積層構造。 - 積層された上部パッケージと下部パッケージとを含み、
前記上部パッケージは、
基板と、
前記基板の上面に接着された半導体チップと、
前記半導体チップの上面に具備された複数のソルダーボールと、
前記基板上の前記半導体チップを覆うように形成されるが、前記ソルダーボールは露出させるように形成された封止材と、を含み、
前記下部パッケージは、
活性面のエッジに複数のチップパッドが形成され、前記チップパッドに連結されたリルーティング配線パターンにより活性面の中央部に複数のソルダーボールパッドが形成された半導体チップと、
前記半導体チップの非活性面に塗布された接着材を通じて前記半導体チップが接着され、上面にボンドフィンガーと下面に基板ランドとが形成された基板と、
前記チップパッドと前記ボンドフィンガー間を電気的に連結する導電性ワイヤと、
前記ソルダーボールパッドを通じて前記半導体チップに付着される複数のソルダーボールと、
前記基板上の前記半導体チップと前記導電性ワイヤとを覆うように形成されるが、前記ソルダーボールは露出させるように形成された封止材と、を含み、
前記上部パッケージの前記ソルダーボールと前記下部パッケージの前記基板ランドとが接続されたパッケージ積層構造。 - 前記基板は対応する前記半導体チップのエッジ外側に延長されたエッジを有することを特徴とする請求項4に記載のパッケージ積層構造。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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KR2003-057514 | 2003-08-20 | ||
KR1020030057514A KR100574947B1 (ko) | 2003-08-20 | 2003-08-20 | Bga 패키지, 그 제조방법 및 bga 패키지 적층 구조 |
Publications (2)
Publication Number | Publication Date |
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JP2005072587A JP2005072587A (ja) | 2005-03-17 |
JP5095074B2 true JP5095074B2 (ja) | 2012-12-12 |
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JP2004239945A Expired - Fee Related JP5095074B2 (ja) | 2003-08-20 | 2004-08-19 | パッケージ積層構造 |
Country Status (3)
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US (1) | US7245008B2 (ja) |
JP (1) | JP5095074B2 (ja) |
KR (1) | KR100574947B1 (ja) |
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2003
- 2003-08-20 KR KR1020030057514A patent/KR100574947B1/ko not_active IP Right Cessation
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2004
- 2004-06-30 US US10/879,066 patent/US7245008B2/en not_active Expired - Fee Related
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US7245008B2 (en) | 2007-07-17 |
KR20050022558A (ko) | 2005-03-08 |
US20050040529A1 (en) | 2005-02-24 |
JP2005072587A (ja) | 2005-03-17 |
KR100574947B1 (ko) | 2006-05-02 |
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