JP2006066551A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2006066551A JP2006066551A JP2004245893A JP2004245893A JP2006066551A JP 2006066551 A JP2006066551 A JP 2006066551A JP 2004245893 A JP2004245893 A JP 2004245893A JP 2004245893 A JP2004245893 A JP 2004245893A JP 2006066551 A JP2006066551 A JP 2006066551A
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Abstract
【解決手段】 パッケージ基板5の主面5aにソルダレジスト膜5hの表面より凹んだ溝部5dが形成され、この溝部5dが半導体チップ1の内側から外側にまたがるように半導体チップ1を配置し、その後、半導体チップ1を押圧してフリップチップ接続することにより、半導体チップ1の下部からはみ出ようとするNCP7を溝部5dに流れ込ませてNCP7のはみ出し量を低減することができ、その結果、NCP7はチップ搭載領域の外側に配置されたワイヤ接続用端子まで到達しないため、ワイヤ接続用端子にNCP7が付着することを防止でき、半導体装置におけるワイヤボンディングの接続信頼性を向上できる。
【選択図】 図4
Description
図1は本発明の実施の形態1の半導体装置の製造に用いられる配線基板の構造と接着剤の塗布位置の一例を示す平面図、図2は本発明の実施の形態1の半導体装置の製造方法におけるフリップチップ接続までの組み立ての一例を示す組み立てフロー図、図3は本発明の実施の形態1の半導体装置の製造方法におけるフリップチップ接続後の組み立ての一例を示す組み立てフロー図、図4は図2に示す組み立てフローにおける熱圧着工程の一例を示す拡大断面図、図5は図4に示すA部の構造を示す拡大部分断面図、図6は本発明の実施の形態1の変形例の配線基板の配線パターンを示す平面図、図7は図6に示すB部の構造を示す拡大部分平面図、図8は図6に示す変形例の配線基板を用いた半導体装置の製造方法におけるフリップチップ接続後の構造の一例を示す平面図、図9は図6に示す変形例の配線基板を用いた半導体装置の製造方法における2段めの半導体チップへのワイヤボンディング後の構造の一例を示す平面図である。
図10は本発明の実施の形態2の半導体装置の製造方法によって組み立てられた半導体装置の構造の一例を示す断面図、図11は図10に示す半導体装置の組み立てに用いられる配線基板の構造と接着剤の塗布位置の一例を示す平面図、図12は図10に示す半導体装置の組み立てにおけるフリップチップ接続後の構造の一例を示す平面図、図13は図10に示す半導体装置の組み立てにおける2段めの半導体チップへのワイヤボンディング後の構造の一例を示す平面図、図14は図10に示す半導体装置の組み立てにおける3段めの半導体チップへのワイヤボンディング後の構造の一例を示す平面図である。
1a 主面
1b 裏面
1c パッド(電極)
1d 金バンプ(突起電極)
1e 側面
2 半導体チップ(他の半導体チップ)
2a 主面
2b 裏面
2c パッド(電極)
3 半導体チップ
3a 主面
3b 裏面
3c パッド
4 半田層
5 パッケージ基板(配線基板)
5a 主面
5b 裏面
5c 配線
5d 溝部
5e フリップチップ用端子(端子)
5f ワイヤ接続用端子(端子)
5g 第2溝部
5h ソルダレジスト膜(絶縁膜)
6 ワイヤ
7 NCP(接着剤)
8 メモリ用チップ
9 はみ出し距離
10 SIP(半導体装置)
11 半田ボール
12 封止体
13 SIP(半導体装置)
14 ノズル
15 加圧ブロック
16 多点式ノズル
17 ステージ
Claims (17)
- 半導体チップがフリップチップ接続される半導体装置の製造方法であって、
(a)主面と裏面を有しており、前記主面に複数の配線と複数の端子と前記複数の配線を覆う絶縁膜とが形成され、前記絶縁膜の表面より凹んだ溝部を有する配線基板を準備する工程と、
(b)前記配線基板の前記主面上に接着剤を配置する工程と、
(c)前記配線基板の前記主面上において前記溝部が半導体チップの内側から外側にまたがるように前記半導体チップを前記接着剤を介して配置する工程と、
(d)前記半導体チップの電極上に接続された突起電極と、前記配線基板の端子とを熱圧着によって接続して前記配線基板に前記半導体チップをフリップチップ接続する工程とを有し、
前記(d)工程において前記半導体チップの裏面を押圧した際に、前記半導体チップの下部からはみ出ようとする前記接着剤を前記溝部に流れ込ませることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、前記(b)工程で、前記接着剤として、異方性導電フィルム、非導電性の樹脂フィルム、異方性導電ペーストもしくは非導電性の樹脂ペーストの何れかを配置することを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記(b)工程で、前記配線基板の前記主面上において前記溝部より内側に前記接着剤を配置することを特徴とする半導体装置の製造方法。
- 請求項3記載の半導体装置の製造方法において、前記溝部より内側に前記接着剤を塗布することを特徴とする半導体装置の製造方法。
- 請求項3記載の半導体装置の製造方法において、前記溝部より内側に前記接着剤を貼り付けることを特徴とする半導体装置の製造方法。
- 請求項3記載の半導体装置の製造方法において、前記接着剤としてペースト状の接着剤を配置することを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記溝部は、前記半導体チップの電極が設けられていない箇所に対応して配置されており、さらに前記半導体チップの端部に沿って配置されていることを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記(d)工程の後、前記半導体チップの裏面上に他の半導体チップを搭載し、その後、前記他の半導体チップの電極と前記配線基板の前記溝部の外側に配置された端子とを導電性のワイヤで接続することを特徴とする半導体装置の製造方法。
- 請求項8記載の半導体装置の製造方法において、前記半導体チップおよび前記他の半導体チップは、両者とも対向する2辺に沿って電極を有しており、前記半導体チップの電極列の方向に対して前記他の半導体チップの電極列の方向を90°変えて配置することを特徴とする半導体装置の製造方法。
- 請求項9記載の半導体装置の製造方法において、前記半導体チップおよび前記他の半導体チップは、両者ともメモリ回路を有したメモリチップであることを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記溝部は、前記絶縁膜の開口によって形成されていることを特徴とする半導体装置の製造方法。
- 半導体チップがフリップチップ接続される半導体装置の製造方法であって、
(a)主面と裏面を有しており、前記主面に複数の配線と複数の端子と前記複数の配線を覆う絶縁膜とが形成され、前記絶縁膜の表面より凹んだ溝部を有する配線基板を準備する工程と、
(b)前記配線基板の前記主面上に接着剤を配置する工程と、
(c)前記配線基板の前記主面上において前記溝部が半導体チップの側面の下部に配置されるように前記半導体チップを前記接着剤を介して配置する工程と、
(d)前記半導体チップの電極上に接続された突起電極と、前記配線基板の端子とを熱圧着によって接続して前記配線基板に前記半導体チップをフリップチップ接続する工程とを有し、
前記(d)工程において前記半導体チップの裏面を押圧した際に、前記半導体チップの下部からはみ出ようとする前記接着剤を前記溝部に流れ込ませることを特徴とする半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、前記(b)工程で、前記接着剤として、異方性導電フィルム、非導電性の樹脂フィルム、異方性導電ペーストもしくは非導電性の樹脂ペーストの何れかを配置することを特徴とする半導体装置の製造方法。
- 請求項12記載の半導体装置の製造方法において、前記(b)工程で、前記配線基板の前記主面上において前記溝部より内側に前記接着剤を配置することを特徴とする半導体装置の製造方法。
- 請求項14記載の半導体装置の製造方法において、前記接着剤としてペースト状の接着剤を配置することを特徴とする半導体装置の製造方法。
- 請求項12記載の半導体装置の製造方法において、前記溝部は、前記半導体チップの電極が設けられていない箇所に対応して配置されており、さらに前記半導体チップの端部に沿って配置されていることを特徴とする半導体装置の製造方法。
- 請求項12記載の半導体装置の製造方法において、前記溝部は、前記絶縁膜の開口によって形成されていることを特徴とする半導体装置の製造方法。
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009537970A (ja) * | 2006-05-19 | 2009-10-29 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング | 絶縁性接続媒体を用いた電気伝導性接続部 |
JP2014130993A (ja) * | 2012-11-28 | 2014-07-10 | Waseda Univ | 積層構造体の製造方法 |
JP2017123446A (ja) * | 2016-01-08 | 2017-07-13 | 株式会社日立製作所 | 半導体装置および半導体パッケージ装置 |
CN107507825A (zh) * | 2016-06-14 | 2017-12-22 | 三星电子株式会社 | 半导体封装 |
WO2022264822A1 (ja) * | 2021-06-14 | 2022-12-22 | 株式会社村田製作所 | 二次電池 |
Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05283478A (ja) * | 1991-12-23 | 1993-10-29 | Motorola Inc | ポリマーアンダーフィルの拡張を制御した半導体デバイス組立体 |
JPH07122592A (ja) * | 1993-10-27 | 1995-05-12 | Fujitsu Ltd | 半導体装置の製造方法並びにその方法に使用する接合樹脂及び樹脂形成装置 |
JPH08181166A (ja) * | 1994-12-22 | 1996-07-12 | Ibiden Co Ltd | プリント配線板 |
JPH09120975A (ja) * | 1995-10-24 | 1997-05-06 | Seiko Epson Corp | 半導体チップの実装構造 |
JPH1098077A (ja) * | 1996-09-20 | 1998-04-14 | Ricoh Co Ltd | 半導体装置の製造方法 |
JPH11186322A (ja) * | 1997-10-16 | 1999-07-09 | Fujitsu Ltd | フリップチップ実装用基板及びフリップチップ実装構造 |
JPH11219984A (ja) * | 1997-11-06 | 1999-08-10 | Sharp Corp | 半導体装置パッケージおよびその製造方法ならびにそのための回路基板 |
JPH11261044A (ja) * | 1998-03-11 | 1999-09-24 | Matsushita Electric Ind Co Ltd | 固体撮像素子付半導体装置及び該半導体装置の製造方法 |
JP2000208544A (ja) * | 1999-01-14 | 2000-07-28 | Toshiba Corp | ベアicチップおよび半導体装置 |
JP2001230274A (ja) * | 2000-02-14 | 2001-08-24 | Fujitsu Ltd | 実装基板及び実装方法 |
JP2001244384A (ja) * | 2000-02-28 | 2001-09-07 | Matsushita Electric Works Ltd | ベアチップ搭載プリント配線基板 |
JP2001267452A (ja) * | 2000-03-16 | 2001-09-28 | Hitachi Ltd | 半導体装置 |
JP2002124538A (ja) * | 2000-10-12 | 2002-04-26 | Eastern Co Ltd | 回路基板 |
JP2004063805A (ja) * | 2002-07-29 | 2004-02-26 | Sony Corp | 半導体装置 |
JP2004349399A (ja) * | 2003-05-21 | 2004-12-09 | Nec Corp | 部品実装基板 |
JP2005011978A (ja) * | 2003-06-19 | 2005-01-13 | Matsushita Electric Ind Co Ltd | 半導体装置 |
-
2004
- 2004-08-25 JP JP2004245893A patent/JP4565931B2/ja not_active Expired - Fee Related
Patent Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05283478A (ja) * | 1991-12-23 | 1993-10-29 | Motorola Inc | ポリマーアンダーフィルの拡張を制御した半導体デバイス組立体 |
JPH07122592A (ja) * | 1993-10-27 | 1995-05-12 | Fujitsu Ltd | 半導体装置の製造方法並びにその方法に使用する接合樹脂及び樹脂形成装置 |
JPH08181166A (ja) * | 1994-12-22 | 1996-07-12 | Ibiden Co Ltd | プリント配線板 |
JPH09120975A (ja) * | 1995-10-24 | 1997-05-06 | Seiko Epson Corp | 半導体チップの実装構造 |
JPH1098077A (ja) * | 1996-09-20 | 1998-04-14 | Ricoh Co Ltd | 半導体装置の製造方法 |
JPH11186322A (ja) * | 1997-10-16 | 1999-07-09 | Fujitsu Ltd | フリップチップ実装用基板及びフリップチップ実装構造 |
JPH11219984A (ja) * | 1997-11-06 | 1999-08-10 | Sharp Corp | 半導体装置パッケージおよびその製造方法ならびにそのための回路基板 |
JPH11261044A (ja) * | 1998-03-11 | 1999-09-24 | Matsushita Electric Ind Co Ltd | 固体撮像素子付半導体装置及び該半導体装置の製造方法 |
JP2000208544A (ja) * | 1999-01-14 | 2000-07-28 | Toshiba Corp | ベアicチップおよび半導体装置 |
JP2001230274A (ja) * | 2000-02-14 | 2001-08-24 | Fujitsu Ltd | 実装基板及び実装方法 |
JP2001244384A (ja) * | 2000-02-28 | 2001-09-07 | Matsushita Electric Works Ltd | ベアチップ搭載プリント配線基板 |
JP2001267452A (ja) * | 2000-03-16 | 2001-09-28 | Hitachi Ltd | 半導体装置 |
JP2002124538A (ja) * | 2000-10-12 | 2002-04-26 | Eastern Co Ltd | 回路基板 |
JP2004063805A (ja) * | 2002-07-29 | 2004-02-26 | Sony Corp | 半導体装置 |
JP2004349399A (ja) * | 2003-05-21 | 2004-12-09 | Nec Corp | 部品実装基板 |
JP2005011978A (ja) * | 2003-06-19 | 2005-01-13 | Matsushita Electric Ind Co Ltd | 半導体装置 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009537970A (ja) * | 2006-05-19 | 2009-10-29 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング | 絶縁性接続媒体を用いた電気伝導性接続部 |
JP2014130993A (ja) * | 2012-11-28 | 2014-07-10 | Waseda Univ | 積層構造体の製造方法 |
JP2017123446A (ja) * | 2016-01-08 | 2017-07-13 | 株式会社日立製作所 | 半導体装置および半導体パッケージ装置 |
CN107507825A (zh) * | 2016-06-14 | 2017-12-22 | 三星电子株式会社 | 半导体封装 |
WO2022264822A1 (ja) * | 2021-06-14 | 2022-12-22 | 株式会社村田製作所 | 二次電池 |
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