CN101142673B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN101142673B
CN101142673B CN2005800490847A CN200580049084A CN101142673B CN 101142673 B CN101142673 B CN 101142673B CN 2005800490847 A CN2005800490847 A CN 2005800490847A CN 200580049084 A CN200580049084 A CN 200580049084A CN 101142673 B CN101142673 B CN 101142673B
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resin
substrate
mentioned
semiconductor device
constitutes
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CN101142673A (zh
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永井孝一
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Socionext Inc
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Fujitsu Semiconductor Ltd
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    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract

在印刷电路板(1)上形成由树脂构成的基底(3)。在基底(3)上涂敷粘结剂(4)，并在该粘结剂(4)上装载并固定IC芯片(5)。然后，利用BGA型的封装树脂(7)密封IC芯片(5)。基底(3)和封装树脂(7)，由相同的树脂构成。

Description

半导体器件及其制造方法
技术领域
本发明涉及一种具有焊球阵列(BGA：Ball Grid Array)封装的半导体器件及其制造方法。
背景技术
当前，对于数码摄像机、数字移动电话以及笔记本计算机等便携式电子设备的小型化、薄型化及轻量化的要求越来越高。为了满足这种要求，针对近几年的VLSI等半导体器件，在三年之内实现了百分之七十左右的缩小化。但是，仅这样还远远不够，而作为重要问题而提出有如何提高安装基板上的部件安装密度。而且，对该课题进行着研究和开发。
作为现有的半导体器件的封装，例如采用了管脚插入型(THD：ThroughHall Mount Device)封装和表面安装型(SMD：Surface Mount Device)封装。在管脚插入型封装中，向设置在印刷电路板上的贯通孔中插入管脚而进行安装。作为该例子，可举例DIP(Dual Inline Package：双列直插式封装)和PGA(Pin Grid Array：引脚网格阵列)等。在表面安装型封装中，将管脚焊接在基板的表面上而进行安装。作为该例子，可举例QFP(Quad Flat Package：四侧引脚扁平封装)、TCP(Tape Carrier Package：带载封装)、BGA(BallGrid Array：焊球阵列)和CSP(Chip Size Package：芯片尺寸封装)等。
在BGA和CSP中，在印刷电路板的一侧面上安装固定有半导体集成电路(IC)芯片。此外，在印刷电路板的另一侧面上安装有由焊锡球构成的多个外部连接端子。而且，向外部连接端子导出有IC芯片的多个电极。图9是示出了现有的BGA封装的立体图，图10是示出了现有的BGA封装的剖面图。
在现有的BGA封装中，在内插板(interposer)用印刷电路板101的一侧面上安装有IC芯片(半导体集成电路)105。作为构成印刷电路板101的绝缘层，例如使用玻璃环氧树脂层、聚酰亚胺层等。此外，在印刷电路板101的另一侧面上设置有由焊锡球构成的多个外部连接端子108。在设置于IC芯片105的上表面上的多个电极110上连接有键合金属丝(bonding wire)106，在键合金属丝106的另一端上，连接有设置于印刷电路板101上的焊盘102。在印刷电路板101内设置有导电层(未图示)。焊盘102通过导电层而与外部连接端子108连接在一起。而且，形成有覆盖IC芯片105等的封装树脂107，从而构成了被封装的半导体器件。
而且，如图11所示，在向主印刷电路板151进行安装时，使半导体器件的各外部连接端子5与设置在主印刷电路板151上的印刷电路板端子152抵接，然后，利用回流焊使各外部连接端子5的下部熔化，从而将各外部连接端子5的下部熔敷在印刷电路板端子152上。
但是，若进行这样的安装，则如图12所示，由于回流焊时的热应力，内插板用印刷电路板101有时会翘曲。其结果，存在于半导体器件内部的IC芯片105也会弯曲。而且，在IC芯片105内包含着构成铁电存储器的铁电电容器等压电元件的情况下，由于对该压电元件会施加压缩应力或收缩应力，因此无法进行正常的工作。特别是在设置有铁电存储器的情况下，会失去数据保持功能，或者无法读出数据，或者发生误动作。
此外，即便是在进行回流焊时未曾发生过问题的IC芯片，伴随着使用时间的经过，也会向内部浸水而发生膨胀和变形。而且，如上所述那样，有时会发生误动作等。
专利文献1：JP特开2001-60638号公报
专利文献2：JP特开2001-156095号公报
专利文献3：JP特开2001-85458号公报
专利文献4：JP特开平7-45735号公报
发明内容
本发明的目的在于，提供一种能够缓和作用于IC芯片上的应力的BGA结构的半导体器件及其制造方法。
本发明者为了解决上述课题，反复进行精心研究的结果，发现了如下问题：在现有的BGA封装中，由于只在IC芯片105的上方存在树脂层107，因此作用于半导体器件上的应力的偏差大，从而发生了如上所述的弯曲和变形。
本申请的发明者将这样的问题作为着眼点，研究提出了如下所示发明。
在本发明涉及的第一半导体器件中设置有：基板；由树脂构成的基底，其设置在上述基板上；集成电路芯片，其设置在上述基底上；粘结剂或银膏，用于将上述集成电路芯片粘结在上述基底上；由树脂构成的焊球阵列型的封装材料，其用于密封上述集成电路芯片；以上述集成电路芯片的上表面为基准的上述封装材料的厚度在40μm以上。
另外，本发明还提供一种半导体器件，其特征在于，具有：基板，由树脂构成的基底，其设置在上述基板上，集成电路芯片，其设置在上述基底上，粘结剂或银膏，用于将上述集成电路芯片粘结在上述基底上，由树脂构成的焊球阵列型的封装材料，其用于密封上述集成电路芯片；上述基底的厚度在100μm至200μm的范围内。
另外，本发明还提供一种半导体器件，其特征在于，具有：基板，由树脂构成的基底，其设置在上述基板上，集成电路芯片，其设置在上述基底上，粘结剂或银膏，用于将上述集成电路芯片粘结在上述基底上，由树脂构成的焊球阵列型的封装材料，其用于密封上述集成电路芯片；上述基底由多芯片封装载带构成。
在本发明涉及的第二半导体器件中设置有：基板；金属板，其设置在上述基板上，而且，由形状记忆合金构成；集成电路芯片，其设置在上述金属板上；由树脂构成的焊球阵列型的封装材料，其用于密封上述集成电路芯片；由树脂构成的基底，其设置在上述基板和上述金属板之间。
在本发明涉及的第三半导体器件中设置有：基板；集成电路芯片，其设置在上述基板上；由树脂构成的焊球阵列型的封装材料，其用于密封上述集成电路芯片。并且，上述基板设有：第一及第二绝缘板；金属板，其被夹持在上述第一及第二绝缘板之间，而且，由相变温度为150℃至200℃的形状记忆合金构成。
另外，本发明还提供一种半导体器件的制造方法，其特征在于，包括：在基板上设置由树脂构成的基底的工序，使用粘结剂或银膏将集成电路芯片粘结在上述基底上的工序，利用由树脂构成的焊球阵列型的封装材料密封上述集成电路芯片的工序；以上述集成电路芯片的上表面为基准的上述封装材料的厚度在40μm以上。
另外，本发明还提供一种半导体器件的制造方法，其特征在于，包括：在基板上设置由树脂构成的基底的工序，使用粘结剂或银膏将集成电路芯片粘结在上述基底上的工序，利用由树脂构成的焊球阵列型的封装材料密封上述集成电路芯片的工序；上述基底的厚度在100μm至200μm的范围内。
另外，本发明还提供一种半导体器件的制造方法，其特征在于，包括：在基板上设置由树脂构成的基底的工序，使用粘结剂或银膏将集成电路芯片粘结在上述基底上的工序，利用由树脂构成的焊球阵列型的封装材料密封上述集成电路芯片的工序；上述基底由多芯片封装载带构成。
附图说明
图1A是按照工序顺序示出了本发明第一实施方式的半导体器件的制造方法的剖面图。
图1B是接着图1A而按照工序顺序示出了半导体器件的制造方法的剖面图。
图1C是接着图1B而按照工序顺序示出了半导体器件的制造方法的剖面图。
图2是示出了第一实施方式的半导体器件的剖面图。
图3是示出了本发明第二实施方式的半导体器件的剖面图。
图4是示出了本发明第三实施方式的半导体器件的剖面图。
图5是示出了Fe-Mn-Si类应力诱发形状记忆合金的温度特性的曲线图。
图6是示出了本发明第四实施方式的半导体器件的剖面图。
图7是示出了本发明第五实施方式的半导体器件的剖面图。
图8是具体示出了第五实施方式中的印刷电路板1c的剖面图。
图9是示出了现有的BGA封装的立体图。
图10是示出了现有的BGA封装的剖面图。
图11是示出了现有的BGA封装与主印刷电路板之间关系的剖面图。
图12是示出了印刷电路板11的弯曲的剖面图。
图13A是按照工序顺序示出了制造印刷电路板的方法的剖面图。
图13B是接着图13A而按照工序顺序示出了制造印刷电路板的方法的剖面图。
图13C是接着图13B而按照工序顺序示出了制造印刷电路板的方法的剖面图。
图13D是接着图13C而按照工序顺序示出了制造印刷电路板的方法的剖面图。
图13E是接着图13D而按照工序顺序示出了制造印刷电路板的方法的剖面图。
图13F是接着图13E而按照工序顺序示出了制造印刷电路板的方法的剖面图。
图13G是接着图13F而按照工序顺序示出了制造印刷电路板的方法的剖面图。
图13H是接着图13G而按照工序顺序示出了制造印刷电路板的方法的剖面图。
图13I是接着图13H而按照工序顺序示出了制造印刷电路板的方法的剖面图。
图13J是接着图13I而按照工序顺序示出了制造印刷电路板的方法的剖面图。
图13K是接着图13J而按照工序顺序示出了制造印刷电路板的方法的剖面图。
图13L是接着图13K而按照工序顺序示出了制造印刷电路板的方法的剖面图。
图13M是接着图13L而按照工序顺序示出了制造印刷电路板的方法的剖面图。
图13N是接着图13M而按照工序顺序示出了制造印刷电路板的方法的剖面图。
图13O是接着图13N而按照工序顺序示出了制造印刷电路板的方法的剖面图。
图14是示出了印刷电路板的例子的图。
具体实施方式
下面，参照附图具体说明本发明的实施方式。
(第一实施方式)
首先，关于本发明的第一实施方式进行说明。但在此，为了方便起见，关于半导体器件的剖面结构，与其制造方法一起进行说明。图1A至图1C是按照工序的顺序示出了本发明的第一实施方式的半导体器件的制造方法的剖面图，图2是示出了第一实施方式的半导体器件的剖面图。
在第一实施方式中，如图1A所示，首先，在形成有焊盘2的印刷电路板1上形成由树脂构成的基底3。将基底3的高度设定为例如100μm～200μm左右。作为印刷电路板1，例如可以使用玻璃环氧树脂基板。
接着，如图1B所示，在基底3上涂敷粘结剂4，并在粘结剂4上装载并固定半导体集成电路芯片(IC芯片)。也可以取代粘结剂4而使用银膏。作为IC芯片5，例如使用具有铁电存储器的芯片。IC芯片5的高度例如是200μm左右。
接着，如图1C所示，利用键合金属丝6，连接设置在IC芯片5上的端子(未图示)和焊盘2。然后，利用封装树脂7，密封IC芯片5和键合金属丝6等。这时，以IC芯片5的上表面为基准的封装树脂7的厚度优选为40μm以上。此外，作为封装树脂7，优先使用含有填料(filler)的树脂。接着，使用激光等，在封装树脂7的上表面刻印用于确定IC芯片5的编号等。在印刷电路板1的背面例如装载焊锡球8而作为外部连接端子。然后，虽无图示，但进行切割(Dicing)。另外，作为构成基底3的树脂，例如使用与封装树脂7同样的材料。但是，在该情况下，优先使构成基底3的树脂的填料含有量高于封装树脂7。
通过如上所述的方式，完成BGA封装结构的半导体器件。如图2所示，该半导体器件例如安装在主印刷电路板51上而被使用。
在这样的第一实施方式中，在IC芯片5的下方存在与封装树脂7同样的基底3。因此，即使封装树脂7伴随着吸湿和回流焊而受到应力的作用，在IC芯片5也会从其周围受到大致均匀的应力作用。因此，即使包含有构成铁电存储器的铁电电容器等压电元件，也不会发生误动作等。
此外，提高构成基底3的树脂的填料含有量，使得其吸湿量低于封装树脂7。因此，能够进一步缓和压缩应力。
进而，在本实施方式中，由于将以IC芯片5的上表面为基准的封装树脂7的厚度设定为40μm以上，因此即使利用激光进行了刻印，也不会对IC芯片5产生损伤。
(第二实施方式)
接着，关于本发明的第二实施方式进行说明。图3是示出了本发明的第二实施方式的半导体器件的剖面图。
在第二实施方式中，在印刷电路板1上粘贴有多芯片封装(MCP：MultiChip Package)载带(tape)9，并在该载带9上固定有IC芯片5。其他方面与第一实施方式的结构相同。
在由上述方式所构成的第二实施方式中，MCP载带9起到与第一实施方式中的基底3同样的作用。其结果，能够得到与第一实施方式同样的效果。
(第三实施方式)
接着，关于本发明的第三实施方式进行说明。图4是示出了本发明的第三实施方式的半导体器件的剖面图。
在第三实施方式中，在基底3上涂敷粘结剂4a，并在该粘结剂4a上粘贴由形状记忆合金构成的金属板11。进而，在金属板11上涂敷粘结剂4b，并在该粘结剂4b上装载并固定IC芯片5。构成金属板11的形状记忆合金例如为Fe-Mn-Si类应力诱发形状记忆合金，具有如图5所示的温度特性。即，该形状记忆合金以240℃～270℃左右的回流焊温度为分界发生相变。此外，也可以取代粘结剂4a和4b而使用银膏等。
在由上述方式所构成的第三实施方式中，即使在进行回流焊时产生热应力，但由形状记忆合金构成的金属板11想要复原为原来的形状，因此对IC芯片5不会作用应力，从而不会发生铁电存储器等的误动作。
此外，并非一定要设置基底3，但为了得到复合效果而要优先设置。
(第四实施方式)
接着，关于本发明的第四实施方式进行说明。图6是示出了本发明的第四实施方式的半导体器件的剖面图。
在第四实施方式中，在印刷电路板1上涂敷粘结剂4a，并在该粘结剂4a上粘贴由形状记忆合金构成的金属板11。进而，在金属板11上涂敷粘结剂4b，并在该粘结剂4b上粘贴由形状记忆合金构成的金属板11a。然后，在金属板11a上涂敷粘结剂4c，并在该粘结剂4c上装载并固定IC芯片5。此外，作为构成金属板11a的形状记忆合金，使用以85℃～100℃左右的温度为分界发生相变的合金。此外，也可以取代粘结剂4a～4c而使用银膏等。
在由如上所述方式所构成的第四实施方式中，通过金属板11的作用，也能够得到与第三实施方式同样的效果。进而，由于设置有金属板11a，因此即使在使用时温度上升到85℃～100℃左右而在封装树脂7产生热应力的情况下，也能够通过金属板11a的复原力来抵消该热应力。因此，对IC芯片5不会作用应力，从而不会发生铁电存储器等的误动作。85℃～100℃左右的温度是例如搭载在汽车上时所达到的温度。
另外，在第四实施方式中，虽未设置基底3，但也可以在印刷电路板1和粘结剂4a之间设置基底3。
(第五实施方式)
接着，关于本发明的第五实施方式进行说明。图7是示出了本发明的第五实施方式的半导体器件的剖面图，图8是详细示出了第五实施方式中的印刷电路板1c的剖面图。
在第五实施方式中，由2张玻璃环氧树脂基板1a、1b和它们所夹持的金属板12构成印刷电路板1c。金属板12例如由在150℃～200℃左右的温度下发生相变的形状记忆合金构成。而且，在印刷电路板1c上通过粘结剂4固定有IC芯片5。另外，150℃～200℃左右的温度是固化封装树脂7时的温度。
如图8所示，在印刷电路板1c上形成有多个贯通孔，并在该多个贯通孔的内面形成有绝缘膜13，而且在该绝缘膜13的内部填入有导电材料14。而且，在导电材料14上形成有焊盘2，并在焊盘2上连接有键合金属丝6。另一方面，在印刷电路板1c的背面侧，导电材料14和焊锡球8通过导电层15连接在一起。
在由如上所述的方式所构成的第五实施方式中，利用金属板12的复原力抵消固化时所产生的热应力。因此，能够防止伴随着该热应力的误动作。
另外，在第五实施方式中，虽未设置有基底3，但也可以在印刷电路板1c与粘结剂4之间设置基底3。
此外，也可以使金属板12的俯视观察时的大小小于玻璃环氧树脂基板1b和1c。在该情况下，也可以在金属板12的外侧形成引线和贯通孔。
在此，关于制造最适合于第五实施方式的印刷电路板的方法进行说明。图13A至图13O是按照工序顺序示出了制造印刷电路板的方法的剖面图。
首先，如图13A所示，在将导电层201和绝缘层202粘合在一起的基材的绝缘层202侧的面上，形成抗蚀剂图案203。
接着，如图13B所示，将抗蚀剂图案203作为掩膜，在绝缘层202上刻画图案。然后，去除抗蚀剂图案203。
接着，如图13C所示，例如利用溅射法，在绝缘层202上和绝缘层202的开口部内形成导电层204。
然后，如图13D所示，利用回蚀或CMP，对导电层204进行平整化。
接着，如图13E所示，在绝缘层202和导电层204上形成绝缘层205。进而，在绝缘层205上形成抗蚀剂图案217。
接着，如图13F所示，将抗蚀剂图案217作为掩膜，在绝缘层205上刻画图案。然后，去除抗蚀剂图案217。
接着，如图13G所示，例如利用溅射法，在绝缘层205上和绝缘层205的开口部内形成导电层206。
然后，如图13H所示，利用回蚀或CMP，对导电层206进行平整化。
接着，如图13I所示，在整个面上形成绝缘层216和形状记忆合金膜207。
接着，如图13J所示，在形状记忆合金膜207上形成抗蚀剂图案208。
接着，如图13K所示，将抗蚀剂图案208作为掩膜，在形状记忆合金膜207上刻画图案。
然后，如图13L所示，去除抗蚀剂图案208。然后，在形状记忆合金膜207上和形状记忆合金膜207的开口部内形成层间绝缘膜209。
接着，如图13M所示，利用回蚀或CMP，对层间绝缘膜209进行平整化。接着，在整个面上形成绝缘层210，并在该绝缘层210上形成抗蚀剂图案211。然后，将抗蚀剂图案211作为掩膜，在绝缘层210上刻画图案。
进而，如图13N所示，将抗蚀剂图案211作为掩膜，在层间绝缘膜209和绝缘层216上刻画图案。其结果，导电层206的一部分被露出。
接着，如图13O所示，去除抗蚀剂图案211。然后，在整个面上形成一直到达到导电层206的导电层212。也可以利用溅射法来形成导电层212。此外，作为导电层212而形成W膜，由此形成W插件。
然后，通过反复进行与这些同样的导电层和绝缘层的形成以及刻画图案，完成如图14所示的印刷电路板。在该印刷电路板中，在导电层212上连接有导电层213和214，在导电层214上连接有焊盘215。此外，在导电层201上形成有图案，并在导电层201连接有焊锡球8。另外，在这些导电层所构成的引线的周围，形成有绝缘层221和222。
此外，也可以相互组合各实施方式。例如，也可以对第五实施方式与第一～第四实施方式进行组合。进而，作为形状记忆合金，除了Fe-Mn-Si类合金以外，也可以使用Ti-Ni类合金。
另外，在专利文献1中公开了在印刷电路板内设置形状记忆部件的情况，但没有公开其相变温度。因此，在什么样的状态下发挥怎样样的功能是不明确的。
在专利文献2和3中公开了由形状记忆合金构成凸块(bump)部的情况。在专利文献4中公开了将半导体器件的顶部(cap)的一部分制作成形状记忆合金的情况。但都无法缓和回流焊时的热应力和固化时的热应力。
工业上的可利用性
如上所述，若根据本发明，则即使伴随着热应力以及/或吸湿而产生了应力，也能够缓和这些应力。因此，即使在集成电路芯片上设置有铁电电容器等压电元件，也能够避免其误动作。

Claims (26)

1.一种半导体器件，其特征在于，具有：
基板，
由树脂构成的基底，其设置在上述基板上，
集成电路芯片，其设置在上述基底上，
粘结剂或银膏，用于将上述集成电路芯片粘结在上述基底上，
由树脂构成的焊球阵列型的封装材料，其用于密封上述集成电路芯片；
以上述集成电路芯片的上表面为基准的上述封装材料的厚度在40μm以上。
2.如权利要求1所述的半导体器件，其特征在于，上述基底和封装材料由相同的树脂构成。
3.如权利要求1所述的半导体器件，其特征在于，在构成上述基底的树脂和构成上述封装材料的树脂中含有填料。
4.如权利要求3所述的半导体器件，其特征在于，构成上述基底的树脂的填料含有量高于构成上述封装树脂的树脂的填料含有量。
5.一种半导体器件，其特征在于，具有：
基板，
由树脂构成的基底，其设置在上述基板上，
集成电路芯片，其设置在上述基底上，
粘结剂或银膏，用于将上述集成电路芯片粘结在上述基底上，
由树脂构成的焊球阵列型的封装材料，其用于密封上述集成电路芯片；
上述基底的厚度在100μm至200μm的范围内。
6.如权利要求5所述的半导体器件，其特征在于，上述基底和封装材料由相同的树脂构成。
7.如权利要求5所述的半导体器件，其特征在于，在构成上述基底的树脂和构成上述封装材料的树脂中含有填料。
8.如权利要求7所述的半导体器件，其特征在于，构成上述基底的树脂的填料含有量高于构成上述封装树脂的树脂的填料含有量。
9.一种半导体器件，其特征在于，
基板，
由树脂构成的基底，其设置在上述基板上，
集成电路芯片，其设置在上述基底上，
粘结剂或银膏，用于将上述集成电路芯片粘结在上述基底上，
由树脂构成的焊球阵列型的封装材料，其用于密封上述集成电路芯片；
上述基底由多芯片封装载带构成。
10.如权利要求9所述的半导体器件，其特征在于，上述基底和封装材料由相同的树脂构成。
11.如权利要求9所述的半导体器件，其特征在于，在构成上述基底的树脂和构成上述封装材料的树脂中含有填料。
12.如权利要求11所述的半导体器件，其特征在于，构成上述基底的树脂的填料含有量高于构成上述封装树脂的树脂的填料含有量。
13.一种半导体器件，其特征在于，具有：
基板；
金属板，其设置在上述基板上，而且，由形状记忆合金构成；
集成电路芯片，其设置在上述金属板上；
由树脂构成的焊球阵列型的封装材料，其用于密封上述集成电路芯片；
由树脂构成的基底，其设置在上述基板和上述金属板之间。
14.如权利要求13所述的半导体器件，其特征在于，上述形状记忆合金在240℃至270℃的温度范围内发生相变。
15.如权利要求13所述的半导体器件，其特征在于，具有第二金属板，该第二金属板设置在上述基板和上述集成电路芯片之间，而且，由在与构成上述金属板的形状记忆合金不同的温度下发生相变的形状记忆合金构成。
16.如权利要求15所述的半导体器件，其特征在于，构成上述第二金属板的形状记忆合金在80℃至100℃的温度范围内发生相变。
17.如权利要求13所述的半导体器件，其特征在于，在构成上述基底的树脂和构成上述封装材料的树脂中含有填料。
18.如权利要求17所述的半导体器件，其特征在于，构成上述基底的树脂的填料含有量高于构成上述封装树脂的树脂的填料含有量。
19.一种半导体器件，其特征在于，具有：
基板；
集成电路芯片，其设置在上述基板上；
由树脂构成的焊球阵列型的封装材料，其用于密封上述集成电路芯片，
其中，上述基板具有：
第一及第二绝缘板；
金属板，其被夹持在上述第一及第二绝缘板之间，而且，由相变温度为150℃至200℃的形状记忆合金构成。
20.如权利要求19所述的半导体器件，其特征在于，具有由树脂构成的基底，该基底设置在上述基板和上述集成电路芯片之间。
21.如权利要求20所述的半导体器件，其特征在于，在构成上述基底的树脂和构成上述封装材料的树脂中含有填料。
22.如权利要求21所述的半导体器件，其特征在于，构成上述基底的树脂的填料含有量高于构成上述封装树脂的树脂的填料含有量。
23.如权利要求22所述的半导体器件，其特征在于，在俯视观察时，上述金属板小于上述第一及第二绝缘板。
24.一种半导体器件的制造方法，其特征在于，包括：
在基板上设置由树脂构成的基底的工序，
使用粘结剂或银膏将集成电路芯片粘结在上述基底上的工序，
利用由树脂构成的焊球阵列型的封装材料密封上述集成电路芯片的工序；
以上述集成电路芯片的上表面为基准的上述封装材料的厚度在40μm以上。
25.一种半导体器件的制造方法，其特征在于，包括：
在基板上设置由树脂构成的基底的工序，
使用粘结剂或银膏将集成电路芯片粘结在上述基底上的工序，
利用由树脂构成的焊球阵列型的封装材料密封上述集成电路芯片的工序；
上述基底的厚度在100μm至200μm的范围内。
26.一种半导体器件的制造方法，其特征在于，包括：
在基板上设置由树脂构成的基底的工序，
使用粘结剂或银膏将集成电路芯片粘结在上述基底上的工序，
利用由树脂构成的焊球阵列型的封装材料密封上述集成电路芯片的工序；
上述基底由多芯片封装载带构成。
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