JP5264585B2 - 電子部品接合方法および電子部品 - Google Patents
電子部品接合方法および電子部品 Download PDFInfo
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- JP5264585B2 JP5264585B2 JP2009071065A JP2009071065A JP5264585B2 JP 5264585 B2 JP5264585 B2 JP 5264585B2 JP 2009071065 A JP2009071065 A JP 2009071065A JP 2009071065 A JP2009071065 A JP 2009071065A JP 5264585 B2 JP5264585 B2 JP 5264585B2
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- electrode
- component
- dummy
- substrate
- electronic component
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
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Description
この半田自己集合を図17(a)〜(e)に基づいて説明する。
何故ならば、最外周の電極aにおいては、半田粒子が溶融、流動する経路Zにおいて、溶融半田が濡れ、留まる電極が存在しないからである。その結果、最外周の電極aには、エリア配置形状の内側電極bと比較し、自己集合される半田の量(体積)が必然的に多くなる。
本発明の電子部品接合方法は、第1電極群と前記第1電極群の外周に配置された第1のダミー電極列と前記第1のダミー電極列の外周で前記第1のダミー電極列のピッチ間に位置する第2のダミー電極列とを有する基板に、第2電極を有する部品を、実装する方法であって、前記第1電極群と、前記第1のダミー電極列と、前記第1電極群と前記第1のダミー電極との間に導電性粒子を含んだ接合樹脂を供給する供給工程と、前記第1電極と前記第2電極との間に隙間を保持し、かつ、前記基板と前記部品とを位置合わせする位置合わせ工程と、前記基板と前記部品とを加熱する加熱工程と、前記基板と前記部品を冷却して前記接合樹脂を凝固する冷却工程と、からなることを特徴とする。
本発明の電子部品接合方法は、第1電極を有する基板に、第2電極と前記第2電極に接続され前記第2電極のエリアから引き出された配線の途中上に位置するダミー電極とを有する部品を実装する方法であって、第1電極上に導電性粒子を含んだ接合樹脂を供給する供給工程と、前記第1電極と前記第2電極との間に隙間を保持し、かつ、前記基板と前記部品とを位置合わせする位置合わせ工程と、前記基板と前記部品とを加熱する加熱工程と、前記基板と前記部品を冷却して前記接合樹脂を凝固する冷却工程と、からなることを特徴とする。
本発明の電子部品接合方法は、第1電極を有する基板に、第2電極群と前記第2電極群の外周に配置された第1のダミー電極列と前記第1のダミー電極列の外周で前記第1のダミー電極列のピッチ間に位置する第2のダミー電極列とを有する部品を、実装する方法であって、前記第1電極に導電性粒子を含んだ接合樹脂を供給する供給工程と、前記第1電極と前記第2電極との間に隙間を保持し、かつ、前記基板と前記部品とを位置合わせする位置合わせ工程と、前記基板と前記部品とを加熱する加熱工程と、前記基板と前記部品を冷却して前記接合樹脂を凝固する冷却工程と、からなることを特徴とする。
本発明の電子部品は、第1電極と、前記第1電極に接続され前記第1電極のエリアから引き出された配線の途中上に位置するダミー電極とを有する基板と、第2電極を有する部品と、前記第1電極と前記第2電極との間に位置する導電性粒子を含む接合樹脂と、からなる電子部品であり、前記第1電極と前記第2電極を含む接合領域以外で、かつ、前記接合樹脂の内に、前記ダミー電極が形成されていることを特徴とする。
本発明の電子部品は、第1電極群と、前記第1電極群の外周に配置された第1のダミー電極列と、前記第1のダミー電極列の外周で前記第1のダミー電極列のピッチ間に位置する第2のダミー電極列とを有する基板と、第2電極を有する部品と、前記第1電極と前記第2電極との間に位置する導電性粒子を含む接合樹脂とからなる電子部品であり、前記第1電極と前記第2電極を含む接合領域以外で、かつ、前記接合樹脂の内に、前記第1のダミー電極と、前記第2のダミー電極が配置されたことを特徴とする。
本発明の電子部品は、第1電極を有する基板と、第2電極と前記第2電極に接続され前記第2電極のエリアから引き出された配線の途中上に位置するダミー電極とを有する部品と、前記第1電極と前記第2電極との間に位置する導電性粒子を含む接合樹脂と、からなる電子部品であり、前記第1電極と前記第2電極を含む接合領域以外で、かつ、前記接合樹脂の内に、前記ダミー電極が配置されていることを特徴とする。
本発明の電子部品は、第1電極を有する基板と、第2電極群と前記第2電極群の外周に配置された第1のダミー電極列と前記第1のダミー電極列の外周で前記第1のダミー電極列のピッチ間に位置する第2のダミー電極列とを有する部品と、前記第1電極と前記第2電極との間に位置する導電性粒子を含む接合樹脂と、からなる電子部品であり、前記第1電極と前記第2電極を含む接合領域以外で、かつ、前記接合樹脂の内に、前記第1のダミー電極と、前記第2のダミー電極とが形成されていることを特徴とする。
(実施の形態1)
図1〜図7は本発明の実施の形態1を示す。
なお、図1(b)においては、形成されているダミー電極15を全て覆う形状で接合樹脂4が供給されている事例を模式的に表したが、必ずしも接合樹脂4の供給時点で、全ての電極を覆う必要は無い。後の接合工程中において、接合樹脂4が流動して、ダミー電極15を覆えば良い。
回路基板1にエリア配置形成された電極2のうちの最外周の電極eの場合は、この電極eを中心とし、隣接する電極との距離を等間隔に分割したエリアE内に存在する半田粉3が接合工程において確率的に自己集合してくる。
しかし、過剰な半田が自己集合されたダミー電極15は、例え半田ショート14が発生したとしても、電気回路設計上、必要でない電極であるがため、電気特性上問題は無い。
以上の結果から、エリア配置された接合用電極の最外周部に、従来例のような半田ショート不良が発生することなく、回路基板1と部品5との接合を安定的に行える。
また、図1〜図3においては、接合用の電極2と電気的には、つながっていないダミー電極15の事例を示したが、本発明はこれに限定されない。例えば、エリア配置された接合用電極2から基板表層を引き回し、配線される回路パターン上に形成しても良い。
図1(a)に示す回路基板1として、グレードFR4のガラスエポキシ基板、厚み0.6mmの両面基板を用いた。回路基板1の上には、部品5の電極6との接合用の電極2を200μmピッチで、484ピン、エリア状に配置した。なお、電極2には、φ100μmサイズ、高さは、18μmで形成されたCuにNi/Auメッキを施したものを用いた。
図1(b)に示すように、回路基板1の電極2およびダミー電極15上には、以下の条件により接合樹脂4を供給し、回路基板1と部品5との接合を実施した。
(比較例1)
比較実験として、従来例の過剰半田吸収用のダミー電極15を設けない図18(a)に示す回路基板1でも接合評価を実施した。
この結果からも、電極2の外側に設けるダミー電極15には、接合電極部の半田ショートを抑制する効果が顕著にあることが明確となった。
例えば、図7に示すようにエリア配置された電極2から基板1を引き回して配線される回路パターン16上にダミー電極15を形成しても良い。この場合のダミー電極15は、形状が限定されるものではなく、任意の形状で良い。ダミー電極15の配置形状も、図7に示すように一列に並べるほかに、千鳥配置や1個飛ばしの配置でもよい。ダミー電極15が近接していても、このダミー電極15に引き付けられた半田は、回路パターン16にも流れて回路パターン16を濡らすことになるため、隣接したダミー電極15の間が半田ブリッジして短絡することは極めて少ない。この場合の具体的な構成としては、ソルダーレジストを、引き出される回路パターン16の接合領域エリア外の部分に設けない構造を挙げることができる。
(実施の形態2)
図11〜図16に基づいて本発明の実施の形態2を示す。
先ず、比較のために従来例を説明する。
図8(a)は回路基板1はグレードFR4のガラスエポキシ基板、厚み0.6mmの両面基板を用いた。回路基板1上には、電子部品との接合用電極2が150μmピッチで、240ピン、ペリフェラル状に配置されている。なお、基板電極2には、幅60μmサイズ、高さは、15μmで形成されたCuにNi/Auメッキを施したものを用いた。
接合樹脂4には、平均粒径20μmの半田粉3が50wt%、エポキシ樹脂22wt%、硬化剤22wt%、活性剤5wt%、硬化促進剤1wt%、含有された組成比により、構成されている材料を用いた。また、半田粉3の組成としては、SnBi系半田を用いた。
この接合事例では、図10に示すように回路基板1上にペリフェラル配置された電極2の接合を行う際に、その接合工程において、例えば、電極fを事例とした場合、電極fを中心とし、隣接する電極との距離を等間隔に分割、且つペリフェラル配置された電極の内外を広く含むエリアF内に存在する半田粉3が確率的に自己集合してくる。その結果、ペリフェラル配置された電極fの内外に広く分布していた半田粉3が、その流動経路Zに半田を濡れさす電極が存在しないため、接合に必要な半田量以上に集合してくるため、半田が過剰量となり、半田ショートとなったと推定される。
この結果から、ペリフェラル配置の電極構造においても、その内外に過剰半田吸収用のダミー電極15を設けることにより、接合電極部の半田ショートを抑制する効果が顕著にあることが明確となった。
上記の各実施の形態において、接合樹脂4に含まれている導電性粒子が半田粉3の場合を説明したが、導電性粒子としては半田コート銅粉、半田コート銀粉、低融点金属でコートされた金属粒子などの導電性粒子なども同様に使用できる。
2 回路基板の電極
3 半田粉(導電性粒子)
4 接合樹脂
5 部品
6 部品の電極
7 吸着ツール
8 ヒータ
9 ステージ
10 ヒータ
11 硬化樹脂成分
12 溶融半田
13 半田金属接合部
14 半田ショート不良部
15 過剰半田吸収用のダミー電極
16 引き回し配線
Claims (16)
- 第1電極と、前記第1電極に接続され前記第1電極のエリアから引き出された配線の途中上に位置するダミー電極とを有する基板に、第2電極を有する部品を実装する方法であって、
第1電極と、前記ダミー電極と、前記第1電極と前記ダミー電極との間に導電性粒子を含んだ接合樹脂を供給する供給工程と、
前記第1電極と前記第2電極との間に隙間を保持し、かつ、前記基板と前記部品とを位置合わせする位置合わせ工程と、
前記基板と前記部品とを加熱する加熱工程と、
前記基板と前記部品を冷却して前記接合樹脂を凝固する冷却工程と、
からなることを特徴とする電子部品接合方法。 - 第1電極群と前記第1電極群の外周に配置された第1のダミー電極列と前記第1のダミー電極列の外周で前記第1のダミー電極列のピッチ間に位置する第2のダミー電極列とを有する基板に、第2電極を有する部品を、実装する方法であって、
前記第1電極群と、前記第1のダミー電極列と、前記第1電極群と前記第1のダミー電極との間に導電性粒子を含んだ接合樹脂を供給する供給工程と、
前記第1電極と前記第2電極との間に隙間を保持し、かつ、前記基板と前記部品とを位置合わせする位置合わせ工程と、
前記基板と前記部品とを加熱する加熱工程と、
前記基板と前記部品を冷却して前記接合樹脂を凝固する冷却工程と、
からなることを特徴とする電子部品接合方法。 - 第1電極を有する基板に、第2電極と前記第2電極に接続され前記第2電極のエリアから引き出された配線の途中上に位置するダミー電極とを有する部品を実装する方法であって、
第1電極上に導電性粒子を含んだ接合樹脂を供給する供給工程と、
前記第1電極と前記第2電極との間に隙間を保持し、かつ、前記基板と前記部品とを位置合わせする位置合わせ工程と、
前記基板と前記部品とを加熱する加熱工程と、
前記基板と前記部品を冷却して前記接合樹脂を凝固する冷却工程と、
からなることを特徴とする電子部品接合方法。 - 第1電極を有する基板に、第2電極群と前記第2電極群の外周に配置された第1のダミー電極列と前記第1のダミー電極列の外周で前記第1のダミー電極列のピッチ間に位置する第2のダミー電極列とを有する部品を、実装する方法であって、
前記第1電極に導電性粒子を含んだ接合樹脂を供給する供給工程と、
前記第1電極と前記第2電極との間に隙間を保持し、かつ、前記基板と前記部品とを位置合わせする位置合わせ工程と、
前記基板と前記部品とを加熱する加熱工程と、
前記基板と前記部品を冷却して前記接合樹脂を凝固する冷却工程と、
からなることを特徴とする電子部品接合方法。 - 第1電極と、前記第1電極に接続され前記第1電極のエリアから引き出された配線の途中上に位置するダミー電極とを有する基板と、
第2電極を有する部品と、
前記第1電極と前記第2電極との間に位置する導電性粒子を含む接合樹脂と、からなる電子部品であり、
前記第1電極と前記第2電極を含む接合領域以外で、かつ、前記接合樹脂の内に、前記ダミー電極が形成されている
電子部品。 - 前記部品は、半導体チップまたはフレキシブル基板もしくはリジット基板である
請求項5記載の電子部品。 - 前記部品は、前記第2電極がペリフェラル配置された半導体チップであり、
前記ダミー電極がペリフェラル配置された前記第2電極よりも外側と内側の少なくとも一方に形成されている
請求項5記載の電子部品。 - 第1電極群と、前記第1電極群の外周に配置された第1のダミー電極列と、前記第1のダミー電極列の外周で前記第1のダミー電極列のピッチ間に位置する第2のダミー電極列とを有する基板と、
第2電極を有する部品と、
前記第1電極と前記第2電極との間に位置する導電性粒子を含む接合樹脂とからなる電子部品であり、
前記第1電極と前記第2電極を含む接合領域以外で、かつ、前記接合樹脂の内に、前記第1のダミー電極と、前記第2のダミー電極が配置された
電子部品。 - 前記部品は、半導体チップまたはフレキシブル基板もしくはリジット基板である
請求項8記載の電子部品。 - 前記部品は、前記第2電極がペリフェラル配置された半導体チップであり、前記ダミー電極がペリフェラル配置された前記第2電極よりも外側と内側の少なくとも一方に形成されている
請求項8記載の電子部品。 - 第1電極を有する基板と、
第2電極と前記第2電極に接続され前記第2電極のエリアから引き出された配線の途中上に位置するダミー電極とを有する部品と、前記第1電極と前記第2電極との間に位置する導電性粒子を含む接合樹脂と、からなる電子部品であり、
前記第1電極と前記第2電極を含む接合領域以外で、かつ、前記接合樹脂の内に、前記ダミー電極が配置されている
電子部品。 - 前記部品は、半導体チップまたはフレキシブル基板もしくはリジット基板である
請求項11記載の電子部品。 - 前記部品は、前記第2電極がペリフェラル配置された半導体チップであり、
前記ダミー電極がペリフェラル配置された前記第2電極よりも外側と内側の少なくとも一方に形成されている
請求項11記載の電子部品。 - 第1電極を有する基板と、
第2電極群と前記第2電極群の外周に配置された第1のダミー電極列と前記第1のダミー電極列の外周で前記第1のダミー電極列のピッチ間に位置する第2のダミー電極列とを有する部品と、
前記第1電極と前記第2電極との間に位置する導電性粒子を含む接合樹脂と、からなる電子部品であり、
前記第1電極と前記第2電極を含む接合領域以外で、かつ、前記接合樹脂の内に、前記第1のダミー電極と、前記第2のダミー電極とが形成されている
電子部品。 - 前記部品は、半導体チップまたはフレキシブル基板もしくはリジット基板である
請求項14記載の電子部品。 - 前記部品は、前記第2電極がペリフェラル配置された半導体チップであり、
前記ダミー電極がペリフェラル配置された前記第2電極よりも外側と内側の少なくとも一方に形成されている
請求項14記載の電子部品。
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JP2009071065A JP5264585B2 (ja) | 2009-03-24 | 2009-03-24 | 電子部品接合方法および電子部品 |
US12/728,555 US8304338B2 (en) | 2009-03-24 | 2010-03-22 | Method of joining electronic component and the electronic component |
CN201010157060.6A CN101848605B (zh) | 2009-03-24 | 2010-03-23 | 电子元器件接合方法及电子元器件 |
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JP2009071065A JP5264585B2 (ja) | 2009-03-24 | 2009-03-24 | 電子部品接合方法および電子部品 |
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JP2010225822A JP2010225822A (ja) | 2010-10-07 |
JP2010225822A5 JP2010225822A5 (ja) | 2012-04-26 |
JP5264585B2 true JP5264585B2 (ja) | 2013-08-14 |
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JP (1) | JP5264585B2 (ja) |
CN (1) | CN101848605B (ja) |
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US8138426B2 (en) * | 2007-11-05 | 2012-03-20 | Panasonic Corporation | Mounting structure |
KR101711499B1 (ko) * | 2010-10-20 | 2017-03-13 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
DE102012217603A1 (de) | 2012-09-27 | 2014-03-27 | Siemens Aktiengesellschaft | Anordnung zur Nukleinsäure-Sequenzierung mittels Tunnelstromanalyse |
DE102013214341A1 (de) * | 2013-07-23 | 2015-01-29 | Siemens Aktiengesellschaft | Verfahren zum Herstellen einer Nanopore zum Sequenzieren eines Biopolymers |
JP6344919B2 (ja) * | 2014-01-21 | 2018-06-20 | キヤノン株式会社 | プリント回路板及び積層型半導体装置 |
JP6588214B2 (ja) * | 2015-03-19 | 2019-10-09 | 新光電気工業株式会社 | 電子部品装置と電子部品装置の製造方法 |
JP2018056234A (ja) * | 2016-09-27 | 2018-04-05 | キヤノン株式会社 | プリント回路板、電子機器及びプリント回路板の製造方法 |
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US5400950A (en) * | 1994-02-22 | 1995-03-28 | Delco Electronics Corporation | Method for controlling solder bump height for flip chip integrated circuit devices |
JP2002314002A (ja) * | 2001-04-18 | 2002-10-25 | Mitsubishi Electric Corp | 半導体装置 |
JP2004104102A (ja) * | 2002-08-21 | 2004-04-02 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2004158733A (ja) | 2002-11-08 | 2004-06-03 | Renesas Technology Corp | 半導体装置およびその製造方法 |
TWM243783U (en) * | 2003-06-30 | 2004-09-11 | Innolux Display Corp | Structure of chip on glass |
JP2005310837A (ja) * | 2004-04-16 | 2005-11-04 | Elpida Memory Inc | 半導体装置及びその製造方法 |
US7301229B2 (en) * | 2004-06-25 | 2007-11-27 | Taiwan Semiconductor Manufacturing Company | Electrostatic discharge (ESD) protection for integrated circuit packages |
JP4477966B2 (ja) * | 2004-08-03 | 2010-06-09 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP2006245189A (ja) * | 2005-03-02 | 2006-09-14 | Matsushita Electric Ind Co Ltd | 半導体素子のフリップチップ実装方法及び実装構造体 |
WO2006103918A1 (ja) * | 2005-03-28 | 2006-10-05 | Matsushita Electric Industrial Co., Ltd. | フリップチップ実装体とフリップチップ実装方法及びフリップチップ実装装置 |
US20070069378A1 (en) * | 2005-04-15 | 2007-03-29 | Chang-Yong Park | Semiconductor module and method of forming a semiconductor module |
US20090085227A1 (en) * | 2005-05-17 | 2009-04-02 | Matsushita Electric Industrial Co., Ltd. | Flip-chip mounting body and flip-chip mounting method |
JP4887997B2 (ja) | 2006-09-19 | 2012-02-29 | 日本電気株式会社 | 電子部品の実装方法 |
JP2008101980A (ja) * | 2006-10-18 | 2008-05-01 | Denso Corp | 容量式半導体センサ装置 |
JP2008226946A (ja) * | 2007-03-09 | 2008-09-25 | Nec Corp | 半導体装置およびその製造方法 |
KR100924552B1 (ko) * | 2007-11-30 | 2009-11-02 | 주식회사 하이닉스반도체 | 반도체 패키지용 기판 및 이를 갖는 반도체 패키지 |
US8525333B2 (en) * | 2008-03-17 | 2013-09-03 | Renesas Electronics Corporation | Electronic device and manufacturing method therefor |
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US8304338B2 (en) | 2012-11-06 |
CN101848605B (zh) | 2014-06-25 |
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