CN1949498A - 无空隙电路板和具有该电路板的半导体封装 - Google Patents
无空隙电路板和具有该电路板的半导体封装 Download PDFInfo
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Abstract
本发明提供了一种无空隙电路板和具有该无空隙电路板的半导体封装,该无空隙电路板包括:保护层,覆盖和保护形成在基底上表面上的电极图案。保护层涂覆在设置在电极图案上的焊料球的周围除了紧靠焊料球的附近之外,从而形成开口。该无空隙电路板还包括至少一个间隙补偿部分,间隙补偿部分包括突起,突起在电极图案之前与向开口注入的底部填充材料接触。突起的厚度与暴露在开口中的电极图案的部分的厚度相同。这防止了在底部填充材料的注入期间由于不均匀的毛细管作用而导致的其中捕获有空气的空隙。
Description
本申请要求于2005年10月10日在韩国知识产权局提交的第2005-95027号韩国专利申请的利益,其公开通过引用包含于此。
技术领域
本发明涉及一种无空隙(void-free)电路板和具有该无空隙电路板的半导体封装。更具体地讲,本发明涉及一种无空隙电路板及具有该无空隙电路板的封装,该无空隙电路板能够防止在将底部填充(underfill)材料注入到间隙的过程中由于半导体芯片和基底之间形成的不均匀间隙造成中的不均匀的毛细管作用(capillary action)而导致的其中捕获有空气的空隙,从而防止生产不合格产品,并提高了产品的可靠性。
背景技术
紧凑小型化的电子装置的最新趋势为在半导体封装技术中所需的高速、高端和高密度安装方法。响应于这种需求,已经开发了芯片规格封装中的倒装芯片安装技术。
公知的倒装芯片安装技术包括将未封装的半导体芯片安装在电路板上,从而组装成半导体芯片封装的技术。
图1是示出了传统半导体封装的剖视图。如图所示,电极图案3被形成为电路板2的上表面上的信号线,阻焊保护层4以预定的厚度形成在电路板2的上方。
保护层4不形成在紧靠电极图案3的连接端3a(见图2)的附近,从而形成开口6,开口6暴露电极图案3的连接端3a和连接端3a周围的电路板2的上表面。
焊料球(solder ball)7在与形成在半导体芯片1的底面上的电极端(未示出)对应的位置被放置在电极图案3的连接端3a上。半导体芯片1通过焊料球与电路板2电连接。
由于附于半导体芯片1的底面的焊料球的高度,使得如上所述的将半导体芯片1安装在电路板2上的过程中在半导体芯片1和电路板2之间形成间隙。结果,支撑半导体芯片1的力量减弱,由于振动产生的应力,导致与焊料球7接触的部分会被损坏。
因此,由绝缘树脂制成的底部填充材料通过配料器(dispenser)(未示出)被注入到半导体芯片1和电路板2之间,并被固化以形成支撑半导体芯片1的底部填充部分8,从而完成倒装芯片封装10。
然而,如图2A中所示,由于以与电极图案3相对或不同的方向来注入底部填充材料以形成底部填充部分8,所以半导体芯片1和电路板2之间的间隙不均匀,这导致了空隙,在空隙中空气填充开口6,如图2B中所示。
即,在开口6中半导体芯片1和电路板2之间的间隙T1大于在开口6中暴露的电极图案3与半导体芯片1之间的间隙T2,因此,在底部填充材料的注入过程中,在间隙T1中毛细管作用较少生效。结果,底部填充材料移动通过间隙T1的流速相对小于底部填充材料移动通过较窄间隙T2的流速。
在这种情况下,如图2A中所示,在方向B上被注入在半导体芯片1和电路板2之间的底部填充材料沿着以虚线描绘的方向C流动,从而填补开口6与半导体芯片1之间的空间,其中,底部填充材料在间隙T1中的流速比间隙T2中的流速慢。结果,到达焊料球7外表面的底部填充材料捕获空气,从而形成空隙V。
在可靠性测试、质量测试或制造过程中,在至少200摄氏度的高温下对底部填充部分8加热的过程中,形成在底部填充部分8中的间隙V膨胀并爆炸,从而降低了产品的可靠性,其中,间隙V的膨胀和爆炸是生产出不合格产品的主要因素。
发明内容
本发明致力于解决现有技术的上述问题,因此,本发明的特定实施例的目的在于提供一种无空隙电路板,其能够防止在将底部填充材料注入在半导体芯片和基底之间的过程中由于不均匀的毛细管作用而导致的其中捕获有空气的空隙的形成。
本发明特定实施例的另一目的在于提供一种半导体封装,其防止在将底部填充材料注入在半导体芯片和基底之间的过程中由于不均匀的毛细管作用而导致的其中捕获有空气的空隙的形成,从而防止生产出不合格产品,并提高了产品的可靠性。
根据用于实现该目的的本发明的一方面,提供了一种无空隙电路板,该无空隙电路板包括:保护层,覆盖和保护形成在基底上表面上的电极图案,其中,保护层被涂覆在设置在电极图案上的焊料球的周围,除了紧靠焊料球的附近外,从而形成开口;至少一个间隙补偿部分,包括突起,该突起在电极图案之前与向开口注入的底部填充材料接触,该突起的厚度与暴露在开口中的电极图案的部分的厚度基本相同。
优选地,间隙补偿部分的宽度与暴露在开口中的电极图案的部分的宽度基本相同。
优选地,间隙补偿部分以焊料球为基准从电极图案转向至少90度。
优选地,间隙补偿部分的突起从电极图案延伸。
优选地,间隙补偿部分的突起由与电极图案的材料相同的材料制成,并在电极图案的制造过程中形成。
优选地,间隙补偿部分的突起的前端与保护层的内边接触。
优选地,间隙补偿部分的突起从保护层向焊料球延伸。
优选地,间隙补偿部分的突起由与保护层的材料相同的材料制成,并在保护层被涂覆时形成。
优选地,间隙补偿部分的突起的前端向焊料球的外表面的附近延伸。
优选地,间隙补偿部分的突起被单独地设置,既没有与电极图案接触的一端也没有与保护层接触的另一端。
优选地,间隙补偿部分的突起由与电极图案的材料相同的材料制成,并在电极图案的制造过程中形成。
优选地,间隙补偿部分的突起由与保护层的材料相同的材料制成,并在保护层被涂覆时形成。
根据用于实现该目的的本发明的另一发明,提供了一种倒装芯片半导体封装,其包括:至少一个半导体芯片;基底,具有通过焊料球安装在其上的半导体芯片,电极图案形成在基底上,保护层被涂覆在设置在电极图案上的焊料球周围,除了紧靠焊料球的附近外,从而形成开口;底部填充部分,由通过间隙注入的底部填充材料形成,间隙形成在半导体芯片和基底之间;至少一个间隙补偿部分,包括突起,突起在电极图案之前与向开口注入的底部填充材料接触,突起的厚度与暴露在开口中的电极图案的部分的厚度相同。
优选地,间隙补偿部分的宽度与暴露在开口中的电极图案的部分的宽度相同。
优选地,间隙补偿部分的厚度与暴露在开口中的电极图案的部分的厚度相同。
优选地,间隙补偿部分以焊料球为基准从电极图案转向至少90度。
优选地,间隙补偿部分的突起从位于基底上的电极图案延伸。
优选地,间隙补偿部分的突起由与电极图案的材料相同的材料制成,并在电极图案的制造过程中形成。
优选地,间隙补偿部分的突起的前端与保护层的内边接触。
优选地,间隙补偿部分的突起从保护层向焊料球延伸。
优选地,间隙补偿部分的突起由与保护层的材料相同的材料制成,并在保护层被涂覆时形成。
优选地,间隙补偿部分的突起的前端向焊料球的外表面的附近延伸。
优选地,间隙补偿部分的突起被单独地设置在基底上,既不具有与电极图案接触的一端也不具有与保护层接触的另一端。
优选地,间隙补偿部分的突起由与电极图案的材料相同的材料制成,并在电极图案的制造过程中形成。
优选地,间隙补偿部分的突起由与保护层的材料相同的材料制成,并在保护层被涂覆时形成。
优选地,间隙补偿部分的突起从半导体的下表面向着基底向下突起。
附图说明
从下面结合附图的详细描述中,本发明的以上和其它目的、特征和其它优点将变得更容易理解,在附图中:
图1是示出了传统的倒装芯片半导体封装的局部剖视图;
图2A是示出了图1中示出的传统半导体封装的主要部分的局部平面图;
图2B是沿着图2A中的Y-Y′截取的局部剖视图;
图3是示出了根据本发明第一实施例的倒装芯片半导体封装的局部剖视图;
图4A和图4B示出了根据本发明第一实施例的倒装芯片半导体封装,其中图4A是主要部分的平面图,图4B是沿着图4A中的线Y1-Y1′截取的局部剖视图;
图5A和图5B示出了根据本发明第二实施例的倒装芯片半导体封装,其中,图5A是主要部分的平面图,图5B是沿着图5A中的线Y2-Y2′截取的局部剖视图;
图6A和图6B示出了根据本发明第三实施例的倒装芯片半导体封装,其中,图6A是主要部分的平面图,图6B是沿着图6A中的线Y3-Y3′截取的局部剖视图;
图7是示出了根据本发明第四实施例的倒装芯片半导体封装的局部剖视图。
具体实施方式
现在将参照附图来详细描述本发明的优选实施例。
图3是示出了根据本发明第一实施例的倒装芯片半导体封装的剖视图,图4A是示出了其主要部分的局部平面图,图4B是示出了其主要部分的局部剖视图。
如图3、图4A和图4B中所示,倒装芯片半导体封装100包括半导体芯片110、基底120、底部填充部分130和间隙补偿部分140。
半导体芯片110由通过焊料球125倒装芯片地结合到基底120上表面上的至少一种有源芯片组件组成。
根据在基底120上表面上预先设计的图案,基底120具有用导电材料比如Cu或Ni印刷或层压的电极图案122。
对应于形成在半导体芯片110底面上的电极端(未示出),电极图案122在其端部具有连接端122a。
阻焊保护层124被以预定的厚度涂覆在形成在基底120上表面上的电极图案122上,以在电镀或焊接过程中保护电极图案122和基底120。
保护层124没有涂覆在电极图案122的连接端122a的附近以形成开口126,从而暴露连接端122a和围绕连接端122a的基底120上表面的部分。
在这里,优选地,阻焊保护层124由绝缘材料比如环氧树脂(epoxy)制成,以在电镀或焊接过程中用作掩模或绝缘层。
在图中,开口126被示出为环绕焊料球128的环形,但这不限制本发明,并且根据基底120的设计条件可进行各种更改。
此外,在基底120上靠近半导体芯片110可安装无源元件(未示出)比如电容器、电感器和电阻器。
为了防止由于基底120和半导体芯片110之间的间隙导致的支撑半导体芯片110的力量减弱,并加强与焊料球128接触的部分,利用配料器(未示出)通过间隙注入由绝缘树脂制成的液态底部填充材料,从而通过毛细管作用来填充间隙。底部填充材料被固化,从而形成底部填充部分130,以支撑半导体芯片110。
同时,在开口126中设置至少一个间隙补偿部分140,以防止在注入底部填充材料期间由于半导体芯片110和基底120之间的不均匀间隙造成的不均匀毛细管作用导致的空隙的形成,其中,开口126暴露基底120上表面的部分和电极图案122的部分。
设置这种间隙补偿部分140以基本上使间隙T2和间隙T3相等,其中,间隙T2在半导体芯片110和电极图案122之间,间隙T3在半导体芯片110和开口126的部分之间,当底部填充材料注入到半导体芯片110和基底120之间时,所述间隙补偿部分140的部分在电极图案122之前与底部填充材料接触。
为了达到上述目的,在开口126中的间隙补偿部分140的部分的厚度与电极图案122的在开口126中暴露的部分的厚度相同。
采用上述的结构,相对于底部填充材料的注入方向B,半导体芯片110和基底120之间的间隙变得大致均匀。因此,通过毛细管作用注入的底部填充材料的毛细管作用均匀地发生在间隙补偿部分140和保护层124,从而使得底部填充材料的流速均匀。
优选地,间隙补偿部分140以焊料球128为基准从电极图案122转向至少90度。
如图4A和4B中所示,间隙补偿部分140可具有突起141,突起141在基底120上从电极图案122连续地延伸。
在这里,突起141由与电极图案122的材料相同的材料制成,并在电极图案122的制造过程中同时地形成。
突起141可在与底部填充材料的注入方向对应的方向上从电极图案122线性延伸,但这不限制本发明。可选择地,突起141可以从电极图案122延伸,而相对于底部填充材料的注入方向偏斜。
此外,优选地,突起141的前端与保护层124的内边接触,以有助于底部填充材料通过突起141流向焊料球128,其中,所述保护层的内边形成与开口126的边界。
图5A是根据本发明第二实施例的倒装芯片半导体封装的主要部分的局部平面图,图5B是其局部剖视图。
如图5A和5B中所示,在开口126中的间隙补偿部分140可具有突起142,突起142以预定长度在基底120上从保护层124的内边延伸至焊料球128,其中,所述保护层124的内边形成与开口126的边界。
突起142由与保护层124的材料相同的材料制成,并当保护层124被涂覆时可以被一体地形成。优选地,突起142的前端延伸至焊料球128外表面的附近,以有助于底部填充材料通过突起142流向焊料球128。
图6A是示出了根据本发明第三实施例的倒装芯片半导体封装的主要部分的局部平面图,图6B是其局部剖视图。
如图6A和图6B中所示,在开口126中的间隙补偿部分140具有突起143,突起143被单独设置在基底120上,而既没有与电极图案122接触的一端又没有与保护层124接触的另一端。
在这里,突起143可以在形成电极图案122的过程中由与电极图案122的材料相同的材料制成,或者,可选择地,突起143可以在形成保护层124的过程中由与保护层124的材料相同的材料制成。
此外,在半导体芯片110和基底120上可形成树脂密封剂(未示出)比如环氧树脂密封剂,以保护它们不受外部环境的影响。
图7是示出了根据本发明第四实施例的倒装芯片半导体封装的主要部分的局部剖视图。
如图7中所示,在开口126中的间隙补偿部分140可具有突起144,突起144从半导体芯片110的底面向着基底120向下突出,而既没有与电极图案122接触的一端又没有与保护层124接触的另一端。
在这种情况下,优选地,突起144向下突出的尺寸使得间隙T3与间隙T2基本上相等,其中,间隙T3在突起144与基底120之间,间隙T2在电极图案122与半导体芯片110之间。
在具有上述结构的半导体封装100中,以预定的厚度将阻焊保护层124涂覆在基底120上,以在电镀或焊接过程中保护被图案印刷在基底120上表面上的电极图案和基底120。通过开口126暴露其上将被放置焊料球128的电极图案122的连接端的附近,其中,开口126没有被涂覆保护层124。
因此,焊料球128放置在电极图案122的端部122a上,半导体芯片110通过焊料球128与基底120电连接。
然后,通过配料器,液态底部填充材料被注入在半导体芯片110和基底120之间,并被固化从而形成底部填充部分130,以加大支撑半导体芯片110的力量并加强与焊料球128接触的部分。
如图4A和4B中所示,间隙补偿部分140具有突起141,突起141从电极图案122延伸,从而在将底部填充材料注入在半导体芯片110和基底120之间的过程中,关于底部填充材料的注入方向B,突起141首先与底部填充材料接触。因此,突起141和半导体芯片110之间的间隙T3变得与电极图案122和半导体芯片110之间的间隙T2基本上相同。
这里,间隙补偿部分140可具有从电极图案122延伸的突起141,但这不限制本发明。可选择地,如图5A和5B中所示,间隙补偿部分140可具有从保护层124延伸的突起,或者如图6A和6B中所示,间隙补偿部分140可具有一端与电极图案122分隔且另一端与保护层124分隔的突起143。此外,如图7中所示,间隙补偿部分140可具有从半导体芯片110的底面向下突出的突起144。
采用上述的结构,底部填充材料通过间隙补偿部分140流向焊料球128的流速,变得与通过保护层124流向开口126附近的流速基本上相同。
因此,底部填充材料到达焊料球128的外表面,从而填补开口126,而不形成通过捕获空气形成的空隙V,从而有助于注入底部填充材料以填补半导体芯片110和基底120之间的空间的过程。
根据以上提出的本发明,在开口中设置间隙补偿部分,以使半导体芯片和突起的首先与底部填充材料接触的部分之间的间隙,与半导体芯片和电极图案之间的间隙相等。因此,以与通过保护层流向开口附近的流速相同的流速,注入的底部填充材料通过间隙补偿部分流向焊料球,从而填补开口,而不形成其中捕获有空气的空隙。结果,防止生产不合格产品,并提高产品可靠性。
虽然已经结合优选实施例示出和描述了本发明,但是,对于本领域的技术人员,在不脱离由权利要求限定的本发明的精神和范围的情况下可以进行更改和变化将是清楚的。
Claims (26)
1、一种无空隙电路板,包括:
保护层,覆盖和保护形成在基底上表面上的电极图案,其中,所述保护层被涂覆在设置在所述电极图案上的焊料球周围,除了紧靠所述焊料球的附近之外,从而形成开口;
至少一个间隙补偿部分,包括突起,所述突起在所述电极图案之前与向所述开口注入的底部填充材料接触,所述突起的厚度与暴露在所述开口中的电极图案的部分的厚度基本相同。
2、如权利要求1所述的无空隙电路板,其中,所述间隙补偿部分的宽度与暴露在所述开口中的电极图案的部分的宽度基本相同。
3、根据权利要求1所述的无空隙电路板,其中,所述间隙补偿部分以所述焊料球为基准从所述电极图案转向至少90度。
4、根据权利要求1所述的无空隙电路板,其中,所述间隙补偿部分的所述突起从所述电极图案延伸。
5、根据权利要求4所述的无空隙电路板,其中,所述突起由与所述电极图案的材料相同的材料制成,并在所述电极图案的制造过程中形成。
6、根据权利要求4所述的无空隙电路板,其中,所述突起的前端与所述保护层的内边接触。
7、根据权利要求1所述的无空隙电路板,其中,所述间隙补偿部分的所述突起从所述保护层向所述焊料球延伸。
8、根据权利要求7所述的无空隙电路板,其中,所述突起由与所述保护层的材料相同的材料制成,并在所述保护层被涂覆时形成。
9、根据权利要求7所述的无空隙电路板,其中,所述突起的前端向所述焊料球的外表面的附近延伸。
10、根据权利要求1所述的无空隙电路板,其中,所述间隙补偿部分的所述突起被单独地设置,而不具有与所述电极图案接触的一端或者与所述保护层接触的另一端。
11、根据权利要求10所述的无空隙电路板,其中,所述突起由与所述电极图案的材料相同的材料制成,并在所述电极的制造过程中形成。
12、根据权利要求10所述的无空隙电路板,其中,所述突起由与所述保护层的材料相同的材料制成,并在所述保护层被涂覆时形成。
13、一种倒装芯片半导体封装,包括:
至少一个半导体芯片;
基底,具有通过焊料球安装在其上的所述半导体芯片,电极图案形成在所述基底上,保护层被涂覆在设置在所述电极图案上的所述焊料球周围,除了紧靠所述焊料球的附近外,从而形成开口;
底部填充部分,由通过间隙注入的底部填充材料形成,所述间隙形成在所述半导体芯片和所述基底之间;
至少一个间隙补偿部分,包括突起,所述突起在所述电极图案之前与向所述开口注入的底部填充材料接触,所述突起的厚度与暴露在所述开口中的电极图案的部分的厚度基本相同。
14、根据权利要求13所述的倒装芯片半导体封装,其中,所述间隙补偿部分的宽度与暴露在所述开口中的电极图案的部分的宽度基本相同。
15、根据权利要求13所述的倒装芯片半导体封装,其中,所述间隙补偿部分的厚度与暴露在所述开口中的电极图案的厚度基本相同。
16、根据权利要求13所述的倒装芯片半导体封装,其中,所述间隙补偿部分以所述焊料球为基准从所述电极图案转向至少90度。
17、根据权利要求13所述的倒装芯片半导体封装,其中,所述间隙补偿部分的所述突起从位于所述基底上的所述电极图案延伸。
18、根据权利要求17所述的倒装芯片半导体封装,其中,所述突起由与所述电极图案的材料基本相同的材料制成,并在所述电极图案的制造过程中形成。
19、根据权利要求17所述的倒装芯片半导体封装,其中,所述突起的前端与所述保护层的内边接触。
20、根据权利要求13所述的倒装芯片半导体封装,其中,所述间隙补偿部分的所述突起从所述保护层向所述焊料球延伸。
21、根据权利要求20所述的倒装芯片半导体封装,其中,所述突起由与所述保护层的材料相同的材料制成,并在所述保护层被涂覆时形成。
22、根据权利要求20所述的倒装芯片半导体封装,其中,所述突起的前端向所述焊料球外表面的附近延伸。
23、根据权利要求13所述的倒装芯片半导体封装,其中,所述间隙补偿部分的所述突起被单独地设置在所述基底上,既不具有与所述电极图案接触的一端也不具有与所述保护层接触的另一端。
24、根据权利要求23所述的倒装芯片半导体封装,其中,所述突起由与所述电极图案的材料相同的材料制成,并在所述电极图案的制造过程中形成。
25、根据权利要求23所述的倒装芯片半导体封装,其中,所述突起由与所述保护层的材料相同的材料制成,并在所述保护层被涂覆时形成。
26、根据权利要求13所述的倒装芯片半导体封装,其中,所述间隙补偿部分的突起从所述半导体芯片的下表面向着所述基底向下突起。
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KR1020050095027 | 2005-10-10 | ||
KR1020050095027A KR100649709B1 (ko) | 2005-10-10 | 2005-10-10 | 보이드 방지형 회로기판과 이를 갖는 반도체 패키지 |
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US (1) | US7400048B2 (zh) |
JP (1) | JP2007110081A (zh) |
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TW (2) | TWI323501B (zh) |
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CN112640593A (zh) * | 2018-08-31 | 2021-04-09 | 西门子股份公司 | 具有用于电子构件的安装位置的电路载体、电子电路和制造方法 |
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CN104812165A (zh) * | 2015-05-08 | 2015-07-29 | 林梓梁 | 一种嵌入式电路板贴片结构及其生产方法 |
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CN112640593A (zh) * | 2018-08-31 | 2021-04-09 | 西门子股份公司 | 具有用于电子构件的安装位置的电路载体、电子电路和制造方法 |
CN112640593B (zh) * | 2018-08-31 | 2024-08-23 | 西门子股份公司 | 具有用于电子构件的安装位置的电路载体、电子电路和制造方法 |
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TWI323501B (en) | 2010-04-11 |
TW200719444A (en) | 2007-05-16 |
TWI314771B (en) | 2009-09-11 |
US7400048B2 (en) | 2008-07-15 |
US20070096337A1 (en) | 2007-05-03 |
TW200941649A (en) | 2009-10-01 |
KR100649709B1 (ko) | 2006-11-27 |
CN100444373C (zh) | 2008-12-17 |
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