TWI453831B - 半導體封裝結構及其製造方法 - Google Patents

半導體封裝結構及其製造方法 Download PDF

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Publication number
TWI453831B
TWI453831B TW099130417A TW99130417A TWI453831B TW I453831 B TWI453831 B TW I453831B TW 099130417 A TW099130417 A TW 099130417A TW 99130417 A TW99130417 A TW 99130417A TW I453831 B TWI453831 B TW I453831B
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Taiwan
Prior art keywords
pin
guiding
connecting section
guiding area
leg
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TW099130417A
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English (en)
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TW201212128A (en
Inventor
郭芳村
毛森
王景弘
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台灣捷康綜合有限公司
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Application filed by 台灣捷康綜合有限公司 filed Critical 台灣捷康綜合有限公司
Priority to TW099130417A priority Critical patent/TWI453831B/zh
Priority to US13/229,667 priority patent/US8822273B2/en
Publication of TW201212128A publication Critical patent/TW201212128A/zh
Priority to US14/341,772 priority patent/US9184152B2/en
Priority to US14/474,420 priority patent/US9595503B2/en
Application granted granted Critical
Publication of TWI453831B publication Critical patent/TWI453831B/zh
Priority to US15/457,790 priority patent/US10229893B2/en

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Description

半導體封裝結構及其製造方法
本發明係關於一種半導體封裝結構及其製造方法，詳言之，係關於一種不需要導線之電晶體之半導體封裝結構及其製造方法。
參考圖1至圖3，顯示習知半導體封裝結構之製造方法之示意圖。參考圖1，提供一導線架1，該導線架1包含至少一基板11、至少一汲極腳位12、至少一源極腳位13及至少一閘極腳位14。其中該汲極腳位12係與該基板11相連接。該源極腳位13及該閘極腳位14係面對該基板11之側邊，且該源極腳位13及該閘極腳位14與該基板11之側邊間具有一間距。
參考圖2，提供至少一晶片2，該晶片2具有一上表面21及一下表面(圖中未示)。該上表面21具有一源極導接區22及一閘極導接區23。該下表面具有一汲極導接區(圖中未示)。接著，將該晶片2置於該導線架1之基板11上，且該汲極導接區係電性連接該基板11。
參考圖3，進行打線製程，利用第一導線31導接該導線架1之源極腳位13與該晶片2之源極導接區22，且利用第二導線32導接該導線架1之閘極腳位14與該晶片2之閘極導接區23。
接著，再進行灌模製程及切割製程，以形成一半導體封裝結構。
該習知半導體封裝結構之製造方法之缺點如下。由於該等第一導線31及第二導線32係為金線，其材料成本昂貴。再者，在打線時，係利用打線機逐一形成該等第一導線31及第二導線32，因此十分耗時。此外，該等第一導線31及第二導線32間必需保留一定的間距以供打線機之打線頭移動，因此該等第一導線31及第二導線32間之間距無法有效地縮小，如果該晶片2縮小至一定程度時，上述習知之製造方法便無法適用。
因此，有必要提供一種創新且具進步性的半導體封裝結構及其製造方法，以解決上述問題。
本發明提供一種半導體封裝結構之製造方法，其包括以下步驟：(a)提供一導線架，該導線架包含至少一基板、至少一第一腳位、至少一第二腳位及至少一第三腳位，其中該第一腳位係與該基板相連接，該第二腳位及該第三腳位係面對該基板之側邊，該第二腳位具有一第一延伸部，該第三腳位具有一第二延伸部；(b)提供至少一晶片，該至少一晶片具有一上表面及一下表面，該上表面具有一第二導接區及一第三導接區，該下表面具有一第一導接區；(c)將該至少一晶片置於該導線架之該至少一基板上，且該第一導接區係電性連接該至少一基板；(d)提供一夾銲片，該夾銲片具有至少一第二連接區段、至少一第三連接區段及至少一中介連接區段，該至少一中介連接區段係連接該至少一第二連接區段及該至少一第三連接區段；(e)將該夾銲片置於該至少一晶片上，且該第二連接區段分別電性連接該至少一晶片之第二導接區及該第二腳位之第一延伸部，該第三連接區段分別電性連接該至少一晶片之第三導接區及該第三腳位之第二延伸部，其中該第二腳位之第一延伸部與該至少一晶片之第二導接區均與該中介連接區段相連接，且該第三腳位之第二延伸部與該至少一晶片之第三導接區均與該中介連接區段相連接；(f)進行灌模製程；及(g)進行切割製程，以去除該中介連接區段，使該第二腳位及該第三腳位絕緣，以形成至少一半導體封裝結構。
藉此，本發明不需使用金線，可有效節省成本。此外，該夾銲片係一整片置放，可有效節省時間，而且該夾銲片可利用蝕刻或其他精密技術製作，以縮小該第二連接區段及該第三連接區段間之間距，而可應用於小尺寸之晶片。
本發明另提供一種半導體封裝結構，其包括一導線架、至少一晶片、一夾銲片及一封膠材料。該導線架包含至少一基板、至少一第一腳位、至少一第二腳位及至少一第三腳位，其中該第一腳位係與該基板相連接，該第二腳位及該第三腳位係面對該基板之側邊，該第二腳位具有一第一延伸部，該第三腳位具有一第二延伸部。每一晶片係位於每一基板上，每一晶片具有一上表面及一下表面，該上表面具有一第二導接區及一第三導接區，該下表面具有一第一導接區，且該第一導接區係電性連接該基板。該夾銲片係位於該至少一晶片上，該夾銲片具有至少一第二連接區段及至少一第三連接區段，該第二連接區段分別電性連接該至少一晶片之第二導接區及該第二腳位之第一延伸部，該第三連接區段分別電性連接該至少一晶片之第三導接區及該第三腳位之第二延伸部。該封膠材料包覆該導線架、該至少一晶片及該夾銲片，其中該至少一第一腳位、該至少一第二腳位、該至少一第三腳位、至少一第二連接區段及至少一第三連接區段係顯露於該封膠材料之側面。
請參考圖4至圖23，顯示本發明半導體封裝結構之製造方法之較佳實施例之各個製程步驟之示意圖。
參考圖4及圖5，其中圖5係圖4之局部放大圖。提供一導線架4，該導線架4包含至少一基板41、至少一第一腳位42、至少一第二腳位43及至少一第三腳位44。其中該等第一腳位42係與該基板41相連接，該第二腳位43及該第三腳位44係面對該基板41之側邊411，該第二腳位43及該第三腳位44與該基板41之側邊411間具有一間距。該第二腳位43具有一第一延伸部431，該第三腳位44具有一第二延伸部441。可以理解的是，該導線架4更包含複數個固定連接區段45，用以連接該至少一基板41、該至少一第一腳位42、該至少一第二腳位43及該至少一第三腳位44，以形成一框架體。在本實施例中，該第一腳位42係為一汲極腳位，該第二腳位43係為一源極腳位，且該第三腳位44係為一閘極腳位。然而，在其它應用中，該第一腳位42係為一源極腳位，該第二腳位43係為一汲極腳位，且該第三腳位44係為一閘極腳位。
參考圖6及圖7，其中圖7係圖6之局部放大圖。形成一第一銲料51於該基板41、該第二腳位43之第一延伸部431及該第三腳位44之第二延伸部441。
參考圖8及圖9，其中圖9係圖8之局部放大圖。提供至少一晶片6，在本實施例中，該晶片6係為功率金氧半場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)。該至少一晶片6具有一上表面61及一下表面64(圖23)，該上表面61具有一第二導接區62及一第三導接區63。該下表面64具有一第一導接區(圖中未示)。接著，將該至少一晶片6設置於該導線架4之該至少一基板41上，其中一基板41係承載一晶片6，且該至少一晶片6之第一導接區係利用該第一銲料51電性連接該至少一基板41。在本實施例中，該第一導接區係為一汲極導接區，該第二導接區62係為一源極導接區，且該第三導接區63係為一閘極導接區。然而，在其它應用中，該第一導接區係為一源極導接區，該第二導接區62係為一汲極導接區，且該第三導接區63係為一閘極導接區。
參考圖10及圖11，其中圖11係圖10之局部放大圖。形成一第二銲料52於該晶片6之第二導接區62及該第三導接區63。
參考圖12、圖13、圖14及圖15，其中圖13係圖12之局部放大圖，圖14係圖13中沿著線14-14之剖視圖，圖15係圖13中沿著線15-15之剖視圖。提供一夾銲片(Clip)7，該夾銲片7具有至少一第二連接區段71、至少一第三連接區段72及至少一中介連接區段73。該至少一中介連接區段73係連接該至少一第二連接區段71及該至少一第三連接區段72。在本實施例中，該第二連接區段71係為一源極連接區段，且該第三連接區段72係為一閘極連接區段。然而，在其它應用中，該第二連接區段71係為一汲極連接區段，且該第三連接區段72係為一閘極連接區段。
在本實施例中，參考圖13及圖14，每一第二連接區段71具有一第一端711、一第二端712、一第一凹處713及一第二凹處714。參考圖13及圖15，每一第三連接區段72具有一第三端721、一第四端722、一第三凹處723及一第四凹處724。該第二連接區段71之第二端712及該第三連接區段72之第四端722皆連接該中介連接區段73。較佳地，參考圖12，該夾銲片7更包括複數個外圍連接區段74及至少一吸附區域75。該等外圍連接區段74用以連接該至少一第二連接區段71、該至少一第三連接區段72及至少一吸附區域75，以形成一框架體。該至少一吸附區域75係為一較大之實體面積，用以提供吸取時所需之面積。
參考圖16、圖17及圖18，其中圖17係圖16之局部放大圖，圖18係圖17中沿著線18-18之剖視圖。將該夾銲片7設置於該至少一晶片6上，且該第二連接區段71分別電性連接該至少一晶片6之第二導接區62及該第二腳位43之第一延伸部431。該第三連接區段72分別電性連接該至少一晶片6之第三導接區63及該第三腳位44之第二延伸部441。該第二腳位43之第一延伸部431與該至少一晶片6之第二導接區62均與該中介連接區段73相連接，且該第三腳位44之第二延伸部441與該至少一晶片6之第三導接區63均與該中介連接區段73相連接。由圖可看出，較佳地，該第二腳位43之第一延伸部431係位於該至少一晶片6之第二導接區62及該中介連接區段73之間，且該第三腳位44之第二延伸部441係位於至少一晶片6之第三導接區63及該中介連接區段73之間。亦即，該中介連接區段73係位於該第二腳位43之第一延伸部431及該第三腳位44之第二延伸部441之外，且該中介連接區段73之位置係位於切割線(該第一切割線L1或該第二切割線L2)上，如圖20及圖21所示。
在本實施例中，該第二連接區段71之第一端711係利用該第一凹處713電性連接該至少一晶片6之第二導接區62，且該第二連接區段71係利用該第二凹處714電性連接該第二腳位43之第一延伸部431。同時，該第三連接區段72之第三端721係利用該第三凹處723電性連接該至少一晶片6之第三導接區63，且該第三連接區段72係利用該第四凹處724電性連接該第三腳位44之第二延伸部441。
接著，進行迴銲製程，使得該導線架4、該至少一晶片6及該夾銲片7確實連接在一起。
接著，參考圖19，進行灌模製程。將上述連接在一起之該導線架4、該至少一晶片6及該夾銲片7置入一模穴(圖中未示)中，再灌入一封膠材料8以完全包覆該導線架4、該至少一晶片6及該夾銲片7(包含該中介連接區段73)。在本實施例中，該等第一腳位42及該基板41之下表面係顯露 於該封膠材料8之外。亦即，整個該導線架4、整個該晶片6及整個該夾銲片7(包含該中介連接區段73)全部被該封膠材料8所包覆。
最後，參考圖20及圖21，沿著第一切割線L1(圖20)或第二切割線L2(圖21)進行切割製程，以去除該導線架4之固定連接區段45、該夾銲片7之中介連接區段73、該夾銲片7之外圍連接區段74及位於該第一切割線L1上之封膠材料8，使該第二腳位43及該第三腳位44絕緣，以形成至少一半導體封裝結構9，如圖23所示。由圖20及圖21可看出，該中介連接區段73之位置係位於切割線(該第一切割線L1或該第二切割線L2)上，使得該中介連接區段73與位於該切割線(該第一切割線L1或該第二切割線L2)上之封膠材料8可以同時被切除。
如果該半導體封裝結構9只要包含一個晶片6的話，則切割時需沿著該等第一切割線L1，如圖20所示。然而，如果該半導體封裝結構9要包含二個晶片6的話(圖22)，則切割時需沿著該等第二切割線L2，如圖21所示。因此，在本發明之製造方法可有較佳之彈性。再者，本發明不需使用金線，可有效節省材料成本。此外，本發明之該夾銲片7係一整片置放，可有效節省時間，而且該夾銲片7可利用蝕刻或其他精密技術製作，以縮小該第二連接區段71及該第三連接區段72間之間距，而可應用於小尺寸之晶片6。
參考圖22，顯示本發明半導體封裝結構之俯視示意圖，其中省略了封膠材料。參考圖23，顯示本發明半導體封裝 結構之剖視示意圖。該半導體封裝結構9包括一導線架4、至少一晶片6、一夾銲片7及一封膠材料8。該導線架4包含至少一基板41、至少一第一腳位42、至少一第二腳位43及至少一第三腳位44。其中該等第一腳位42係與該基板41相連接，該第二腳位43及該第三腳位44係面對該基板41之側邊411，該第二腳位43及該第三腳位44與該基板41之側邊411間具有一間距。該第二腳位43具有一第一延伸部431，該第三腳位44具有一第二延伸部441。在本實施例中，該第一腳位42係為一汲極腳位，該第二腳位43係為一源極腳位，且該第三腳位44係為一閘極腳位。然而，在其它應用中，該第一腳位42係為一源極腳位，該第二腳位43係為一汲極腳位，且該第三腳位44係為一閘極腳位。
每一晶片6係位於每一基板41上。在本實施例中，該晶片6係為功率金氧半場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)。該至少一晶片6具有一上表面61及一下表面64，該上表面61具有一第二導接區62及一第三導接區63。該下表面64具有一第一導接區(圖中未示)。該第一導接區係電性連接該基板41。在本實施例中，該第一導接區係為一汲極導接區，該第二導接區62係為一源極導接區，且該第三導接區63係為一閘極導接區。然而，在其它應用中，該第一導接區係為一源極導接區，該第二導接區62係為一汲極導接區，且該第三導接區63係為一閘極導接區。
該夾銲片7係位於該至少一晶片6上。該夾銲片7具有至 少一第二連接區段71及至少一第三連接區段72。在本實施例中，每一第二連接區段71具有一第一端711、一第二端712、一第一凹處713及一第二凹處714。每一第三連接區段72具有一第三端721、一第四端722、一第三凹處723及一第四凹處724。在本實施例中，該第二連接區段71係為一源極連接區段，且該第三連接區段72係為一閘極連接區段。然而，在其它應用中，該第二連接區段71係為一汲極連接區段，且該第三連接區段72係為一閘極連接區段。
該第二連接區段71分別電性連接該至少一晶片6之第二導接區62及該第二腳位43之第一延伸部431。該第三連接區段72分別電性連接該至少一晶片6之第三導接區63及該第三腳位44之第二延伸部441。在本實施例中，該第二連接區段71之第一端711係利用該第一凹處713電性連接該至少一晶片6之第二導接區62，且該第二連接區段71係利用該第二凹處714電性連接該第二腳位43之第一延伸部431。同時，該第三連接區段72之第三端721係利用該第三凹處723電性連接該至少一晶片6之第三導接區63，且該第三連接區段72係利用該第四凹處724電性連接該第三腳位44之第二延伸部441。
該封膠材料8包覆該導線架4、該至少一晶片6及該夾銲片7，其中該至少一第一腳位42、該至少一第二腳位43、該至少一第三腳位44、至少一第二連接區段71及至少一第三連接區段72係顯露於該封膠材料8之側面81。在本實施例中，由於上述製程所導致之結果，該第一腳位42之外露 表面、該第二腳位43之外露表面及該第三腳位44之外露表面係與該封膠材料8之側面81齊平。
較佳地，該半導體封裝結構9更包括第一銲料51及一第二銲料52。該第一銲料51係用以連接該至少一基板41及該至少一晶片6、該第二腳位43之第一延伸部431及該第二連接區段71、以及該第三腳位44之第二延伸部441及該第三連接區段72。該第二銲料52係用以連接該第二連接區段71及該至少一晶片6之第二導接區62、以及該第三連接區段72及該至少一晶片6之第三導接區63。
惟上述實施例僅為說明本發明之原理及其功效，而非用以限制本發明。因此，習於此技術之人士對上述實施例進行修改及變化仍不脫本發明之精神。本發明之權利範圍應如後述之申請專利範圍所列。
L1‧‧‧第一切割線
L2‧‧‧第二切割線
1‧‧‧導線架
2‧‧‧晶片
4‧‧‧導線架
6‧‧‧晶片
7‧‧‧夾銲片
8‧‧‧封膠材料
9‧‧‧半導體封裝結構
11‧‧‧基板
12‧‧‧汲極腳位
13‧‧‧源極腳位
14‧‧‧閘極腳位
21‧‧‧上表面
22‧‧‧第二導接區
23‧‧‧第三導接區
31‧‧‧第一導線
32‧‧‧第二導線
41‧‧‧基板
42‧‧‧第一腳位
43‧‧‧第二腳位
44‧‧‧第三腳位
45‧‧‧固定連接區段
51‧‧‧第一銲料
52‧‧‧第二銲料
61‧‧‧上表面
62‧‧‧第二導接區
63‧‧‧第三導接區
64‧‧‧下表面
71‧‧‧第二連接區段
72‧‧‧第三連接區段
73‧‧‧中介連接區段
74‧‧‧外圍連接區段
75‧‧‧吸附區域
81‧‧‧封膠材料之側面
411‧‧‧基板之側邊
431‧‧‧第一延伸部
441‧‧‧第二延伸部
711‧‧‧第一端
712‧‧‧第二端
713‧‧‧第一凹處
714‧‧‧第二凹處
721‧‧‧第三端
722‧‧‧第四端
723‧‧‧第三凹處
724‧‧‧第四凹處
圖1至圖3顯示習知半導體封裝結構之製造方法之示意圖；及圖4至圖23顯示本發明半導體封裝結構之製造方法之較佳實施例之各個製程步驟之示意圖。
4．．．導線架
6．．．晶片
7．．．夾銲片
8．．．封膠材料
9．．．半導體封裝結構
41．．．基板
42．．．第一腳位
43．．．第二腳位
51．．．第一銲料
52．．．第二銲料
61．．．上表面
64．．．下表面
71．．．第二連接區段
81．．．封膠材料之側面
411．．．基板之側邊
431．．．第一延伸部
711．．．第一端
712．．．第二端
713．．．第一凹處
714．．．第二凹處

Claims (15)

  1. 一種半導體封裝結構之製造方法，包括以下步驟：(a)提供一導線架，該導線架包含至少一基板、至少一第一腳位、至少一第二腳位及至少一第三腳位，其中該第一腳位係與該基板相連接，該第二腳位及該第三腳位係面對該基板之側邊，該第二腳位具有一第一延伸部，該第三腳位具有一第二延伸部；(b)提供至少一晶片，該至少一晶片具有一上表面及一下表面，該上表面具有一第二導接區及一第三導接區，該下表面具有一第一導接區；(c)設置該至少一晶片於該導線架之該至少一基板上，且該第一導接區係電性連接該至少一基板；(d)提供一夾銲片，該夾銲片具有至少一第二連接區段、至少一第三連接區段及至少一中介連接區段，該至少一中介連接區段係連接該至少一第二連接區段及該至少一第三連接區段；(e)設置該夾銲片於該至少一晶片上，且該第二連接區段分別電性連接該至少一晶片之第二導接區及該第二腳位之第一延伸部，該第三連接區段分別電性連接該至少一晶片之第三導接區及該第三腳位之第二延伸部，其中該第二腳位之第一延伸部與該至少一晶片之第二導接區均與該中介連接區段相連接，且該第三腳位之第二延伸部與該至少一晶片之第三導接區均與該中介連接區段相連接，該中介連接區段 之位置係位於切割線上；(f)進行灌模製程，以形成一封膠材料以完全包覆該導線架、該至少一晶片及該夾銲片，其中該中介連接區段係被該封膠材料所包覆；及(g)沿著該切割線進行切割製程，以去除該中介連接區段及部份封膠材料，使該第二腳位及該第三腳位絕緣，以形成至少一半導體封裝結構。
  2. 如請求項1之製造方法，其中該步驟(a)中，該導線架更包含複數個固定連接區段，用以連接該至少一基板、該至少一第一腳位、該至少一第二腳位及該至少一第三腳位。
  3. 如請求項1之製造方法，其中該步驟(a)中，該第二腳位及該第三腳位與該基板之側邊間具有一間距。
  4. 如請求項1之製造方法，其中該步驟(b)之後更包括一形成一第一銲料於該基板、該第二腳位之第一延伸部及該第三腳位之第二延伸部之步驟，該步驟(c)之後更包括一形成一第二銲料於該第二導接區及該第三導接區之步驟，且該步驟(e)之後更包括一進行迴銲製程之步驟。
  5. 如請求項1之製造方法，其中該步驟(d)中，該至少一第二連接區段具有一第一端及一第二端，該至少一第三連接區段具有一第三端及一第四端，該至少一第二連接區段之第二端及該至少一第三連接區段之第四端皆連接該至少一中介連接區段，且該步驟(e)中，該第二連接區段之第一端電性連接該至少一晶片之第二導接區，該第三 連接區段之第三端電性連接該至少一晶片之第三導接區。
  6. 如請求項1之製造方法，其中該步驟(d)中，該至少一第二連接區段具有一第一凹處及一第二凹處，該至少一第三連接區段具有一第三凹處及一第四凹處，該至少一第二連接區段係利用該第一凹處電性連接該至少一晶片之第二導接區，該至少一第二連接區段係利用該第二凹處電性連接該第二腳位之第一延伸部，該第三連接區段係利用該第三凹處電性連接該至少一晶片之第三導接區，該第三連接區段係利用該第四凹處電性連接該第三腳位之第二延伸部。
  7. 如請求項1之製造方法，其中該第一腳位係為一汲極腳位，該第二腳位係為一源極腳位，該第三腳位係為一閘極腳位，該第一導接區係為一汲極導接區，該第二導接區係為一源極導接區，該第三導接區係為一閘極導接區，該第二連接區段係為一源極連接區段，且該第三連接區段係為一閘極連接區段。
  8. 如請求項1之製造方法，其中該第一腳位係為一源極腳位，該第二腳位係為一汲極腳位，該第三腳位係為一閘極腳位，該第一導接區係為一源極導接區，該第二導接區係為一汲極導接區，該第三導接區係為一閘極導接區，該第二連接區段係為一汲極連接區段，且該第三連接區段係為一閘極連接區段。
  9. 一種半導體封裝結構，包括： 一導線架，包含至少一基板、至少一第一腳位、至少一第二腳位及至少一第三腳位，其中該第一腳位係與該基板相連接，該第二腳位及該第三腳位係面對該基板之側邊，該第二腳位具有一第一延伸部，該第三腳位具有一第二延伸部；至少一晶片，每一晶片係位於每一基板上，每一晶片具有一上表面及一下表面，該上表面具有一第二導接區及一第三導接區，該下表面具有一第一導接區，且該第一導接區係電性連接該基板；一夾銲片，位於該至少一晶片上，該夾銲片具有至少一第二連接區段及至少一第三連接區段，該第二連接區段分別電性連接該至少一晶片之第二導接區及該第二腳位之第一延伸部，該第三連接區段分別電性連接該至少一晶片之第三導接區及該第三腳位之第二延伸部；及一封膠材料，包覆該導線架、該至少一晶片及該夾銲片，其中該至少一第一腳位、該至少一第二腳位、該至少一第三腳位、至少一第二連接區段及至少一第三連接區段係顯露於該封膠材料之側面，其中該第一腳位之外露表面、該第二腳位之外露表面及該第三腳位之外露表面係與該封膠材料之側面齊平。
  10. 如請求項9之半導體封裝結構，其中該第二腳位及該第三腳位與該基板之側邊間具有一間距。
  11. 如請求項9之半導體封裝結構，更包括：一第一銲料，用以連接該至少一基板及該至少一晶 片、該第二腳位之第一延伸部及該第二連接區段、以及該第三腳位之第二延伸部及該第三連接區段；及一第二銲料，用以連接該第二連接區段及該至少一晶片之第二導接區、以及該第三連接區段及該至少一晶片之第三導接區。
  12. 如請求項9之半導體封裝結構，其中該至少一第二連接區段具有一第一端及一第二端，該至少一第三連接區段具有一第三端及一第四端，該第二連接區段之第一端電性連接該至少一晶片之第二導接區，該第二連接區段之第二端顯露於該封膠材料之側面，該第三連接區段之第三端電性連接該至少一晶片之第三導接區，該第三連接區段之第四端顯露於該封膠材料之側面。
  13. 如請求項9之半導體封裝結構，其中該至少一第二連接區段具有一第一凹處及一第二凹處，該至少一第三連接區段具有一第三凹處及一第四凹處，該至少一第二連接區段係利用該第一凹處電性連接該至少一晶片之第二導接區，該至少一第二連接區段係利用該第二凹處電性連接該第二腳位之第一延伸部，該第三連接區段係利用該第三凹處電性連接該至少一晶片之第三導接區，該第三連接區段係利用該第四凹處電性連接該第三腳位之第二延伸部。
  14. 如請求項9之半導體封裝結構，其中該第一腳位係為一汲極腳位，該第二腳位係為一源極腳位，該第三腳位係為一閘極腳位，該第一導接區係為一汲極導接區，該第 二導接區係為一源極導接區，該第三導接區係為一閘極導接區，該第二連接區段係為一源極連接區段，且該第三連接區段係為一閘極連接區段。
  15. 如請求項9之半導體封裝結構，其中該第一腳位係為一源極腳位，該第二腳位係為一汲極腳位，該第三腳位係為一閘極腳位，該第一導接區係為一源極導接區，該第二導接區係為一汲極導接區，該第三導接區係為一閘極導接區，該第二連接區段係為一汲極連接區段，且該第三連接區段係為一閘極連接區段。
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