JP2012015202A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2012015202A JP2012015202A JP2010148092A JP2010148092A JP2012015202A JP 2012015202 A JP2012015202 A JP 2012015202A JP 2010148092 A JP2010148092 A JP 2010148092A JP 2010148092 A JP2010148092 A JP 2010148092A JP 2012015202 A JP2012015202 A JP 2012015202A
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- lead
- island
- protrusion
- semiconductor device
- metal
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Abstract
【解決手段】 アイランドのリードと対向する辺に、リード端部と同じ高さでリード側に突出する突起部を設ける。突起部とリード端部を同時にクランパで押圧することにより、吊りピンや、アイランド周囲の押さえ領域がない場合であっても、アイランドの浮きを防止できる。
【選択図】 図1
Description
該半導体素子が固着されるアイランドと、該アイランドと離間して対向配置され、前記半導体素子と電気的に接続されて一部が外部に導出するリードと、一端が前記半導体素子の前記電極と固着し、他端が前記リードと固着する金属リボンとを備え、前記アイランドには、前記リードに対向する辺から前記リードの近傍に向かって突出する突起部を設けることにより解決するものである。
10 リードフレーム
11、11A、11B 第1リード
12、12A、12B 第2リード
13 第3リード
14 アイランド
15 突起部
16 リード突起部
20 半導体素子
21、21A、21B 金属リボン
17、17A、17B 接続部
18、18A、18B 接続部
30 金属メッキ層
31、31A、31B 金属メッキ層
32、32A、32B 金属メッキ層
33、33A、33B 金属メッキ層
50 クランパ
51 第1凸部
52 第2凸部
Claims (12)
- 主面に電極が配置された半導体素子と、
該半導体素子が固着されるアイランドと、
該アイランドと離間して対向配置され、前記半導体素子と電気的に接続されて一部が外部に導出するリードと、
一端が前記半導体素子の前記電極と固着し、他端が前記リードと固着する金属リボンとを備え、
前記アイランドには、前記リードに対向する辺から前記リードの近傍に向かって突出する突起部が設けられることを特徴とする半導体装置。 - 前記突起部は先端が、平面視において前記リードの前記アイランドに対向する辺の延長線上を超える位置に達することを特徴とする請求項1に記載の半導体装置。
- 前記突起部の主面と、前記リード部の端部の主面はそれぞれ金属メッキ層が設けられることを特徴とする請求項1または請求項2に記載の半導体装置。
- 前記リードに前記突起部方向に突出するリード突起部が設けられ、前記金属メッキ層は前記リード突起部に部分的に設けられることを特徴とする請求項3に記載の半導体装置。
- 前記突起部の近傍に、主面に金属メッキ層が設けられて金線が固着されるリードが配置されることを特徴とする請求項1から請求項4のいずれかに記載の半導体装置。
- 他の金属リボンと、該他の金属リボンが固着される他のリードと、前記他の金属リボンに対応して前記アイランドに設けられた他の突起部とを有することを特徴とする請求項1から請求項5のいずれかに記載の半導体装置。
- アイランドの主面に配置された半導体素子の電極と、前記アイランドと離間して対向するリードとを、金属リボンにて接続する工程を備えた半導体装置の製造方法であって、
前記アイランドの前記リードに対向する辺から前記リードの近傍に突出して設けられた突起部をクランパの凸部で押圧して前記金属リボンの一端を前記電極に固着し、他端を前記リードに固着することを特徴とする半導体装置の製造方法。 - 前記凸部は前記突起部と同時に前記リードの端部を押圧することを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記リードの端部は前記突起部方向に突出するリード突起部が設けられ、該リード突起部が前記凸部に押圧されることを特徴とする請求項8に記載の半導体装置の製造方法。
- 前記金属リボンは前記電極に超音波接合されることを特徴とする請求項7から請求項9のいずれかに記載の半導体装置の製造方法。
- 前記アイランド上の他の電極と、該アイランドに対向する他のリードとを他の金属リボンで接続する工程を有し、
前記アイランドの前記他のリードに対向する辺から前記他のリードの近傍に突出して設けられた他の突起部をクランパの他の凸部で押圧して前記他の金属リボンの一端を前記他の電極に固着し、他端を前記他のリードに固着することを特徴とする請求項7から請求項10のいずれかに記載の半導体装置の製造方法。 - 前記他のリードの端部は前記他の突起部方向に突出する他のリード突起部が設けられ、前記他の凸部は前記他の突起部と同時に前記他のリード突起部を押圧することを特徴とする請求項11に記載の半導体装置の製造方法。
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US9966330B2 (en) | 2013-03-14 | 2018-05-08 | Vishay-Siliconix | Stack die package |
US9589929B2 (en) | 2013-03-14 | 2017-03-07 | Vishay-Siliconix | Method for fabricating stack die package |
US9385070B2 (en) * | 2013-06-28 | 2016-07-05 | Delta Electronics, Inc. | Semiconductor component having a lateral semiconductor device and a vertical semiconductor device |
JP2015144216A (ja) * | 2014-01-31 | 2015-08-06 | 株式会社東芝 | 半導体装置及びその製造方法 |
WO2016051595A1 (ja) * | 2014-10-03 | 2016-04-07 | 三菱電機株式会社 | リードフレーム、半導体装置の製造方法 |
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