WO2016051595A1 - リードフレーム、半導体装置の製造方法 - Google Patents

リードフレーム、半導体装置の製造方法 Download PDF

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Publication number
WO2016051595A1
WO2016051595A1 PCT/JP2014/076571 JP2014076571W WO2016051595A1 WO 2016051595 A1 WO2016051595 A1 WO 2016051595A1 JP 2014076571 W JP2014076571 W JP 2014076571W WO 2016051595 A1 WO2016051595 A1 WO 2016051595A1
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WIPO (PCT)
Prior art keywords
narrow
lead terminal
wide
lead frame
end side
Prior art date
Application number
PCT/JP2014/076571
Other languages
English (en)
French (fr)
Inventor
坂本　健
武敏 鹿野
裕史 川島
Original Assignee
三菱電機株式会社
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Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2014/076571 priority Critical patent/WO2016051595A1/ja
Priority to US15/322,191 priority patent/US10541193B2/en
Priority to DE112014007018.1T priority patent/DE112014007018B4/de
Priority to KR1020177008409A priority patent/KR101979519B1/ko
Priority to JP2016551455A priority patent/JP6237919B2/ja
Priority to CN201480082449.5A priority patent/CN106796931B/zh
Publication of WO2016051595A1 publication Critical patent/WO2016051595A1/ja
Priority to US16/686,971 priority patent/US11387173B2/en

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    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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Definitions

  • the present invention relates to a lead frame and a method of manufacturing a semiconductor device provided with the lead frame.
  • Patent Document 1 discloses that, after sealing a lead frame with a resin, the unnecessary resin is plunged with a break pin and removed.
  • the tie bar width be larger.
  • the tie bar is the part to be cut before the product is completed. Therefore, in order to cut the tie bar easily, it is preferable that the tie bar width be smaller. As described above, when the width of the tie bar is reduced, it is difficult to fix the tie bar with the holding jig, and when the width of the tie bar is increased, the tie bar can not be easily cut.
  • the present invention was made to solve the above-mentioned problems, and it is easy to hold down a tie bar with a holding jig, and a lead frame easy to cut the tie bar, and a semiconductor device using the lead frame. Intended to provide a method.
  • a lead frame according to the present invention comprises a first lead terminal, a second lead terminal provided in parallel to the first lead terminal, and a tie bar connecting the first lead terminal and the second lead terminal.
  • the tie bar includes a first narrow portion in contact with the first lead terminal, a second narrow portion in contact with the second lead terminal, a width smaller than the first narrow portion and the second narrow portion.
  • a wide width portion connecting the first narrow width portion and the second narrow width portion, and a portion of the wide width portion between the first narrow width portion and the second narrow width portion A hole is formed.
  • a semiconductor element is fixed to a lead frame including a first lead terminal, a second lead terminal, and a tie bar connecting the first lead terminal and the second lead terminal.
  • a transfer molding step of providing a runner flow path along the tie bar to form a resin covering the semiconductor element, a first narrow portion in contact with the first lead terminal, and a second width in contact with the second lead terminal The wide portion of the tie bar including a narrow portion, a wide portion that is wider than the first narrow portion and the second narrow portion, and connects the first narrow portion and the second narrow portion.
  • the tie bar is provided with a large width portion and a small width portion, it is possible to easily hold the tie bar by the holding jig and cut the tie bar.
  • FIG. 1 is a plan view of a lead frame according to a first embodiment. It is a top view which shows a lead frame and a semiconductor element. It is a top view of a semiconductor device after wire connection. It is a top view of resin etc. It is a top view of a lead frame etc. in a removal process.
  • FIG. 6 is a cross-sectional view taken along a broken line VI-VI in FIG. 5;
  • FIG. 7 is a cross-sectional view taken along a broken line VII-VII in FIG. 5;
  • FIG. 2 is a cross-sectional view of a semiconductor device manufactured by the method of manufacturing a semiconductor device according to the first embodiment.
  • FIG. 10 is a partial plan view of a lead frame according to a second embodiment.
  • FIG. 18 is a plan view of a portion of a lead frame or the like according to a third embodiment.
  • FIG. 21 is a plan view of a portion of a lead frame according to a fourth embodiment; It is sectional drawing of a holding jig etc. in a removal process.
  • FIG. 21 is a plan view of a portion of a lead frame according to a fifth embodiment; It is sectional drawing of a holding jig etc. in a removal process.
  • FIG. 1 is a plan view of a lead frame 10 according to a first embodiment of the present invention.
  • the lead frame 10 is provided with an outer frame 12.
  • a first lead terminal 14, a second lead terminal 16, a third lead terminal 18, and a fourth lead terminal 20 are connected to the outer frame 12. These lead terminals are provided in parallel.
  • the outer frame 12 and the first lead terminal 14, the first lead terminal 14 and the second lead terminal 16, the second lead terminal 16 and the third lead terminal 18, and the third lead terminal 18 and the fourth lead terminal 20 are tie bars 22 respectively.
  • the tie bar 22 includes a first narrow portion 22a, a second narrow portion 22b, and a wide portion 22c.
  • the first narrow portion 22 a is in contact with the first lead terminal 14.
  • the second narrow portion 22 b is in contact with the second lead terminal 16.
  • the wide portion 22 c connects the first narrow portion 22 a and the second narrow portion 22 b.
  • the wide portion 22c is wider than the first narrow portion 22a and the second narrow portion 22b. That is, the wide portion 22c extends longer in the upward direction (y positive direction) than the first narrow width portion 22a and the second narrow width portion 22b, and extends in the lower direction (y negative direction).
  • a through hole 22d is formed in a portion between the first narrow width portion 22a and the second narrow width portion 22b in the wide width portion 22c.
  • FIG. 2 is a plan view showing the lead frame and the semiconductor element.
  • the semiconductor devices 30 and 32 are IGBT (Insulated Gate Bipolar Transistor) chips having an emitter and a base on the front surface and a collector on the back surface.
  • the semiconductor elements 34 and 36 are diodes having an anode on the front surface and a cathode on the back surface.
  • the collectors of the semiconductor devices 30 and 32 and the cathodes of the semiconductor devices 34 and 36 are fixed to the die pad portion of the first lead terminal 14 by soldering.
  • the semiconductor element is fixed to the die pad portion of the third lead terminal 18.
  • FIG. 3 is a plan view of the semiconductor device after wire connection.
  • the wire 40 connects the emitter of the semiconductor device 30 and the anode of the semiconductor device 34 to the second lead terminal 16.
  • the wire 42 connects the emitter of the semiconductor element 32 and the anode of the semiconductor element 36 to the second lead terminal 16.
  • the wire 44 connects the gate of the semiconductor element 30 and the control terminal 24.
  • the wire 46 connects the gate of the semiconductor element 32 and the control terminal 24.
  • the semiconductor element and a part of the lead frame are connected by wire. If necessary, a heat spreader is soldered to the lead frame.
  • FIG. 4 is a plan view of a resin or the like formed by the transfer molding process.
  • the lead frame is set in the mold cavity and clamped.
  • the resin is filled in the cavity through the pot portion (where the cull 50 is present), the runner flow path on the tie bar 22, and the gate flow path.
  • the resin is cured and the mold is opened to take out a molded product in which the lead frame and the resin are integrated from the mold.
  • the resin comprises cull 50, runner 52, gate 54 and package 56.
  • the runners 52 are provided on the tie bars 22 along the tie bars 22.
  • the runner 52 fills the through hole 22d of the wide portion 22c but does not cover the upper end and the lower end of the wide portion 22c. That is, the upper end portion of the wide portion 22c is exposed in the y positive direction of the runner 52, and the lower end portion of the wide portion 22c is exposed in the y negative direction of the runner 52.
  • the package 56 is a portion that covers the semiconductor element and protects the semiconductor element.
  • the process then proceeds to the removal step.
  • the removal step is a step of striking down the runner 52 attached to the tie bar 22.
  • FIG. 5 is a plan view of a lead frame or the like in the removing step.
  • the removing step first, the upper end portion of the wide portion 22 c of the tie bar 22 is fixed by the pressing jig 60, and the lower end portion of the wide portion 22 c is fixed by the pressing jig 62.
  • the holding jig 60 has an upper portion 60a and a lower portion 60b.
  • the upper portion 60a is in contact with the upper surface of the upper end portion of the wide portion 22c
  • the lower portion 60b is in contact with the lower surface of the upper portion of the wide portion 22c. Then, the upper end of the wide portion 22c is fixed by reducing the distance between the upper portion 60a and the lower portion 60b.
  • the holding jig 62 has an upper portion 62a and a lower portion 62b.
  • the upper portion 62a is in contact with the upper surface of the lower end portion of the wide portion 22c, and the lower portion 62b is in contact with the lower surface of the lower end portion of the wide portion 22c. Then, the distance between the upper portion 62a and the lower portion 62b is reduced to fix the lower end portion of the wide portion 22c.
  • the runner 52 is knocked down in a state where the upper end and the lower end of the wide portion 22c are fixed by the holding jigs 60 and 62.
  • 7 is a cross-sectional view taken along a broken line VII-VII in FIG.
  • the runner push pin 70 is inserted into the through hole 22d provided in the wide portion 22c, and the runner 52 is knocked down. That is, the resin formed in the through hole 22 d is pushed by the runner push pin 70 to knock down the runner 52.
  • a resin of a part of the runner 52 must be formed in the through hole 22d.
  • the runner 52 is separated from the tie bar 22.
  • FIG. 8 is a cross-sectional view of a semiconductor device manufactured by the method of manufacturing a semiconductor device according to the first embodiment of the present invention. By performing each of the above steps, a plurality of semiconductor devices shown in FIG. 8 are formed.
  • the tie bar 22 of the lead frame 10 has a first narrow width portion 22a, a second narrow width portion 22b, and a wide width portion 22c.
  • the upper end portion and the lower end portion of the wide portion 22c are fixed by pressing jigs 60 and 62. Since the wide portion 22c is larger in width than the first narrow portion 22a and the second narrow portion 22b, the wide portions 22c can be easily fixed by the pressing jigs 60 and 62. By fixing the wide portion 22c, the force of the runner push pin 70 can be efficiently applied to the runner 52, and the runner 52 can be reliably removed.
  • the first narrow portion 22a and the second narrow portion 22b which are narrower than the wide portion 22c, are cut. Therefore, the clamping pressure at the time of tie bar cutting can be lowered or the number of times of clamping can be reduced. That is, the tie bar 22 can be easily cut.
  • the upper end and the lower end of the wide portion 22c are fixed by the holding jigs 60 and 62, but either one of the upper end and the lower end may be fixed. Further, either one of the upper end and the lower end of the wide portion may be omitted.
  • the y coordinate of the lower end of the wide portion is maintained at a position where the upper end of the wide portion extends in the y positive direction longer than the upper ends of the first narrow portion 22a and the second narrow portion 22b.
  • the y coordinates of the lower ends of the first narrow portion 22a and the second narrow portion 22b may be matched.
  • the upper end of the wide portion is fixed by a pressing jig.
  • An insulating sheet may be provided on the back side of the semiconductor element. Devices other than IGBTs and diodes may be used as semiconductor elements.
  • FIG. 9 is a partial plan view of the lead frame according to the second embodiment.
  • the wide portion 22e is provided with a trapezoidal portion 22f (upper end portion) which is upwardly convex in plan view, and a trapezoidal portion 22g (lower end portion) which is downwardly convex in plan view.
  • the lead frame is produced by punching and pressing a metal plate with a punching die.
  • the clamping pressure on the lead frame of the punching die should be small. Therefore, trapezoidal portions 22f and 22g are provided in the wide portion 22e. Thereby, the clamping pressure of the punching die can be made smaller than in the case of forming the wide portion having a rectangular shape.
  • FIG. 10 is a partial plan view of a lead frame according to a modification.
  • the upper end portion 22i and the lower end portion 22j of the wide portion 22h are formed in a semicircular shape in plan view.
  • the outer edge of the wide portion 22 h is curved.
  • FIG. 11 is a partial plan view of a lead frame or the like according to a third embodiment.
  • the area in which the runners are formed is indicated by a dot-and-dash line.
  • the width (y1) of the first narrow width portion 22a and the second narrow width portion 22b is smaller than the width (y2) of the runner. Therefore, the clamping pressure at the time of tie bar cutting can be lowered or the number of times of clamping can be reduced.
  • the runner flow path of sufficient width is securable by making the width
  • FIG. 12 is a partial plan view of the lead frame according to the fourth embodiment.
  • An upper end side through hole 22k is formed on the upper end side of the wide portion 22c, and a lower end side through hole 22m is formed on the lower end side of the wide portion 22c.
  • the through hole 22d is located between the upper end through hole 22k and the lower end through hole 22m.
  • FIG. 13 is a cross-sectional view of a holding jig or the like in the removing step.
  • the wide portion 22c of the tie bar shown in FIG. 13 is a wide portion at line XIII-XIII in FIG.
  • the holding jig 60 has a convex portion 60c integrally formed with the upper portion 60a
  • the holding jig 62 has a convex portion 62c integrally formed with the upper portion 62a.
  • the convex portion 60c is inserted into the upper end side through hole 22k
  • the convex portion 62c is inserted into the lower end side through hole 22m.
  • the position of the lead frame can be set to a predetermined position, so that the runner pin can be reliably passed through the through hole 22d.
  • the convex portions 60c and 62c inserted into the upper end side through hole 22k and the lower end side through hole 22m suppress the displacement of the lead frame in the left-right direction. Therefore, displacement and lifting of the lead frame due to molding shrinkage of the runner 52 can be prevented. Moreover, since the upper end side through hole 22 k and the lower end side through hole 22 m are provided in a part of the tie bar 22, the convex portions 60 c and 62 c inserted into these are close to the runner 52. Therefore, the displacement of the lead frame can be sufficiently suppressed. Only one of the upper end side through hole and the lower end side through hole may be provided.
  • FIG. 14 is a partial plan view of the lead frame according to the fifth embodiment.
  • An upper end side recess 22o is formed on the upper end side of the wide portion 22c, and a lower end side recess 22p is formed on the lower end side of the wide portion 22c.
  • the through hole 22d is located between the upper end recess 22o at the upper end of the wide portion 22c and the lower end recess 22p at the lower end of the wide portion 22c.
  • FIG. 15 is a cross-sectional view of a holding jig or the like in the removing step.
  • the holding jigs 60 and 62 have convex portions 60c and 62c, respectively.
  • the convex portion 60c is inserted into the upper end side concave portion 22o
  • the convex portion 62c is inserted into the lower end side concave portion 22p.
  • the lead frame can be positioned at a predetermined position.
  • the convex portions 60c and 62c are pressed against the wide portion 22c, the effect of preventing the lead frame from floating can be enhanced.

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Abstract

　第１リード端子と、該第１リード端子と平行に設けられた第２リード端子と、該第１リード端子と該第２リード端子を接続するタイバーと、を備え、該タイバーは、該第１リード端子に接する第１幅狭部と、該第２リード端子に接する第２幅狭部と、該第１幅狭部と該第２幅狭部よりも幅が広く、該第１幅狭部と該第２幅狭部をつなぐ幅広部と、を備え、該幅広部のうち該第１幅狭部と該第２幅狭部の間の部分には貫通孔が形成されたことを特徴とする。

Description

リードフレーム、半導体装置の製造方法
　この発明は、リードフレーム及びリードフレームを備えた半導体装置の製造方法に関する。
　特許文献１には、リードフレームを樹脂で封止した後に、不要樹脂をブレイクピンで突いて除去することが開示されている。
日本特開２００７－１２８９３０号公報
　ランナー突きピンで不要樹脂の一部であるランナーを突いて、ランナーを打ち落とす。ランナーの打ち落としは、タイバーの一部を押さえジグで押さえた状態で行うことが好ましい。押さえジグでタイバーを固定するためには、タイバー幅が大きい方が好ましい。
　他方、タイバーは製品完成前に切断される部分である。よって、タイバーを容易に切断するためには、タイバー幅が小さい方が好ましい。このように、タイバー幅を小さくすれば押さえジグでタイバーを固定しづらくなり、タイバー幅を大きくすればタイバーを容易に切断できなくなる問題があった。
　本発明は上述の問題を解決するためになされたものであり、押さえジグでタイバーを押さえることが容易であり、かつタイバーの切断が容易なリードフレームと、そのリードフレームを用いた半導体装置の製造方法を提供することを目的とする。
　本願の発明にかかるリードフレームは、第１リード端子と、該第１リード端子と平行に設けられた第２リード端子と、該第１リード端子と該第２リード端子を接続するタイバーと、を備え、該タイバーは、該第１リード端子に接する第１幅狭部と、該第２リード端子に接する第２幅狭部と、該第１幅狭部と該第２幅狭部よりも幅が広く、該第１幅狭部と該第２幅狭部をつなぐ幅広部と、を備え、該幅広部のうち該第１幅狭部と該第２幅狭部の間の部分には貫通孔が形成されたことを特徴とする。
　本願の発明にかかる半導体装置の製造方法は、第１リード端子と、第２リード端子と、該第１リード端子と該第２リード端子を接続するタイバーを備えるリードフレームに半導体素子を固定する工程と、該タイバーに沿ったランナー流路を設け該半導体素子を覆う樹脂を形成するトランスファーモールド工程と、該第１リード端子に接する第１幅狭部と、該第２リード端子に接する第２幅狭部と、該第１幅狭部と該第２幅狭部よりも幅が広く、該第１幅狭部と該第２幅狭部をつなぐ幅広部と、を備える該タイバーの該幅広部の上端部又は下端部を押さえジグで固定しつつ、該幅広部のうち該第１幅狭部と該第２幅狭部の間の部分に設けられた貫通孔にランナー突きピンを挿入し、該タイバーに付着したランナーを打ち落とす除去工程と、該第１幅狭部と該第２幅狭部を切断する工程と、を備えたことを特徴とする。
　本発明のその他の特徴は以下に明らかにする。
　この発明によれば、タイバーに幅の大きい部分と幅の小さい部分を設けたので、押さえジグでタイバーを押さえることと、タイバーを切断することを容易に実施できる。
実施の形態１に係るリードフレームの平面図である。 リードフレームと半導体素子を示す平面図である。 ワイヤ接続後の半導体装置の平面図である。 樹脂等の平面図である。 除去工程におけるリードフレーム等の平面図である。 図５のＶＩ－ＶＩ破線における断面図である。 図５のＶＩＩ－ＶＩＩ破線における断面図である。 実施の形態１に係る半導体装置の製造方法で製造された半導体装置の断面図である。 実施の形態２に係るリードフレームの一部平面図である。 変形例に係るリードフレームの一部平面図である。 実施の形態３に係るリードフレーム等の一部平面図である。 実施の形態４に係るリードフレームの一部平面図である。 除去工程における押さえジグ等の断面図である。 実施の形態５に係るリードフレームの一部平面図である。 除去工程における押さえジグ等の断面図である。
　本発明の実施の形態に係るリードフレーム及び半導体装置の製造方法について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。
実施の形態１．
　図１は、本発明の実施の形態１に係るリードフレーム１０の平面図である。リードフレーム１０は外枠１２を備えている。外枠１２には、第１リード端子１４、第２リード端子１６、第３リード端子１８、及び第４リード端子２０が接続されている。これらのリード端子は平行に設けられている。
　外枠１２と第１リード端子１４、第１リード端子１４と第２リード端子１６、第２リード端子１６と第３リード端子１８、第３リード端子１８と第４リード端子２０は、それぞれタイバー２２で接続されている。タイバー２２は、第１幅狭部２２ａ、第２幅狭部２２ｂ及び幅広部２２ｃを備えている。第１幅狭部２２ａは第１リード端子１４に接する。第２幅狭部２２ｂは第２リード端子１６に接する。幅広部２２ｃは第１幅狭部２２ａと第２幅狭部２２ｂをつなぐ。
　幅広部２２ｃは、第１幅狭部２２ａと第２幅狭部２２ｂよりも幅が広い。つまり、幅広部２２ｃは、第１幅狭部２２ａと第２幅狭部２２ｂよりも上方向（ｙ正方向）に長く伸び、かつ下方向（ｙ負方向）に長く伸びている。幅広部２２ｃのうち第１幅狭部２２ａと第２幅狭部２２ｂの間の部分には貫通孔２２ｄが形成されている。
　本発明の実施の形態１に係る半導体装置の製造方法を説明する。まず、リードフレームに半導体素子を固定する。図２は、リードフレームと半導体素子を示す平面図である。半導体素子３０、３２は表面にエミッタとベースを有し裏面にコレクタを有するＩＧＢＴ(Insulated Gate Bipolar transistor)チップである。半導体素子３４、３６は表面にアノードを有し裏面にカソードを有するダイオードである。半導体素子３０、３２のコレクタと半導体素子３４、３６のカソードをはんだで第１リード端子１４のダイパッド部分に固定する。同様に、半導体素子を第３リード端子１８のダイパッド部分に固定する。
　次いで、必要なワイヤ接続を行う。図３は、ワイヤ接続後の半導体装置の平面図である。ワイヤ４０は、半導体素子３０のエミッタと半導体素子３４のアノードを第２リード端子１６に接続する。ワイヤ４２は、半導体素子３２のエミッタと半導体素子３６のアノードを第２リード端子１６に接続する。ワイヤ４４は、半導体素子３０のゲートと制御端子２４を接続する。ワイヤ４６は、半導体素子３２のゲートと制御端子２４を接続する。こうして、半導体素子とリードフレームの一部をワイヤ接続する。なお、必要に応じて、リードフレームにヒートスプレッダをはんだ接合する。
　次いで、トランスファーモールド工程に処理を進める。トランスファーモールド工程では、複数の成形品を１セットの金型で成形する。この成形方式は、サイドランナーゲート方式と呼ばれている。図４は、トランスファーモールド工程により形成された樹脂等の平面図である。トランスファーモールド工程では、リードフレームを金型のキャビティ内にセットし、型締めする。そして、ポット部（カル５０のある場所）、タイバー２２上のランナー流路、及びゲート流路を経由させた樹脂を、キャビティ内に充填する。その後、樹脂を硬化させ、型開きすることで、リードフレームと樹脂が一体化した成形品を金型から取り出す。樹脂は、カル５０、ランナー５２、ゲート５４及びパッケージ５６を含む。ランナー５２はタイバー２２に沿ってタイバー２２の上に設けられる。ランナー５２は幅広部２２ｃの貫通孔２２ｄを埋めるが、幅広部２２ｃの上端部と下端部は覆わない。つまり、幅広部２２ｃの上端部はランナー５２のｙ正方向に露出し、幅広部２２ｃの下端部はランナー５２のｙ負方向に露出している。パッケージ５６は、半導体素子を覆い、半導体素子を保護する部分である。
　次いで、除去工程に処理を進める。除去工程は、タイバー２２に付着したランナー５２を打ち落とす工程である。図５は、除去工程におけるリードフレーム等の平面図である。除去工程ではまず、タイバー２２の幅広部２２ｃの上端部を押さえジグ６０で固定し、幅広部２２ｃの下端部を押さえジグ６２で固定する。
　図６は、図５のＶＩ－ＶＩ破線における断面図である。押さえジグ６０は上部６０ａと下部６０ｂを備えている。上部６０ａが幅広部２２ｃの上端部の上面に接し、下部６０ｂが幅広部２２ｃの上端部の下面に接する。そして、上部６０ａと下部６０ｂの距離を小さくすることで、幅広部２２ｃの上端部を固定する。押さえジグ６２は上部６２ａと下部６２ｂを備えている。上部６２ａが幅広部２２ｃの下端部の上面に接し、下部６２ｂが幅広部２２ｃの下端部の下面に接する。そして、上部６２ａと下部６２ｂの距離を小さくすることで、幅広部２２ｃの下端部を固定する。
　このように、幅広部２２ｃの上端部と下端部を押さえジグ６０、６２により固定した状態で、ランナー５２を打ち落とす。図７は、図５のＶＩＩ－ＶＩＩ破線における断面図である。幅広部２２ｃに設けられた貫通孔２２ｄにランナー突きピン７０を挿入し、ランナー５２を打ち落とす。つまり、貫通孔２２ｄに形成された樹脂をランナー突きピン７０で突いて、ランナー５２を打ち落とす。ランナー突きピン７０でランナー５２を打ち落とすためには、貫通孔２２ｄにランナー５２の一部の樹脂が形成されていなければならない。こうして、ランナー５２をタイバー２２から分離させる。
　次いで、パッケージ５６を完全硬化させるための加熱工程を実施する。次いで、タイバー２２の第１幅狭部２２ａと第２幅狭部２２ｂを切断する。さらに、例えば外枠１２等のリードフレーム１０の不要部分を切断する。その後、リード端子の成形、製品テスト等を経て、半導体装置が完成する。図８は、本発明の実施の形態１に係る半導体装置の製造方法で製造された半導体装置の断面図である。上記の各工程を実施することで、図８に示す半導体装置が複数個形成される。
　実施の形態１に係るリードフレーム１０のタイバー２２は、第１幅狭部２２ａ、第２幅狭部２２ｂ及び幅広部２２ｃを有している。除去工程では、幅広部２２ｃの上端部と下端部を押さえジグ６０、６２で固定する。幅広部２２ｃは、第１幅狭部２２ａと第２幅狭部２２ｂよりも幅が大きいので、押さえジグ６０、６２により容易に幅広部２２ｃを固定できる。幅広部２２ｃを固定することで、ランナー突きピン７０の力を効率よくランナー５２にかけて確実にランナー５２を除去できる。
　また、タイバー２２を切断する際には、幅広部２２ｃよりも幅の狭い第１幅狭部２２ａと第２幅狭部２２ｂを切断する。したがって、タイバーカット時のクランプ圧を低くしたり、クランプ回数を少なくしたりすることができる。つまり、容易にタイバー２２を切断できる。
　除去工程では押さえジグ６０、６２で幅広部２２ｃの上端部と下端部を固定したが、上端部と下端部のずれか一方を固定してもよい。また、幅広部の上端部と下端部のいずれか一方を省略してもよい。例えば、図１において、幅広部の上端は第１幅狭部２２ａと第２幅狭部２２ｂの上端よりもｙ正方向に長く伸びた状態を維持しつつ、幅広部の下端のｙ座標を第１幅狭部２２ａと第２幅狭部２２ｂの下端のｙ座標と一致させてもよい。この場合、押さえジグで幅広部の上端部を固定する。半導体素子の裏面側に絶縁シートを設けてもよい。半導体素子としてＩＧＢＴとダイオード以外のデバイスを利用しても良い。
　これらの変形は以下の実施の形態に係るリードフレームと半導体装置の製造方法にも応用できる。なお、以下の実施の形態に係るリードフレーム及び半導体装置の製造方法は、実施の形態１との共通点が多いので実施の形態１との相違点を中心に説明する。
実施の形態２．
　図９は、実施の形態２に係るリードフレームの一部平面図である。幅広部２２ｅは平面視で上に凸となる台形部分２２ｆ（上端部分）と、平面視で下に凸となる台形部分２２ｇ（下端部分）を備えている。リードフレームは、金属板をパンチング金型でパンチングプレスすることにより生産する。パンチング金型のリードフレームに対するクランプ圧力は小さい方がよい。そこで、幅広部２２ｅに台形部分２２ｆ、２２ｇを設けた。これにより、矩形形状の幅広部を形成する場合よりも、パンチング金型のクランプ圧力を小さくすることができる。
　図１０は、変形例に係るリードフレームの一部平面図である。幅広部２２ｈの上端部分２２ｉと下端部分２２ｊは平面視で半円状に形成されている。これにより、幅広部２２ｈの外縁は曲線となっている。幅広部の外縁を曲線とすることで、パンチング金型のクランプ圧力を小さくすることができる。
実施の形態３．
　図１１は、実施の形態３に係るリードフレーム等の一部平面図である。ランナーが形成される領域は一点鎖線で示されている。第１幅狭部２２ａと第２幅狭部２２ｂの幅（ｙ１）は、ランナーの幅（ｙ２）より小さい。よって、タイバーカット時のクランプ圧を低くしたり、クランプ回数を少なくしたりすることができる。また、ランナーの幅（ｙ２）を第１幅狭部２２ａと第２幅狭部２２ｂの幅（ｙ１）より大きくすることで、十分な幅のランナー流路を確保できる。
実施の形態４．
　図１２は、実施の形態４に係るリードフレームの一部平面図である。幅広部２２ｃの上端側には上端側貫通孔２２ｋが形成され、幅広部２２ｃの下端側には下端側貫通孔２２ｍが形成されている。貫通孔２２ｄは、上端側貫通孔２２ｋと下端側貫通孔２２ｍに挟まれた位置にある。
　図１３は、除去工程における押さえジグ等の断面図である。図１３に示されるタイバーの幅広部２２ｃは、図１２のＸＩＩＩ－ＸＩＩＩ線における幅広部である。押さえジグ６０は上部６０ａと一体形成された凸部６０ｃを有し、押さえジグ６２は上部６２ａと一体形成された凸部６２ｃを有している。除去工程では、凸部６０ｃを上端側貫通孔２２ｋに挿入し、凸部６２ｃを下端側貫通孔２２ｍに挿入する。これにより、リードフレームの位置を予め定められた位置にすることができるので、確実にランナー突きピンを貫通孔２２ｄに通すことができる。
　上端側貫通孔２２ｋと下端側貫通孔２２ｍに挿入された凸部６０ｃ、６２ｃは、リードフレームの左右方向の変位を抑制する。したがって、ランナー５２の成型収縮によるリードフレームの変位及び浮きを防ぐことができる。しかも、上端側貫通孔２２ｋと下端側貫通孔２２ｍがタイバー２２の一部に設けられているので、これらに挿入される凸部６０ｃ、６２ｃはランナー５２に近接している。そのため、リードフレームの変位を十分に抑制することができる。なお、上端側貫通孔と下端側貫通孔のいずれか一方だけを設けてもよい。
実施の形態５．
　図１４は、実施の形態５に係るリードフレームの一部平面図である。幅広部２２ｃの上端側には上端側凹部２２ｏが形成され、幅広部２２ｃの下端側には下端側凹部２２ｐが形成されている。貫通孔２２ｄは、幅広部２２ｃの上端部にある上端側凹部２２ｏと幅広部２２ｃの下端部にある下端側凹部２２ｐに挟まれた位置にある。
　図１５は、除去工程における押さえジグ等の断面図である。押さえジグ６０、６２はそれぞれ凸部６０ｃ、６２ｃを有している。除去工程では、凸部６０ｃを上端側凹部２２ｏに挿入し、凸部６２ｃを下端側凹部２２ｐに挿入する。これにより、リードフレームを予め定められた場所に位置させることができる。しかも、凸部６０ｃ、６２ｃが幅広部２２ｃに押し付けられるので、リードフレームの浮きを防止する効果を高めることができる。
　なお、上記の各実施の形態に係るリードフレームと半導体装置の製造方法の特徴を適宜に組み合わせても良い。
　１０　リードフレーム、　１２　外枠、　１４　第１リード端子、　１６　第２リード端子、　１８　第３リード端子、　２０　第４リード端子、　２２　タイバー、　２２ａ　第１幅狭部、　２２ｂ　第２幅狭部、　２２ｃ　幅広部、　２２ｄ　貫通孔、　２２ｋ　上端側貫通孔、　２２ｍ　下端側貫通孔、　２２ｏ　上端側凹部、　２２ｐ　下端側凹部、　２４　制御端子、　３０,３２,３４,３６　半導体素子、　５０　カル、　５２　ランナー、　５４　ゲート、　５６　パッケージ、　６０,６２　押さえジグ、　７０　ランナー突きピン

Claims (9)

  1. 　第１リード端子と、
    　前記第１リード端子と平行に設けられた第２リード端子と、
    　前記第１リード端子と前記第２リード端子を接続するタイバーと、を備え、
    　前記タイバーは、
    　前記第１リード端子に接する第１幅狭部と、
    　前記第２リード端子に接する第２幅狭部と、
    　前記第１幅狭部と前記第２幅狭部よりも幅が広く、前記第１幅狭部と前記第２幅狭部をつなぐ幅広部と、を備え、
    　前記幅広部のうち前記第１幅狭部と前記第２幅狭部の間の部分には貫通孔が形成されたことを特徴とするリードフレーム。
  2. 　前記幅広部は平面視で上に凸となる台形部分と、平面視で下に凸となる台形部分を備えたことを特徴とする請求項１に記載のリードフレーム。
  3. 　前記幅広部の外縁は曲線であることを特徴とする請求項１に記載のリードフレーム。
  4. 　前記幅広部の上端側には上端側貫通孔が形成され、前記幅広部の下端側には下端側貫通孔が形成されたことを特徴とする請求項１～３のいずれか１項に記載のリードフレーム。
  5. 　前記幅広部の上端側には上端側凹部が形成され、前記幅広部の下端側には下端側凹部が形成されたことを特徴とする請求項１～３のいずれか１項に記載のリードフレーム。
  6. 　第１リード端子と、第２リード端子と、前記第１リード端子と前記第２リード端子を接続するタイバーを備えるリードフレームに半導体素子を固定する工程と、
    　前記タイバーに沿ったランナー流路を設け前記半導体素子を覆う樹脂を形成するトランスファーモールド工程と、
    　前記第１リード端子に接する第１幅狭部と、前記第２リード端子に接する第２幅狭部と、前記第１幅狭部と前記第２幅狭部よりも幅が広く、前記第１幅狭部と前記第２幅狭部をつなぐ幅広部と、を備える前記タイバーの前記幅広部の上端部又は下端部を押さえジグで固定しつつ、前記幅広部のうち前記第１幅狭部と前記第２幅狭部の間の部分に設けられた貫通孔にランナー突きピンを挿入し、前記タイバーに付着したランナーを打ち落とす除去工程と、
    　前記第１幅狭部と前記第２幅狭部を切断する工程と、を備えたことを特徴とする半導体装置の製造方法。
  7. 　前記第１幅狭部と前記第２幅狭部の幅は、前記ランナーの幅より小さいことを特徴とする請求項６に記載の半導体装置の製造方法。
  8. 　前記幅広部には、前記上端部に設けられた上端側貫通孔、又は前記下端部に設けられた下端側貫通孔が形成され、
    　前記押さえジグは凸部を有し、前記除去工程では、前記凸部を前記上端側貫通孔又は前記下端側貫通孔に挿入し、前記リードフレームの位置を予め定められた位置にすることを特徴とする請求項６又は７に記載の半導体装置の製造方法。
  9. 　前記幅広部には、前記上端部に設けられた上端側凹部、又は前記下端部に設けられた下端側凹部が形成され、
    　前記押さえジグは凸部を有し、前記除去工程では、前記凸部を前記上端側凹部又は前記下端側凹部に挿入し、前記リードフレームの位置を予め定められた位置にすることを特徴とする請求項６又は７に記載の半導体装置の製造方法。
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JP6237919B2 (ja) 2017-11-29

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