JP6237919B2 - リードフレーム、半導体装置の製造方法 - Google Patents
リードフレーム、半導体装置の製造方法 Download PDFInfo
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- JP6237919B2 JP6237919B2 JP2016551455A JP2016551455A JP6237919B2 JP 6237919 B2 JP6237919 B2 JP 6237919B2 JP 2016551455 A JP2016551455 A JP 2016551455A JP 2016551455 A JP2016551455 A JP 2016551455A JP 6237919 B2 JP6237919 B2 JP 6237919B2
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- 239000004065 semiconductor Substances 0.000 title claims description 45
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 238000000034 method Methods 0.000 claims description 24
- 239000011347 resin Substances 0.000 claims description 13
- 229920005989 resin Polymers 0.000 claims description 13
- 238000001721 transfer moulding Methods 0.000 claims description 6
- 238000005520 cutting process Methods 0.000 claims description 4
- 238000003825 pressing Methods 0.000 claims description 4
- 238000004080 punching Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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Description
図1は、本発明の実施の形態1に係るリードフレーム10の平面図である。リードフレーム10は外枠12を備えている。外枠12には、第1リード端子14、第2リード端子16、第3リード端子18、及び第4リード端子20が接続されている。これらのリード端子は平行に設けられている。
図9は、実施の形態2に係るリードフレームの一部平面図である。幅広部22eは平面視で上に凸となる台形部分22f(上端部分)と、平面視で下に凸となる台形部分22g(下端部分)を備えている。リードフレームは、金属板をパンチング金型でパンチングプレスすることにより生産する。パンチング金型のリードフレームに対するクランプ圧力は小さい方がよい。そこで、幅広部22eに台形部分22f、22gを設けた。これにより、矩形形状の幅広部を形成する場合よりも、パンチング金型のクランプ圧力を小さくすることができる。
図11は、実施の形態3に係るリードフレーム等の一部平面図である。ランナーが形成される領域は一点鎖線で示されている。第1幅狭部22aと第2幅狭部22bの幅(y1)は、ランナーの幅(y2)より小さい。よって、タイバーカット時のクランプ圧を低くしたり、クランプ回数を少なくしたりすることができる。また、ランナーの幅(y2)を第1幅狭部22aと第2幅狭部22bの幅(y1)より大きくすることで、十分な幅のランナー流路を確保できる。
図12は、実施の形態4に係るリードフレームの一部平面図である。幅広部22cの上端側には上端側貫通孔22kが形成され、幅広部22cの下端側には下端側貫通孔22mが形成されている。貫通孔22dは、上端側貫通孔22kと下端側貫通孔22mに挟まれた位置にある。
図14は、実施の形態5に係るリードフレームの一部平面図である。幅広部22cの上端側には上端側凹部22oが形成され、幅広部22cの下端側には下端側凹部22pが形成されている。貫通孔22dは、幅広部22cの上端部にある上端側凹部22oと幅広部22cの下端部にある下端側凹部22pに挟まれた位置にある。
Claims (9)
- 第1リード端子と、
前記第1リード端子と平行に設けられた第2リード端子と、
前記第1リード端子と前記第2リード端子を接続するタイバーと、を備え、
前記タイバーは、
前記第1リード端子に接する第1幅狭部と、
前記第2リード端子に接する第2幅狭部と、
前記第1幅狭部と前記第2幅狭部よりも幅が広く、前記第1幅狭部と前記第2幅狭部をつなぐ幅広部と、を備え、
前記幅広部のうち前記第1幅狭部と前記第2幅狭部の間の部分には貫通孔が形成され、
前記貫通孔は前記幅広部だけにあることを特徴とするリードフレーム。 - 前記幅広部は平面視で上に凸となる台形部分と、平面視で下に凸となる台形部分を備えたことを特徴とする請求項1に記載のリードフレーム。
- 前記幅広部の外縁は曲線であることを特徴とする請求項1に記載のリードフレーム。
- 前記幅広部の上端側には上端側貫通孔が形成され、前記幅広部の下端側には下端側貫通孔が形成されたことを特徴とする請求項1〜3のいずれか1項に記載のリードフレーム。
- 前記幅広部の上端側には上端側凹部が形成され、前記幅広部の下端側には下端側凹部が形成されたことを特徴とする請求項1〜3のいずれか1項に記載のリードフレーム。
- 第1リード端子と、第2リード端子と、前記第1リード端子と前記第2リード端子を接続するタイバーを備えるリードフレームに半導体素子を固定する工程と、
前記タイバーに沿ったランナー流路を設け前記半導体素子を覆う樹脂を形成するトランスファーモールド工程と、
前記第1リード端子に接する第1幅狭部と、前記第2リード端子に接する第2幅狭部と、前記第1幅狭部と前記第2幅狭部よりも幅が広く、前記第1幅狭部と前記第2幅狭部をつなぐ幅広部と、を備える前記タイバーの前記幅広部の上端部又は下端部を押さえジグで固定しつつ、前記幅広部のうち前記第1幅狭部と前記第2幅狭部の間の部分に設けられた貫通孔にランナー突きピンを挿入し、前記タイバーに付着したランナーを打ち落とす除去工程と、
前記第1幅狭部と前記第2幅狭部を切断する工程と、を備えたことを特徴とする半導体装置の製造方法。 - 前記第1幅狭部と前記第2幅狭部の幅は、前記ランナーの幅より小さいことを特徴とする請求項6に記載の半導体装置の製造方法。
- 前記幅広部には、前記上端部に設けられた上端側貫通孔、又は前記下端部に設けられた下端側貫通孔が形成され、
前記押さえジグは凸部を有し、前記除去工程では、前記凸部を前記上端側貫通孔又は前記下端側貫通孔に挿入し、前記リードフレームの位置を予め定められた位置にすることを特徴とする請求項6又は7に記載の半導体装置の製造方法。 - 前記幅広部には、前記上端部に設けられた上端側凹部、又は前記下端部に設けられた下端側凹部が形成され、
前記押さえジグは凸部を有し、前記除去工程では、前記凸部を前記上端側凹部又は前記下端側凹部に挿入し、前記リードフレームの位置を予め定められた位置にすることを特徴とする請求項6又は7に記載の半導体装置の製造方法。
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