CN106409694B - 半导体装置及其制造方法 - Google Patents
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Abstract
散热性良好的半导体装置的制造方法中,成形承载半导体芯片的岛部的成形模具由内冲头(10)和冲头导槽(11)和外冲头(12)构成,抵接成形模具而形成岛部的凹部(14)和突出壁(8)和薄壁部(9)。使所述岛部的背面露出,通过树脂来密封岛部的表面及侧面、薄壁部、半导体芯片、内部引线及导线。
Description
技术领域
本发明涉及承载半导体芯片的岛部(island)的背面从密封树脂露出的半导体装置及其的制造方法。
背景技术
通常,在承载半导体芯片的岛部的背面从密封树脂露出的高散热型半导体装置中,将元件搭载部的背面抵接到密封模具而填充密封树脂时,存在密封树脂流入元件搭载部的背面与密封模具之间,在岛部的背面侧产生薄毛刺的情况。在该情况下,出现岛部的背面侧的露出部的有效面积减少而散热效果降低的问题。
因此,想到通过在岛部的背面侧形成凹形(挖孔)和岛部背面的突出壁,提高密封时突出壁向下模的按压,防止薄毛刺入侵到岛部的背面部的中央部的对策(例如,参照专利文献1)。
现有技术文献
专利文献
专利文献1:日本特开2013-175795号公报。
发明内容
【发明要解决的课题】
然而,如专利文献1所示,通过在岛部的背面侧形成凹形(挖孔),可以一定程度抑制薄毛刺向岛部的背面的入侵,但并不是完全抑制的。另外,因凹形的形状而在树脂毛刺除去工序中不能充分地除去进入到凹部的树脂毛刺,在基板安装时产生起因于树脂毛刺的空隙,有可能降低散热特性。
本发明鉴于上述不良情况而构思,其课题在于提供防止薄毛刺向岛部背面的附着的半导体装置的制造方法。
【用于解决课题的方案】
为了解决上述课题而采用了以下方案。
首先,承载半导体芯片的岛部的背面从密封树脂露出的半导体装置的制造方法中,其特征在于包括:成形由所述岛部和内部引线和外部引线构成的引线框的工序;在所述岛部上承载半导体芯片的工序;经由导线连接所述半导体芯片和所述内部引线的工序;以及树脂密封所述岛部和所述半导体芯片和所述内部引线和导线的工序,成形所述引线框的工序中,将成为岛部的片材置于小片(die),将由内冲头(inner punch)和冲头导槽和外冲头构成的成形模具抵接到片材,同时成形与内冲头抵接的凹部、与冲头导槽抵接的突出壁、和与外冲头抵接的薄壁部。
另外,半导体装置的制造方法的特征在于:在成形所述引线框的工序中,使用所述内冲头和所述冲头导槽的阶梯差可变的成形模具。
另外,半导体装置的制造方法的特征在于:在成形所述引线框的工序中,使用所述内冲头和所述外冲头的间隔可变的成形模具。
另外,半导体装置的制造方法的特征在于:在所述树脂密封的工序中,在模具内的空腔的中央设置浇口,在比所述空腔的中央靠下方设置所述薄壁部,从所述浇口进行树脂注入。
【发明效果】
通过采用上述方案,能够抑制在岛部的背面侧产生的薄毛刺,确保岛部的露出部的有效面积,得到较高的散热特性。
附图说明
【图1】本发明的第一实施方式所涉及的半导体装置的截面图。
【图2】示出本发明的第一实施方式所涉及的半导体装置中所使用的引线框(岛部)的制造工序的侧面图。
【图3】本发明的第一实施方式所涉及的半导体装置的(透过)平面图。
【图4】本发明的第一实施方式所涉及的半导体装置的背面图。
具体实施方式
以下,基于附图,说明用于实施本发明的方式。
图1是本发明的第一实施方式所涉及的半导体装置的截面图。
半导体芯片2承载于岛部7上,半导体芯片2上的电极(未图示)经由导线3与内部引线5电连接。岛部7、半导体芯片2、导线3被密封树脂4覆盖。而且,为了提高散热性,岛部7的背面从密封树脂4露出。从内部引线5延伸的外部引线6也从密封树脂4露出,其端部连接到布线基板等。
在此,作为本发明的半导体装置1的特征之处在于这一点,即岛部7具有遍及背面的周围的整个圆周而向下方突出的突出壁8和被它包围的凹部14,并且在岛部7的侧面的上端部具有向侧方突出的薄壁部9。岛部7的表面和薄壁部9的上表面为相同高度,形成平面。突出壁8可以控制在其高度为0.05~0.10mm、宽度为0.05~0.20mm的范围。通过在岛部7的背面的周围设置具有如此的高度的突出壁8,在对承载于岛部7上的半导体芯片2进行树脂密封时突出壁8被按压到树脂密封用的下模(未图示),基于以下理由能够防止密封树脂的浸入、抑制薄毛刺的产生。
即,在本发明中在岛部7的侧面的上端部设置向侧方突出的薄壁部9,该薄壁部9在树脂密封时起到将岛部7按到下模这一作用。虽然未图示,但是注入树脂的浇口设置在由上模和下模形成的空腔的纵向的中央附近,从此处向周围的模具供给树脂。岛部7的薄壁部9比上述中央附近更靠下方,因此薄壁部9的上方的树脂体积会比下方的树脂体积大得多,将岛部7按到下模,所以会防止树脂通过突出壁8之下而向凹部14入侵。
如以上说明的那样,在本发明中,在岛部的周围的下端部设置向下方突出的突出壁和被它包围的凹部并且在岛部7的周围的上端部设置向侧方突出的薄壁部,因此抑制在岛部7的背面产生薄毛刺,减轻对露出部有效面积缩小的担忧,能够确保较高的散热性。
图2是示出半导体装置的岛部的成形工序的侧面图。
在此,上下相反地图示了图1所示的岛部7。将岛部7的厚度夸大描绘。在小片13的平坦面上以使岛部7的半导体芯片承载面朝下的方式放置由岛部的材料即铜或铜合金构成的片材,岛部7的背面通过成形模具来成形。成形模具由内冲头10和冲头导槽11和外冲头12构成,通过内冲头10在岛部7的背面形成凹部14。在内冲头10的两端设有冲头导槽11,由此决定突出壁8的高度,通过在冲头导槽11的外侧设置的外冲头12来形成薄壁部9。
即,以使凹部14与内冲头10抵接、突出壁8与冲头导槽11抵接、薄壁部9与外冲头12抵接的方式成形。在本发明中因为从内冲头10和外冲头12双方按压岛部7,所以在冲头导槽11会推出大量的铜部件。因此,突出壁8有可能设为最大到0.10mm的高度,而且,由于存在与该突出壁8同时形成的薄壁部9,树脂密封时可以防止密封树脂的入侵、抑制薄毛刺的产生。
此外,通过成形模具的内冲头10和冲头导槽11和外冲头12的相互高度和成形模具对片材的抵接压的调整,能够调整凹部14的深度和突出壁8的高度和薄壁部9厚度。在此使用的成形模具能够将内冲头10和冲头导槽11的阶梯差设为可变,另外,将内冲头10和外冲头12的间隔设为可变,由此,能得到期望的高度和宽度的突出壁。
另外,通过冲裁从实施镀银的由铜或铜合金构成的片材形成内部引线5、外部引线6、岛部7。岛部7在冲裁后进行下压(depress)加工。岛部7在冲裁后根据需要进行翘曲矫正。对片材进行下压加工后切割为框尺寸,完成引线框的制作。
图3是本发明的第一实施方式所涉及的半导体装置的透视平面图。在岛部7上,隔着导电性或绝缘性接合膜而承载半导体芯片2,半导体芯片2上的电极(未图示)经由用金(Au)或铜(Cu)构成的导线3而与内部引线5电连接。岛部7、半导体芯片2、导线3被密封树脂4覆盖。从内部引线5延伸的外部引线6从密封树脂4露出,构成为其端部连接到布线基板等。另外,薄壁部9设置在岛部7的整个周围,从而增加密封树脂4与岛部7的接触面积,提高密合性,从而也起到防止岛部7从密封树脂4脱落这一作用。
图4是本发明的第一实施方式所涉及的半导体装置的背面图。
多个外部引线6从密封树脂4的侧面引出,在密封树脂的中央区域配置有在整个周围设置突出壁8的岛部7。该岛部7背面的凹部14露出,以能确保较高的散热性。
附图所使用的标号如下:
1 半导体装置;2 半导体芯片;3 导线;4 密封树脂;5 内部引线;6 外部引线;7岛部;8 突出壁;9 薄壁部;10 内冲头;11 冲头导槽;12 外冲头;13 小片;14 凹部。
Claims (4)
1.一种半导体装置的制造方法,所述半导体装置中承载半导体芯片的岛部的背面从密封树脂露出,其特征在于包括:
成形由岛部和内部引线和外部引线构成的引线框的工序;
在所述岛部上承载半导体芯片的工序;
经由导线连接所述半导体芯片和所述内部引线的工序;以及
树脂密封所述岛部、所述半导体芯片、所述内部引线及所述导线的工序,
成形所述引线框的工序中,将成为岛部的片材置于小片,抵接由内冲头和冲头导槽和外冲头构成的成形模具,同时成形与所述内冲头抵接的凹部、与所述冲头导槽抵接的突出壁、和与所述外冲头抵接的薄壁部,
在成形所述引线框的工序中,所述冲头导槽与所述突出壁在所述突出壁的高度方向上相接触,由此,决定所述突出壁的高度。
2.如权利要求1所述的半导体装置的制造方法,其特征在于:在成形所述引线框的工序中,使用所述内冲头和所述冲头导槽的阶梯差可变的成形模具。
3.如权利要求1所述的半导体装置的制造方法,其特征在于:在成形所述引线框的工序中,使用所述内冲头和所述外冲头的间隔可变的成形模具。
4.如权利要求1所述的半导体装置的制造方法,其特征在于:在所述树脂密封的工序中,在模具内的空腔的中央设置浇口,在比所述空腔的中央靠下方设置所述薄壁部,从所述浇口进行树脂注入。
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JPH06302736A (ja) * | 1993-04-14 | 1994-10-28 | Nec Corp | 半導体装置用リードフレームの製造方法および半導体装置 |
JP2013069955A (ja) * | 2011-09-26 | 2013-04-18 | Renesas Electronics Corp | 半導体装置、半導体装置の製造方法およびリードフレーム |
JP2013175795A (ja) * | 2013-06-12 | 2013-09-05 | Mitsui High Tec Inc | リードフレームの製造方法 |
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JP2995119B2 (ja) * | 1992-02-17 | 1999-12-27 | アピックヤマダ株式会社 | パワートランジスタ用リードフレームの製造方法 |
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JP5089184B2 (ja) * | 2007-01-30 | 2012-12-05 | ローム株式会社 | 樹脂封止型半導体装置およびその製造方法 |
US20130069955A1 (en) * | 2009-05-29 | 2013-03-21 | David Tristram | Hierarchical Representation of Time |
JP5876669B2 (ja) * | 2010-08-09 | 2016-03-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6092645B2 (ja) * | 2013-02-07 | 2017-03-08 | エスアイアイ・セミコンダクタ株式会社 | 半導体装置 |
US9620438B2 (en) * | 2014-02-14 | 2017-04-11 | Stmicroelectronics (Malta) Ltd | Electronic device with heat dissipater |
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JPH04199664A (ja) * | 1990-11-29 | 1992-07-20 | Seiko Epson Corp | 半導体装置 |
JPH06302736A (ja) * | 1993-04-14 | 1994-10-28 | Nec Corp | 半導体装置用リードフレームの製造方法および半導体装置 |
JP2013069955A (ja) * | 2011-09-26 | 2013-04-18 | Renesas Electronics Corp | 半導体装置、半導体装置の製造方法およびリードフレーム |
JP2013175795A (ja) * | 2013-06-12 | 2013-09-05 | Mitsui High Tec Inc | リードフレームの製造方法 |
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