JP6100612B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP6100612B2 JP6100612B2 JP2013111360A JP2013111360A JP6100612B2 JP 6100612 B2 JP6100612 B2 JP 6100612B2 JP 2013111360 A JP2013111360 A JP 2013111360A JP 2013111360 A JP2013111360 A JP 2013111360A JP 6100612 B2 JP6100612 B2 JP 6100612B2
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Description
本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクション等に分けて記載するが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、記載の前後を問わず、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しの説明を省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
以下の実施の形態で説明する技術はリードを封止体の下面側で露出させる種々のパッケージタイプの半導体装置に適用可能である。本実施の形態では、一例として、外部端子である複数のリードが、封止体の下面(実装面)において封止体から露出する、QFN(Quad Flat Non-leaded package)型の半導体装置に適用した実施態様を取り上げて説明する。図1は本実施の形態の半導体装置の上面図、図2は、図1に示す半導体装置の実装面側を示す下面図、図3は図1のA−A線に沿った断面図である。また、図4は、図1に示す封止体を透視した状態で半導体装置の内部構造を示す透視平面図である。
まず、本実施の形態の半導体装置1の構成の概要について、図1〜図4を用いて説明する。本実施の形態の半導体装置1は、ダイパッド(チップ搭載部、タブ)2(図2〜図4参照)と、ダイパッド2上に接着材7(図3、図4参照)を介して搭載された半導体チップ3(図3、図4参照)と、を備えている。また、半導体装置1は、半導体チップ3(ダイパッド2)の周囲に配置された複数のリード(端子、外部端子)4と、半導体チップ3の複数のパッド(電極、ボンディングパッド)PD(図4参照)と複数のリード4とを、それぞれ電気的に接続する複数のワイヤ(導電性部材)5(図4参照)と、を有している。また、ダイパッド2には、複数の吊りリードTLが接続されている。また、半導体装置1は半導体チップ3、複数のワイヤ5、および複数のリード4の一部を封止する封止体(樹脂体)6を備えている。
まず、半導体装置1の外観構造について説明する。図1に示す封止体(樹脂体)6の平面形状は四角形からなる。封止体6は上面6aと、この上面6aとは反対側の下面(裏面、実装面)6b(図2参照)と、この上面6aと下面6bとの間に位置する側面6cとを有している。側面6cは、図3に示すように、上面6aおよび下面6bに対して直交しない、傾斜面となっている。
次に半導体装置1の内部構造について説明する。図4に示すように、ダイパッド2の上面(チップ搭載面)2aは、平面形状が四角形(四辺形)からなる。本実施の形態では、例えば正方形である。また、図4に示す例では、半導体チップ3の外形サイズ(裏面3bの平面サイズ)よりも、ダイパッド2の外形サイズ(平面サイズ)の方が大きい。このように半導体チップ3を、その外形サイズよりも大きい面積を有するダイパッド2に搭載し、ダイパッド2の下面2bを封止体6から露出させることで、放熱性を向上させることができる。
次に、図1〜図4に示す半導体装置1の製造工程について、説明する。本実施の形態における半導体装置1は、図5に示す組立てフローに沿って製造される。図5は、図1〜図4に示す半導体装置の組み立てフローを示す説明図である。
まず、図5に示す基材準備工程として、図6に示すようなリードフレーム(基材)LFを準備する。図6は、図5に示す基材準備工程で準備するリードフレームの全体構造を示す平面図、図7は、図6に示す複数のデバイス形成部のうちの一つの拡大平面図である。
次に、図5に示す半導体チップ搭載工程として、図8および図9に示すように半導体チップ3を、ダイパッド2上に接着材7を介して搭載する。図8は、図7に示すダイパッド上に、ボンディング材を介して半導体チップを搭載した状態を示す拡大平面図、図9は、図8のA−A線に沿った拡大断面図である。
次に、図5に示すワイヤボンディング工程として、図10および図11に示すように、半導体チップ3の複数のパッドPDと複数のリード4とを、複数のワイヤ(導電性部材)5を介して、それぞれ電気的に接続する。図10は、図8に示す半導体チップと複数のリードを、ワイヤを介して電気的に接続した状態を示す拡大平面図、図11は、図10のA−A線に沿った拡大断面図である。
次に、図5に示す封止工程として、図12および図13に示すように、封止体6を形成し、半導体チップ3(図13参照)、複数のワイヤ5(図13参照)、および複数のリード4(図13参照)のそれぞれ一部を樹脂で封止する。図12は、図10に示すリードフレームのデバイス形成部に、封止体を形成した状態を示す平面図、図13は図12のA−A線に沿った拡大断面図である。また、図14は、図5に示す封止工程において、成形金型内にリードフレームを配置した状態を示す断面図である。また、図15は、図12に示すA−A線に沿った断面において、成形金型でリードフレームを挟んだ状態を示す拡大断面図である。また、図16は、図12に示す封止体が形成された後のリードフレームの全体構造の例を示す平面図である。また、図17は、図12に示すリードフレームの反対面側を示す拡大平面図である。なお、図16では、図13および図14に示す成形金型に樹脂を供給されることにより形成された封止部(樹脂体)を示しているが、成形金型50の平面形状を判り易く説明するため、各封止部の符号と伴に、成形金型の構成部分の符号を付している。
次に、図5に示すゲートブレイク工程として、図17に示す主ランナ封止部6rmおよび副ランナ封止部6rsをリードフレームLFから分離させる。図18は、図12に示す主ランナ封止部および副ランナ封止部を取り除いた状態を示す拡大平面図である。また、図19は、図18に示すA−A線に沿った断面において、リードフレームの下面側からピンを挿入し、主ランナ封止部および副ランナ封止部を押し出した状態を示す拡大断面図である。また、図20は、図18に示す副ランナ部の周辺の拡大平面図である。また、図24は、図18に対する比較例を示す拡大平面図である。また、図25は、図24に示すA−A線に沿った断面において、リードフレームの下面側からピンを挿入し、主ランナ封止部および副ランナ封止部を押し出した状態を示す拡大断面図である。
次に、図5に示すベーク工程として、図21に示すように、成形金型から取り出したリードフレームLFをベーク炉BKに搬送し、リードフレームLFに加熱処理を施す。図21は、図18に示すリードフレームを積み重ね、ベーク炉に搬入する状態を模式的に示す説明図である。上記封止工程においてキャビティ内に供給された樹脂は、硬化してはいるものの、樹脂が完全に硬化しきっていない状態である。これは、次に成形金型50(図14参照)に搬送される次のリードフレームLFに対して、いち早くモールド工程を施すためである。そのため、本実施の形態では、樹脂を硬化させる工程を、2回に分けている。そして、本ベーク工程において、上記封止工程で形成された封止体6に含まれる効果成分を、完全に硬化(本硬化)させる。
次に、図5に示す樹脂除去工程として、図18に示すダム内樹脂部6dmを取り除く。図22は、図18に示すダム内樹脂部、ゲート内樹脂部、および副ランナ封止部の残存部分を除去した状態を示す拡大平面図である。
次に、図5に示すめっき工程として、図22に示す複数のリード4のデバイス封止部6mbからの露出面に、金属膜SD(図3参照)を形成する。本工程では、例えば、電解めっき法により、樹脂から露出した金属部材の表面に、例えば半田からなる金属膜SD(図3参照)を形成する。
次に、図5に示す個片化工程として、図23に示すように、複数のリード4および吊りリードTLが連結されている枠部LFsを切断し、複数のデバイス形成部LFdを、それぞれ個片に分割する。図23は、図5に示す個片化工程において、デバイス形成部毎に個片化した状態を示す拡大平面図である。
以上、本願発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は上記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。
例えば、上記実施の形態では、平面視において四角形からなる封止体6の四つの主辺において、複数のリード4の一部が外側に向かってわずかに(0.3mm程度)突出したタイプのQFNについて説明した。しかし、変形例として、例えば図1に示すリード4の封止体6からの突出部分を切断しても良い。また他の変形例として、封止体6から突出したリード4の長さをさらに長くして、実装面に向かって曲げ加工を施すことにより、所謂、QFP(Quad Flat Package)型の半導体装置に適用することもできる。
また例えば、上記実施の形態では、封止工程において、リードフレームLFと下型52の間に、樹脂フィルム53を介在させる封止方式について説明した。しかし、変形例としては、樹脂フィルム53を介在させず、リードフレームLFと下型52とを接触させる方式で封止することもできる。
また例えば、上記実施の形態では、図5に示すフレーム積層工程やフレーム積層解除工程において、リードフレームLFを搬送する装置の保持方法として、図21に示すように複数のデバイス封止部6mbのそれぞれに吸着保持部CDbを接触させて吸着保持する方法について説明した。しかし変形例として、例えば図1に示すリードフレームLFの外枠LFfの側面を図示しない保持治具(チャック)で挟んで保持する方法を適用することができる。このような保持方法の場合であっても、リードフレームLFが傾いている場合には、確実に保持する事が難しい。しかし、上記実施の形態で説明した技術を適用すれば、複数のリードフレームLFを積み重ねた時に、各リードフレームLFが傾き難くなる。このため、上記変形例を適用した場合でもリードフレームを確実に保持することができる。
また例えば、上記実施の形態では、フレーム積層工程とフレーム積層解除工程を、代表例としてベーク工程の前後に記載しているが、ベーク工程以外の工程でフレーム積層工程とフレーム積層解除工程を行うこともできる。
さらに、上記実施の形態で説明した技術思想の要旨を逸脱しない範囲内において、変形例同士を組み合わせて適用することができる。
2 ダイパッド(チップ搭載部、タブ)
2a 上面(チップ搭載面)
2b 下面
3 半導体チップ
3a 表面(主面、上面)
3b 裏面(主面、下面)
3c 側面
4 リード(端子、外部端子)
4a 上面
4b 下面
4i インナ部
4o アウタ部
5 ワイヤ(導電性部材)
6 封止体(樹脂体)
6a 上面
6b 下面(裏面、実装面)
6c 側面
6cl カル封止部(樹脂供給部)
6dm ダム内樹脂部
6g ゲート内樹脂部
6mb デバイス封止部(本体部)
6p 角部
6rm 主ランナ封止部
6rs 副ランナ封止部
6sp スペーサ樹脂部
6vt ベント内樹脂部
7 接着材
11 露出部(フィン、コーナリード)
50 成形金型
50cl カル
51 上型(金型)
51a クランプ面(金型面、押し付け面、面)
51b キャビティ(窪み部)
51rm 主ランナ
51rs 副ランナ
52 下型(金型)
52a クランプ面(金型面、押し付け面、面)
53 樹脂フィルム(フィルム材)
BK ベーク炉
CD 搬送装置
CDb 吸着保持部
CDc 搬送機構部
Cp 屈曲点
HS ヒートステージ(リードフレーム加熱台)
HSa 搭載面
Ldm ダム部
LF リードフレーム(基材)
LFa 上面
LFb 下面
LFd デバイス形成部(デバイス領域、製品形成部、製品領域)
LFf 外枠
Lfr 領域
LFs 枠部
Lg ゲート部
Lrm 主ランナ部
Lrs 副ランナ部
PD パッド(電極、ボンディングパッド)
PN ピン(ディゲートピン)
PNt 先端面(押し出し面)
S1、S2 辺
SD 金属膜
THh、THs 副貫通孔
THm 主貫通孔
THs1、THs2 部分
TL 吊りリード
Tw1、Tw2、Tw3 開口幅
XY1、XY2 方向
Claims (15)
- 以下の工程を含む半導体装置の製造方法:
(a)第1面と、前記第1面の反対側の第2面と、前記第1面の第1領域および前記第2面の第1領域を有するデバイス形成部と、前記第1面の第2領域および前記第2面の第2領域を有し、かつ平面視において前記デバイス形成部の周囲に設けられた枠部と、第1方向に沿って前記枠部における前記第1面に設けられた主ランナ部と、前記デバイス形成部に連結されたゲート部と、前記ゲート部と前記主ランナ部とを連結するように前記枠部の前記第1面に設けられた副ランナ部と、前記主ランナ部において前記第1面および前記第2面のうちの一方から他方に向かって形成された主貫通孔と、前記副ランナ部において前記第1面および前記第2面のうちの一方から他方に向かって形成された副貫通孔と、を備えたリードフレームを準備する工程;
ここで、
前記副貫通孔は、平面視において、前記副ランナ部が延びる第2方向に沿って、前記主ランナ部側に位置する第1部分と、前記第1部分よりも前記ゲート部側に位置する第2部分と、を有し、
平面視において、前記第2方向における前記副貫通孔の最大開口幅は、前記第2方向と直交する第3方向における前記副貫通孔の最大開口幅よりも大きく、
平面視において、前記第3方向における前記副貫通孔の開口幅は、前記第1部分から前記第2部分のうちの前記ゲート部側の端部に向かって徐々に小さくなっており、
前記副貫通孔の前記第2部分の前記ゲート部側の端部は、平面視において、直線的に形成されており、
(b)前記(a)工程の後、前記デバイス形成部に半導体チップを配置する工程;
(c)前記(b)工程の後、前記主ランナ部を覆う成型金型の主ランナ、前記副ランナ部を覆う前記成型金型の副ランナおよび前記リードフレームの前記ゲート部を介して、前記デバイス形成部の前記半導体チップを覆う前記成型金型のキャビティ内に樹脂を供給することにより、前記デバイス形成部に前記半導体チップを封止するデバイス封止部、前記主ランナ部に主ランナ封止部、および前記副ランナ部に副ランナ封止部をそれぞれ形成する工程;
(d)前記(c)工程の後、前記リードフレームの前記第2面側から前記主貫通孔および前記副貫通孔のそれぞれに、その先端面の平面形状が円形から成る円柱形のピンを挿入し、前記主ランナ封止部および前記副ランナ封止部を前記リードフレームから分離させる工程。 - 請求項1において、
前記(d)工程の後、前記(d)工程まで施した複数の前記リードフレームを積み重ねた状態で、複数の前記リードフレームに加熱処理を施す、半導体装置の製造方法。 - 請求項2において、
前記リードフレームに加熱処理を施した後、複数の前記リードフレームが積み重ねられた積層体から、個々の前記リードフレームを、保持治具を用いて順番に取り出す、半導体装置の製造方法。 - 請求項3において、
前記(c)工程では、前記デバイス封止部の周囲にスペーサ樹脂部が形成され、
前記スペーサ樹脂部の厚さは、前記デバイス封止部の厚さよりも大きく、かつ、前記副ランナ封止部の厚さよりも小さい、半導体装置の製造方法。 - 請求項4において、
前記(d)工程では、前記主ランナ封止部および前記副ランナ封止部を前記リードフレームから分離させた後に、前記副ランナ封止部の一部が前記リードフレームの前記第1面上に残留しており、
前記副ランナ封止部の残留した部分の厚さは、前記スペーサ樹脂部の厚さよりも小さい、半導体装置の製造方法。 - 請求項1において、
前記副貫通孔の前記第1部分の前記主ランナ部側の周縁部は、平面視において、前記主ランナ部に近づくように湾曲した形状となっている、半導体装置の製造方法。 - 請求項1において、
前記(c)工程では、前記リードフレームの前記第2面と前記成型金型の間に樹脂フィルムを介在させた状態で、前記副ランナ封止部を形成する、半導体装置の製造方法。 - 請求項1において、
前記(d)工程の後、前記デバイス封止部の周囲にレーザを照射して、前記デバイス封止部から露出する複数のリードの間に埋め込まれたダム内樹脂部を除去する、半導体装置の製造方法。 - 以下の工程を含む半導体装置の製造方法:
(a)第1面と、前記第1面の反対側の第2面と、前記第1面の第1領域および前記第2面の第1領域を有し、第1方向に沿って設けられた複数のデバイス形成部と、前記第1面の第2領域および前記第2面の第2領域を有し、平面視において前記複数のデバイス形成部それぞれの周囲に設けられた枠部と、前記第1方向に沿って前記枠部の前記第1面に設けられた主ランナ部と、前記複数のデバイス形成部のうちの第1デバイス形成部に連結された第1ゲート部と、前記第1ゲート部と前記主ランナ部とを連結するように前記枠部の前記第1面に設けられた第1副ランナ部と、前記主ランナ部において前記第1面および前記第2面のうちの一方から他方に向かって形成された主貫通孔と、前記第1副ランナ部において前記第1面および前記第2面のうちの一方から他方に向かって形成された第1副貫通孔と、前記複数のデバイス形成部のうちの第2デバイス形成部に連結された第2ゲート部と、前記第2ゲート部と前記主ランナ部とを連結するように前記枠部の前記第1面に設けられた第2副ランナ部と、前記第2副ランナ部において前記第1面および前記第2面のうちの一方から他方に向かって形成された第2副貫通孔と、を備えたリードフレームを準備する工程;
ここで、
前記第1副貫通孔は、平面視において、前記第1副ランナ部が延びる第2方向に沿って、前記主ランナ部側に位置する第1部分と、前記第1部分よりも前記ゲート部側に位置する第2部分と、を有し、
前記第2副貫通孔は、平面視において、前記第2副ランナ部が延びる前記第2方向に沿って、前記主ランナ部側に位置する第3部分と、前記第3部分よりも前記ゲート部側に位置する第4部分と、を有し、
平面視において、前記第2方向における前記第1および第2副貫通孔の最大開口幅は、前記第2方向と直交する第3方向における前記第1および第2副貫通孔の最大開口幅よりも大きく、
平面視において、前記第3方向における前記第1および第2副貫通孔の開口幅は、前記第1または第3部分から前記第2または第4部分のうちの前記第1または第2ゲート部側の端部に向かって徐々に小さくなっており、
前記第1副貫通孔の前記第2部分の前記ゲート部側の端部は、平面視において、直線的に形成されており、
前記第2副貫通孔の前記第4部分の前記ゲート部側の端部は、平面視において、直線的に形成されており、
(b)前記(a)工程の後、前記複数のデバイス形成部に複数の半導体チップをそれぞれ配置する工程;
(c)前記(b)工程の後、前記主ランナ部を覆う成型金型の主ランナ、前記第1副ランナ部を覆う前記成型金型の第1副ランナおよび前記リードフレームの前記第1ゲート部を介して、前記第1デバイス形成部の第1半導体チップを覆う前記成型金型の第1キャビティ内に樹脂を供給し、前記主ランナ、前記第2副ランナ部を覆う前記成型金型の第2副ランナおよび前記リードフレームの前記第2ゲート部を介して、前記第2デバイス形成部の第2半導体チップを覆う前記成型金型の第2キャビティ内に樹脂を供給することにより、前記複数のデバイス形成部に前記複数の半導体チップを封止する複数のデバイス封止部、前記主ランナ部に主ランナ封止部、前記第1副ランナ部に第1副ランナ封止部、および前記第2副ランナ部に第2副ランナ封止部をそれぞれ形成する工程;
(d)前記(c)工程の後、前記リードフレームの前記第2面側から前記主貫通孔、前記第1副貫通孔、および前記第2副貫通孔のそれぞれに、その先端面の平面形状が円形から成る円柱形のピンを挿入し、前記主ランナ封止部、前記第1副ランナ封止部、および前記第2副ランナ封止部を前記リードフレームから分離させる工程。 - 請求項9において、
前記(d)工程の後、前記(d)工程まで施した複数の前記リードフレームを積み重ねた状態で、複数の前記リードフレームに加熱処理を施す、半導体装置の製造方法。 - 請求項10において、
前記リードフレームに加熱処理を施した後、複数の前記リードフレームが積み重ねられた積層体から、個々の前記リードフレームを、保持治具を用いて順番に取り出す、半導体装置の製造方法。 - 請求項11において、
前記(c)工程では、前記複数のデバイス封止部の間に複数のスペーサ樹脂部が形成され、
前記複数のスペーサ樹脂部の厚さは、前記複数のデバイス封止部の厚さよりも大きく、かつ、前記第1および第2副ランナ封止部の厚さよりも小さい、半導体装置の製造方法。 - 請求項12において、
前記(d)工程では、前記主ランナ封止部、および前記第1副ランナ封止部を前記リードフレームから分離させた後に、前記第1副ランナ封止部の一部が前記リードフレームの前記第1面上に残留しており、
前記第1副ランナ封止部の残留した部分の厚さは、前記複数のスペーサ樹脂部の厚さよりも小さい、半導体装置の製造方法。 - 請求項9において、
前記第1副貫通孔の前記第1部分の前記主ランナ部側の周縁部は、平面視において、前記主ランナ部に近づくように湾曲した形状となっており、
前記第2副貫通孔の前記第3部分の前記主ランナ部側の周縁部は、平面視において、前記主ランナ部に近づくように湾曲した形状となっている、半導体装置の製造方法。 - 請求項9において、
前記(d)工程では、前記第1副ランナ封止部に前記ピンを挿入して前記第1副ランナ封止部と前記リードフレームとを剥離させた後、前記第2副ランナ封止部に前記ピンを挿入して前記第2副ランナ封止部と前記リードフレームとを剥離させる、半導体装置の製造方法。
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