JP6129645B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP6129645B2 JP6129645B2 JP2013113337A JP2013113337A JP6129645B2 JP 6129645 B2 JP6129645 B2 JP 6129645B2 JP 2013113337 A JP2013113337 A JP 2013113337A JP 2013113337 A JP2013113337 A JP 2013113337A JP 6129645 B2 JP6129645 B2 JP 6129645B2
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- die pad
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Description
本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクション等に分けて記載するが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、記載の前後を問わず、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しの説明を省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
まず、本実施の形態の半導体装置1の構成の概要について、図1〜図5を用いて説明する。本実施の形態の半導体装置1は、ダイパッド(チップ搭載部、タブ)10(図3〜図5参照)と、ダイパッド10上にダイボンド材(接着材)8(図3〜図5参照)を介して搭載された半導体チップ3(図3〜図5参照)と、を備えている。また、半導体装置1は、半導体チップ3(ダイパッド10)の隣(周囲)に配置された複数のリード(端子、外部端子)4と、半導体チップ3の複数のパッド(電極、ボンディングパッド)PD(図3、図4参照)と複数のリード4とをそれぞれ電気的に接続する複数のワイヤ(導電性部材)5(図3、図4参照)と、を有している。また、半導体装置1は半導体チップ3および複数のワイヤ5を封止する封止体(樹脂体)7を備えている。また、ダイパッド10には、複数の吊りリード9が接続されている。
まず、半導体装置1の外観構造について説明する。図1に示す封止体(樹脂体)7の平面形状は四角形である。詳細には、各角部が面取り加工されており、これにより封止体7の欠けを抑制している。封止体7は上面7aと、この上面7aとは反対側の下面(裏面、実装面)7b(図2参照)と、この上面7aと下面7bとの間に位置する側面7cとを有している。側面7cは、図4に示すように傾斜面となっている。封止体7の角部とは、封止体7の四辺(四つの主辺)のうち、交差する任意の二辺(二つの主辺)の交点である角の周辺領域を含んでいる。なお、厳密には、図1に示すように、封止体7の角部は、一部が面取り加工されているので、主辺の交点は封止体7の角部よりも外側に配置される。しかし、面取り加工部は、主辺の長さと比較して十分に小さいため、本願では、面取り加工部の中心を封止体7の角と見做して説明する。つまり、本願においては、封止体7の四辺(四つの主辺)のうち、任意の二辺(二つの主辺)が交差する領域であって、該領域が面取り加工されている場合にはその面取り加工部が角部に相当し、該領域が面取り加工されていない場合には、任意の二辺(二つの主辺)の交点が角部に相当する。以下、本願において、封止体7の角部と説明するときは、特に異なる意味、内容で用いている旨を明記した場合を除き、上記と同様の意味、内容として用いる。
次に、半導体装置1の内部構造について説明する。図3に示すように、ダイパッド10の上面(チップ搭載面)10aは、平面形状が四角形(四辺形)から成る。また、本実施の形態では、半導体チップ3の外形サイズ(図4に示す裏面3bの平面サイズ)よりも、ダイパッド10の外形サイズ(平面サイズ)の方が大きい。このように半導体チップ3を、その外形サイズよりも大きい面積を有するダイパッド10に搭載し、図2に示すようにダイパッド10の下面10bを封止体7から露出させることで、放熱性を向上させることができる。ダイパッド10のその他の詳細な構造は後述する。
次に、図2〜図4に示すダイパッド10の詳細な構造と、その構造とすることにより得られる効果について説明する。図6は、図3に示すダイパッドを拡大して示す拡大平面図である。また、図7は、図6のA−A線に沿った拡大断面図である。また、図8は、図3のC部の拡大平面図、図9は、図8のA−A線に沿った拡大断面図である。なお、図6では、中央部11と周縁部12の境界を判り易く示すため、周縁部12にドットパターンを付して示している。また、図9では、ワイヤ5の一部(ワイヤ5a)がリード4に接続され、ワイヤ5の他の一部(ワイヤ5b)がダイパッド10に接続されることを明示するため、ワイヤ5aを点線で、ワイヤ5bを実線で示している。
次に、図1〜図9を用いて説明した半導体装置1の製造工程について、説明する。本実施の形態における半導体装置1は、図11に示す組立てフローに沿って製造される。図11は、図1〜図9に示す半導体装置の組み立てフローを示す説明図である。
まず、図11に示すリードフレーム準備工程として、図12に示すようなリードフレーム20を準備する。図12は、図11のリードフレーム準備工程で準備するリードフレームの全体構造を示す平面図、図13は、図12に示す複数の製品形成部のうちの一部の拡大平面図である。また、図14は、図11に示す段差面形成工程で段差面を形成する直前の状態を示す拡大断面図である。また、図15は、図14に示すダイパッドにプレス加工を施して段差面を形成した状態を示す拡大断面図である。また、図16は、図13に示すリードフレームのリードの延在方向に沿った拡大断面図である。また、図17は、図13に示すリードフレームの吊りリードの延在方向に沿った拡大断面図である。
次に、図11に示す半導体チップ搭載工程として、図18および図19に示すように半導体チップ3を、ダイパッド10上にダイボンド材8を介して搭載する。図18は、図13に示すダイパッド上に、ボンディング材を介して半導体チップを搭載した状態を示す拡大平面図、図19は、図16に示すダイパッド上に、ボンディング材を介して半導体チップを搭載した状態を示す拡大断面図である。
次に、図11に示すワイヤボンディング工程として、図20および図21に示すように、半導体チップ3の複数のパッドPDと複数のリード4とを、複数のワイヤ(導電性部材)5aを介して、それぞれ電気的に接続する。また、本工程では、ワイヤ5bを介して半導体チップ3とダイパッド10を電気的に接続する。図20は、図18に示す半導体チップと、複数のリードおよびダイパッドを、ワイヤを介して電気的に接続した状態を示す拡大平面図、図21は、図19に示す半導体チップと複数のリードを、ワイヤを介して電気的に接続した状態を示す拡大断面図である。また、図22は、図21のダイパッドのワイヤ接続領域周辺を拡大して示す拡大断面図である。
次に、図11に示す封止工程(封止体形成工程)として、図23および図24に示すように、封止体(樹脂体)7を形成し、半導体チップ3(図24参照)、複数のワイヤ5(図24参照)、リード4のインナリード部4a、およびダイパッド10(図24参照)の上面10a(図24参照)を封止する。図23は、図20に示すリードフレームの製品形成部に、封止体を形成した状態を示す拡大平面図、図24は図21に示すリードフレームの製品形成部に、封止体を形成した状態を示す拡大断面図である。また、図25は、図24の一部を拡大した断面において、封止用の樹脂の流れを模式的に示す説明図である。
次に、図11に示す外装めっき工程として、図26に示すように封止体7から露出する複数のリード4の露出面(アウタリード部4b)に金属膜(外装めっき膜、半田膜)SDを形成する。図26は、図24に示す封止体から露出する複数のリードおよびダイパッドの露出面に金属膜(外装めっき膜、半田膜)を形成した状態を示す拡大断面図である。
次に、リード成形工程として、リードフレーム20の枠部20cに連結された複数のリード4の連結部を切断した後、リード4に曲げ加工を施して成形する。図27は、図11に示す外装めっき工程で金属膜を形成した複数のリードを、リードフレームの枠部から切断し、成形した状態を示す拡大平面図である。なお、図23に対する断面図は、図4と同様なので図示は省略する。また、図27は、図11に示す個片化工程が完了した状態を示しており、図23に示す吊りリード9も切断されている。
次に、図11に示す個片化工程として、図27に示すように、枠部20cに連結されている複数の吊りリード9(図23参照)を切断し、製品形成部20a毎に個片化して複数の半導体装置1を取得する。
以上、本願発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。
3 半導体チップ
3a 表面(主面、上面)
3b 裏面(主面、下面)
4 リード(端子、外部端子)
4a インナリード部
4b アウタリード部
5、5a、5b ワイヤ(導電性部材)
7 封止体(樹脂体)
7a 上面
7b 下面(裏面、実装面)
7c 側面
7f フィラ粒子
7p 樹脂
8 ダイボンド材(接着材)
9 吊りリード
9a 傾斜部
10、10H1 ダイパッド(チップ搭載部、タブ)
10a 上面(チップ搭載面)
10b 下面(実装面)
10c 側面
10d チップ搭載領域
10wb ワイヤ接続領域(ワイヤボンディング領域)
11 中央部(部分)
11a 上面
11b 下面
12 周縁部(部分)
12 チップ接続部
12a 上面
12b 下面
12j 連結部
13 段差部
13a、13b 段差面
13H1 折り曲げ部
13H1a 傾斜面
13j 連結部
14 金属膜
15 スリット
20 リードフレーム
20a 製品形成部
20b 外枠
20c 枠部(ダム部)
21 タイバー(ダム部)
31、32 治具(せん断治具)
31、32 治具
31a 上治具
31b 下治具
32a 上治具
32b 下治具
35 成形金型
36 上型(第1金型)
36a 金型面(第1金型面)
36b キャビティ(凹部)
37 下型(第2金型)
37a 金型面(第2金型面)
37b キャビティ(凹部)
CP キャピラリ
Cu 銅
HS ヒートステージ(加熱台)
HSa ダイパッド保持面
HSb リード保持面
HSc 周縁部保持面
HT ヒータ(熱源)
PD パッド(電極、ボンディングパッド)
SD 金属膜(外装めっき膜、半田膜)
Claims (20)
- 第1面、前記第1面の反対側に位置する第2面を有するダイパッドと、
前記ダイパッドの隣に配置される複数のリードと、
表面、前記表面に形成された複数の電極、および前記表面の反対側に位置する裏面を有し、前記ダイパッドの前記第1面のチップ搭載領域上に、前記裏面の全体が前記第1面と対向した状態で搭載される半導体チップと、
前記半導体チップの前記複数の電極の一部と前記複数のリードを電気的に接続する複数の第1ワイヤと、
前記半導体チップの前記複数の電極の他部と前記ダイパッドを電気的に接続する第2ワイヤと、
前記複数のリードの一部および前記ダイパッドの前記第2面が露出するように、前記半導体チップ、前記複数の第1ワイヤおよび前記第2ワイヤを封止する封止体と、
を有し、
前記ダイパッドは、
前記チップ搭載領域を含み、前記第1面と同じ方向を向く第3面、および前記第3面の反対側に位置する第4面を有する第1部分と、
前記第1面と同じ方向を向く第5面および前記第5面の反対側に位置する第6面を有し、平面視において、前記第1部分を囲むように設けられている第2部分と、
前記第1面において、前記第1部分の前記第3面と、前記第2部分の前記第5面との間に設けられた第1段差面と、
前記第2面において、前記第1部分の前記第4面と、前記第2部分の前記第6面との間で、かつ、前記ダイパッドの厚さ方向において、前記第1段差面の延長上に設けられた第2段差面と、
前記第1段差面と前記第2段差面の間に位置し、前記ダイパッドの前記第1部分と前記第2部分とを連結する連結部と、
を備え、
前記第2ワイヤは、前記第2部分の前記第5面に設けられたワイヤ接続領域に接続され、
前記第2部分の前記第5面は、前記第1部分の前記第3面よりも高い位置に配置され、
前記ダイパッドの厚さ方向において、前記連結部の厚さは、前記第2部分の前記第5面と前記第1部分の前記第3面の高低差、および前記第2部分の前記第6面と前記第1部分の前記第4面の高低差、のそれぞれより大きく、
前記第1段差面および前記第2段差面のそれぞれは、前記第1部分と前記第2部分の境界において前記ダイパッドの一部分が、せん断された、せん断面である、半導体装置。 - 請求項1において、
前記第1段差面は、前記第1部分の前記第3面の周囲を連続的に囲むように形成されている、半導体装置。 - 請求項2において、
前記第2部分の前記第6面は、前記第1部分の前記第4面よりも高い位置に配置され、かつ、前記封止体に覆われている、半導体装置。 - 請求項3において、
前記第2部分の前記ワイヤ接続領域と、前記第1段差面の間には、前記第5面および前記第6面のうち、一方から他方までを貫通するようにスリットが形成されている、半導体装置。 - 請求項4において、
前記第2部分の幅は、前記ダイパッドの厚さよりも大きい、半導体装置。 - 請求項4において、
前記第1段差面の高さは、前記ダイパッドの厚さの半分以下である、半導体装置。 - 請求項4において、
前記封止体には、複数のフィラ粒子が含まれている、半導体装置。 - 請求項1において、
前記第1段差面と前記第1部分の前記第3面とが成す角は、直角、あるいは、直角よりも小さい鋭角に形成されている、半導体装置。 - 請求項1において、
前記ダイパッドの厚さ方向において、前記連結部の厚さは、前記第1部分の厚さに対して1/2以上、かつ2/3以下である、半導体装置。 - 請求項1において、
前記第2段差面および前記第2部分の前記第6面は、前記封止体に覆われている、半導体装置。 - (a)第1面、前記第1面の反対側に位置する第2面を有するダイパッドと、前記ダイパッドの隣に配置される複数のリードと、を備えるリードフレームを準備する工程;
(b)表面、前記表面に形成された複数の電極、および前記表面の反対側に位置する裏面を有する半導体チップを、前記裏面の全体が前記第1面と対向するように前記ダイパッドの前記第1面のチップ搭載領域上に搭載する工程;
(c)前記(b)工程の後、前記半導体チップの前記複数の電極の一部と前記複数のリードを複数の第1ワイヤを介して電気的に接続し、前記複数の電極の他部と前記ダイパッドとを、第2ワイヤを介して電気的に接続する工程;
(d)前記(c)工程の後、前記複数のリードの一部および前記ダイパッドの前記第2面が露出するように、前記半導体チップ、前記複数の第1ワイヤおよび前記第2ワイヤを樹脂で封止する工程;
を有し、
前記(a)工程で準備する前記リードフレームの前記ダイパッドは、
前記チップ搭載領域を含み、前記第1面と同じ方向を向く第3面、および前記第3面の反対側に位置する第4面を有する第1部分と、
前記第1面と同じ方向を向き、前記第1部分の前記第3面よりも高い位置に配置されている第5面、および前記第5面の反対側に位置する第6面を有し、平面視において、前記第1部分を囲むように設けられている第2部分と、
前記第1面において、前記第1部分の前記第3面と、前記第2部分の前記第5面との間に設けられた第1段差面と、
前記第2面において、前記第1部分の前記第4面と、前記第2部分の前記第6面との間で、かつ、前記ダイパッドの厚さ方向において、前記第1段差面の延長上に設けられた第2段差面と、
前記第1段差面と前記第2段差面の間に位置し、前記ダイパッドの前記第1部分と前記第2部分とを連結する連結部と、
を備えており、
前記ダイパッドの厚さ方向において、前記連結部の厚さは、前記第2部分の前記第5面と前記第1部分の前記第3面の高低差、および前記第2部分の前記第6面と前記第1部分の前記第4面の高低差、のそれぞれより大きく、
前記第1段差面および前記第2段差面のそれぞれは、前記第1部分と前記第2部分の境界において前記ダイパッドの一部分が、せん断されることにより形成されたせん断面であって、
前記(c)工程で、前記第2ワイヤは、前記第2部分の前記第5面に設けられたワイヤ接続領域に接続される、半導体装置の製造方法。 - 請求項11において、
前記第1段差面は、前記第1部分の前記第3面の周囲を連続的に囲むように形成されている、半導体装置の製造方法。 - 請求項12において、
前記第2部分の前記第6面は、前記第1部分の前記第4面よりも高い位置に配置され、
前記(d)工程では、前記第2部分の前記第6面を前記樹脂で覆うように封止する、半導体装置の製造方法。 - 請求項13において、
前記第2部分の前記ワイヤ接続領域と、前記第1段差面の間には、前記第5面および前記第6面のうち、一方から他方までを貫通するようにスリットが形成されている、半導体装置の製造方法。 - 請求項14において、
前記(d)工程では、成形金型内に前記リードフレームを配置した状態で、軟化した前記樹脂を圧入した後、硬化させる、半導体装置の製造方法。 - 請求項15において、
前記第2部分の幅は、前記ダイパッドの厚さよりも大きい、半導体装置の製造方法。 - 請求項15において、
前記第1段差面の高さは、前記ダイパッドの厚さの半分以下である、半導体装置の製造方法。 - 請求項15において、
前記(d)工程で、前記半導体チップ、前記複数の第1ワイヤおよび前記第2ワイヤを封止する前記樹脂には、複数のフィラ粒子が含まれている、半導体装置の製造方法。 - 請求項11において、
前記ダイパッドの厚さ方向において、前記連結部の厚さは、前記第1部分の厚さに対して1/2以上、かつ2/3以下である、半導体装置の製造方法。 - 請求項11において、
前記第2段差面および前記第2部分の前記第6面は、前記(d)工程において前記樹脂で封止される、半導体装置の製造方法。
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JP6922674B2 (ja) * | 2017-11-09 | 2021-08-18 | トヨタ自動車株式会社 | 半導体装置 |
US10777489B2 (en) * | 2018-05-29 | 2020-09-15 | Katoh Electric Co., Ltd. | Semiconductor module |
JP7057727B2 (ja) * | 2018-07-12 | 2022-04-20 | 株式会社三井ハイテック | リードフレームおよび半導体装置 |
JP7134137B2 (ja) * | 2019-05-31 | 2022-09-09 | 三菱電機株式会社 | 半導体装置 |
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EP0895287A3 (en) * | 1997-07-31 | 2006-04-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and lead frame for the same |
US6831352B1 (en) * | 1998-10-22 | 2004-12-14 | Azimuth Industrial Company, Inc. | Semiconductor package for high frequency performance |
KR100335480B1 (ko) | 1999-08-24 | 2002-05-04 | 김덕중 | 칩 패드가 방열 통로로 사용되는 리드프레임 및 이를 포함하는반도체 패키지 |
JP4417541B2 (ja) | 2000-10-23 | 2010-02-17 | ローム株式会社 | 半導体装置およびその製造方法 |
JP3436253B2 (ja) * | 2001-03-01 | 2003-08-11 | 松下電器産業株式会社 | 樹脂封止型半導体装置およびその製造方法 |
JP2003142636A (ja) * | 2001-08-02 | 2003-05-16 | Nec Kyushu Ltd | 封止用樹脂、樹脂封止型半導体及びシステムインパッケージ |
TWI338358B (en) * | 2003-11-19 | 2011-03-01 | Rohm Co Ltd | Method of fabricating lead frame and method of fabricating semiconductor device using the same, and lead frame and semiconductor device using the same |
JP4511278B2 (ja) * | 2004-08-11 | 2010-07-28 | 三洋電機株式会社 | セラミックパッケージ |
JP4767277B2 (ja) | 2008-04-08 | 2011-09-07 | パナソニック株式会社 | リードフレームおよび樹脂封止型半導体装置 |
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- 2014-05-16 US US14/280,414 patent/US9368432B2/en active Active
- 2014-05-29 CN CN201410233734.4A patent/CN104218013B/zh active Active
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US11067288B2 (en) | 2017-05-15 | 2021-07-20 | Backer Ehp Inc. | Dual coil electric heating element |
US11098904B2 (en) | 2017-05-15 | 2021-08-24 | Backer Ehp Inc. | Dual coil electric heating element |
USD955168S1 (en) | 2019-07-03 | 2022-06-21 | Backer Ehp Inc. | Electric heating element |
US11581156B2 (en) | 2019-07-03 | 2023-02-14 | Backer Ehp Inc. | Dual coil electric heating element |
US11929220B2 (en) | 2019-07-03 | 2024-03-12 | Backer Ehp Inc. | Dual coil electric heating element |
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JP2014232811A (ja) | 2014-12-11 |
KR20140140486A (ko) | 2014-12-09 |
CN203932042U (zh) | 2014-11-05 |
HK1204506A1 (en) | 2015-11-20 |
CN104218013A (zh) | 2014-12-17 |
CN104218013B (zh) | 2018-11-23 |
US20140353809A1 (en) | 2014-12-04 |
US9368432B2 (en) | 2016-06-14 |
TW201507071A (zh) | 2015-02-16 |
TWI639214B (zh) | 2018-10-21 |
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