JP7134137B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7134137B2 JP7134137B2 JP2019102527A JP2019102527A JP7134137B2 JP 7134137 B2 JP7134137 B2 JP 7134137B2 JP 2019102527 A JP2019102527 A JP 2019102527A JP 2019102527 A JP2019102527 A JP 2019102527A JP 7134137 B2 JP7134137 B2 JP 7134137B2
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Description
図1は、実施の形態1における半導体装置の構成を示す下面図である。図2は、図1に示されるA-A’における断面図である。図3は、図1に示されるB-B’における断面図である。図4は、図1に示される半導体装置の結線の構成を示す結線図である。
実施の形態2における半導体装置を説明する。実施の形態2は実施の形態1の下位概念であり、実施の形態2における半導体装置は、実施の形態1における半導体装置の各構成を含む。なお、実施の形態1と同様の構成および動作については説明を省略する。
実施の形態3における半導体装置を説明する。実施の形態3は実施の形態1の下位概念であり、実施の形態3における半導体装置は、実施の形態1における半導体装置の各構成を含む。なお、実施の形態1または2と同様の構成および動作については説明を省略する。
実施の形態4における半導体装置を説明する。実施の形態4は実施の形態1の下位概念であり、実施の形態4における半導体装置は、実施の形態1における半導体装置の各構成を含む。なお、実施の形態1から3のいずれかと同様の構成および動作については説明を省略する。
実施の形態5における半導体装置を説明する。実施の形態5は実施の形態1の下位概念であり、実施の形態5における半導体装置は、実施の形態1における半導体装置の各構成を含む。なお、実施の形態1から4のいずれかと同様の構成および動作については説明を省略する。
Claims (6)
- 半導体素子と、
表面に前記半導体素子を搭載するダイパッドと、
前記半導体素子を覆って封止する封止材と、
各々の一端が前記封止材の内部で前記半導体素子に接続され、各々の他端が前記封止材の側面から導出される複数のリードと、を備え、
前記半導体素子と前記ダイパッドと前記封止材とを含むパッケージの下面は、前記ダイパッドの裏面側に位置し、凸状の反り形状を有し、
前記封止材は、前記パッケージの前記下面に、突起部を含み、
前記突起部は、
前記複数のリードが導出する側とは反対側の前記下面において、前記ダイパッドの近傍に対応する位置に設けられる、半導体装置。 - 前記パッケージと前記複数のリードとを含む構造の重心は、平面視において、前記パッケージの中心から偏心している、請求項1に記載の半導体装置。
- 前記封止材の前記内部に設けられ、前記半導体素子の駆動を制御する制御IC(Integrated Circuit)を、さらに備える、請求項1または請求項2に記載の半導体装置。
- 前記封止材の前記内部に設けられ、前記半導体素子に並列接続されるスナバコンデンサを、さらに備える、請求項1から請求項3のいずれか一項に記載の半導体装置。
- 前記半導体素子は、材料として、ワイドバンドギャップ半導体を含む、請求項1から請求項4のいずれか一項に記載の半導体装置。
- 前記凸状の前記反り形状は、前記パッケージの前記下面における一方向に凸状に反っており、
前記複数のリードは、前記封止材の外面を構成する複数の側面のうち、前記一方向の前記側面から導出されている、請求項1から請求項5のいずれか一項に記載の半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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JP2019102527A JP7134137B2 (ja) | 2019-05-31 | 2019-05-31 | 半導体装置 |
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DE102020113643.9A DE102020113643A1 (de) | 2019-05-31 | 2020-05-20 | Halbleitervorrichtung |
CN202010454386.9A CN112018053B (zh) | 2019-05-31 | 2020-05-26 | 半导体装置 |
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US20200381323A1 (en) | 2020-12-03 |
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JP2020198342A (ja) | 2020-12-10 |
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