CN106098565A - 双面散热带引脚薄型扁平封装功率半导体器件的生产方法 - Google Patents
双面散热带引脚薄型扁平封装功率半导体器件的生产方法 Download PDFInfo
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Abstract
本发明公开了一种双面散热带引脚薄型扁平封装功率半导体器件的生产方法,包括(1)划片、(2)软焊料上芯、(3)第二管脚与芯片的连接键合、(4)塑封等步骤,在步骤(3)中,采用焊接劈刀在芯片上压出长条形带有菱形花纹的焊接点,将铝带的一端与芯片焊接;再用焊接劈刀在第二管脚上压出长条形带有菱形花纹的焊接点,将铝带的另一端与芯片焊接;铝带除焊接点外,其余部位均向上拱起,铝带向上拱起的高度不超过420um;在步骤(4)中,塑封后,铝带拱起部位的顶面距离塑封料的顶面厚度为100um‑200um。采用双面散热两排内嵌式引脚扁平封装方法,能够迅速将热量传导到器件表面,达到迅速散热从而保护产品的目的。
Description
技术领域
本发明涉及一种新型功率半导体器件,尤其是双面散热两排内嵌式引脚薄型扁平封装的功率半导体器件的生产方法。
背景技术
随着近年来消费市场对功率器件的需求不断扩大,为功率器件封装行业带来了发展契机。功率器件产品广泛应用于汽车电子产品、计算机管理电源、灯光启动电源、电瓶车等领域,也促进了大电流、高电压功率器件和MOSFET封装技术的发展。
功率器件产品在工作时要消耗较大的电功率,要求产品具有优良的散热能力,电参数要稳定,可靠性要高。因此,在封装和使用中,要求产品散热部位热容量要大,还要有足够的散热功能,工作时能够将内部芯片产生的热量迅速传导到器件表面,避免芯片过热烧伤,或者引起框架基片变形引起分层而影响产品的可靠性。在导电性方面,还要求有良好可靠的电气性能。
所以,功率器件的散热设计是否合理,对功率器件封装行业起到了关键性的作用。传统产品散热途径主要是背面散热片散热,是单面散热。
现目前,半导体中的芯片与管脚采用铜线键合连接,塑封后仅在芯片的背面由引线框架作为散热面进行散热,无法满足新的功率半导体的散热要求。
发明内容
本发明的目的在于提供一种双面散热两排内嵌式引脚扁平封装的功率半导体器件的生产方法,以解决空间有限的产品在使用功率器件过程中能够迅速将热量传导到器件表面,达到迅速散热从而保护产品的目的。
为此,本发明所采用的技术方案为:一种双面散热带引脚薄型扁平封装功率半导体器件的生产方法,包括以下步骤:
步骤一、划片:形成带第一引脚的引线框架,以及独立的第二引脚;
步骤二、软焊料上芯:将引线框架在高温轨道中加热,并通有氮氢混合保护气体,再通过高导热软焊料将芯片焊接在引线框架上方;
步骤三、第二管脚与芯片的连接键合;
步骤四、塑封:
步骤五、去溢料:
步骤六:电镀:
步骤七:切筋分粒成型:
步骤八:测试及包装;
其特征在于:
在步骤三中,选择铝带作为键合连接材料,采用焊接劈刀在芯片上压出与铝带宽度一致的长条形带有菱形花纹的焊接点,将铝带的一端与芯片焊接;再用焊接劈刀在第二管脚上压出与铝带宽度一致的长条形带有菱形花纹的焊接点,将铝带的另一端与芯片焊接;所述铝带除焊接点外,其余部位均向上拱起,拱起部位的顶部为平面,所述铝带在芯片正面形成第二散热面,与设置在芯片背面作为第一散热面的引线框架,共同构成双面散热结构,所述铝带向上拱起的高度不超过420um;
在步骤四中,塑封后,铝带拱起部位的顶面距离塑封料的顶面厚度为100um—200um,第一引脚和第二引脚靠近芯片的一端被塑封,另一端裸露在外,构成两排内嵌式引脚。
作为上述方案的优选,在步骤三中,所述焊接劈刀在芯片上共压出两条相互平行的并与铝带宽度一致的长条形带有菱形花纹的焊接点,除铝带的一端与芯片焊接外,另一端与第二管脚焊接外,铝带的中部也通过焊接点与芯片焊接,从而形成了两个等高的拱起部位,适用于芯片尺寸较大的功率半导体器件焊接。
进一步,所述第二散热面的面积为第二散热面的面积的60%以上,以确保芯片上面有足够的散热面积。
本发明的有益效果:
(1)、芯片与第二管脚键合连接采用大面积的铝带焊接,在芯片正面形成面积与背面面积相当的金属散热通道,塑封后铝带表面塑封料厚度在100um—200um之间,器件正面通过大面积铝带散热,器件背面通过引线框架散热,形成双面散热通道,在器件工作时能迅速通过双散热通道将器件内部热量传导出去;
(2)、限定塑封后铝带表面塑封料厚度在100um—200um之间,既能保证塑封料对芯片的有效保护,又能保证铝带的散热效果;
(3)铝带采用除焊接点外,其余部位均向上拱起的结构形式,既能增加铝带的强度,防止变形,从而保护芯片;又能减少铝带距离塑封料表面的距离,以保证散热效果;
(4)焊接铝带前,采用焊接劈刀在芯片及第二管脚上压出与铝带宽度一致的长条形带有菱形花纹的焊接点,保证焊接的可靠性。
综上所述,该生产方法可用于封装MOSFET驱动器、功率器件、电源系统等,具有卓越电性能和散热性能,可广泛应用于汽车电子产品、计算机管理电源、灯光启动电源、电瓶车等领域以及大电流、高电压功率器件、MOSFET的封装及其它产品,应用范围广阔,市场需求量大,有较好的市场前景。
附图说明
图1为本双面散热带引脚薄型扁平封装功率半导体器件的俯视图。
图2为图1的仰视图。
具体实施方式
下面通过实施例并结合附图,对本发明作进一步说明:
结合图1—图2所示,一种双面散热带引脚薄型扁平封装功率半导体器件的生产方法,包括以下步骤:
步骤一、划片。
通过划片形成带第一引脚1的引线框架3,以及独立的第二引脚2;引线框架3包含若干排列分布的引线框架单元,以及用于连接各个引线框架单元的中筋,经步骤七的切筋分粒成型后,被分割成独立的引线框架单元。
步骤二、软焊料上芯。
为配合焊料熔化,先将引线框架3在高温轨道中加热,通常为330—380℃的高温轨道;并通有10.6%的氮氢混合保护气体,以提高焊料的浸润性,减少焊料气泡的产生,防止引线框架在高温环境下氧化,提高芯片粘接的可靠性;再通过高导热软焊料4,如贺利氏公司生产的Pb94.5Sn3Ag2.5的软焊料,将芯片5焊接在引线框架3上方。
步骤三、第二管脚与芯片的连接键合。
传统工艺中选用铜线进行第二管脚与芯片的连接键合。而本方案中,选择铝带6作为键合连接材料,如TANAKA公司生产的铝带;采用焊接劈刀在芯片5上压出与铝带6宽度一致的长条形带有菱形花纹的焊接点7,将铝带6的一端与芯片5焊接;再用焊接劈刀在第二管脚2上压出与铝带6宽度一致的长条形带有菱形花纹的焊接点7,将铝带6的另一端与芯片5焊接;铝带6除焊接点7外,其余部位均向上拱起,拱起部位的顶部为平面,铝带6在芯片5正面形成第二散热面,与设置在芯片5背面作为第一散热面的引线框架3,共同构成双面散热结构,所述铝带6向上拱起的高度不超过420um。
对于尺寸规格较大的芯片来说,相应地增加铝带的尺寸,为保证铝带焊接的可靠性及整体强度,焊接劈刀在芯片5上共压出两条相互平行的并与铝带6宽度一致的长条形带有菱形花纹的焊接点7,除铝带6的一端与芯片5焊接,另一端与第二管脚2焊接外,铝带6的中部也通过焊接点7与芯片5焊接,从而形成了两个等高的拱起部位。最好是,第二散热面的面积为第二散热面的面积的60%以上,这个数值越大,散热效果越好,但应确保铝带6与芯片5接触的尺寸不得超出芯片5的外轮廓,以避免短路。
步骤四、塑封。
使用低应力,高导热塑封材料进行塑封,如SUMIKON公司的190系列(环保型)、NITTO公司的7000系列(环保型)、华海公司G400系列(环保型)、SCIENCHEM公司的HKG400系列(环保型)。先对引线框架进行预热,在引线框架预热温度与模具温度相差±5℃时进行上料,在合模注塑前要保证引线框架定位准确,与模具配合要紧密,开模后脱模要顺畅。进料流道要使用冲流道模具,让冲流道凸模穿过冲流凹槽,冲压掉粘附在框架和进浇口的进料流道。最后,对产品进行后固化处理。
铝带拱起部位的顶面距离塑封料的顶面厚度为100um—200um,第一引脚和第二引脚靠近芯片的一端被塑封,另一端裸露在外,构成两排内嵌式引脚。
步骤五、去溢料。
电镀前要对引线框架表面进行去溢料软化,再用高压水清除掉塑封过程留下的溢料。
步骤六:电镀。
电镀前首先要去除引线框架表面的杂质及氧化物,其次要对引线框架表面部位进行轻微腐蚀,以提高引线框架与镀层的结合力;然后利用电化学原理在引线框架表面镀上锡层;再次清洗电镀后框架表面的残留药水;电镀结束后进行烘烤。
步骤七:切筋分粒成型。
切筋分粒成型使用级进模,多工位冲切分离法,冲切掉引线边框及中筋连结部位,形成单只产品,再装入包装管中。在切筋分粒成型中,为了避免轨道传送中引线框架变形及镀层划伤,在输料前要修整在塑封或传递过程中造成的引线框架压边及引线框架变形,引线框架在切筋模具轨道传送过程中要使引线框架在轨道中悬浮。冲切凸模与凹模的单边间隙要控制在0.04mm左右,防止毛刺和拉锡现象。
步骤八:测试及包装。
Claims (3)
1.一种双面散热带引脚薄型扁平封装功率半导体器件的生产方法,包括以下步骤:
步骤一、划片:形成带第一引脚的引线框架,以及独立的第二引脚;
步骤二、软焊料上芯:将引线框架在高温轨道中加热,并通有氮氢混合保护气体,再通过高导热软焊料将芯片焊接在引线框架上方;
步骤三、第二管脚与芯片的连接键合;
步骤四、塑封:
步骤五、去溢料:
步骤六:电镀:
步骤七:切筋分粒成型:
步骤八:测试及包装;
其特征在于:
在步骤三中,选择铝带作为键合连接材料,采用焊接劈刀在芯片上压出与铝带宽度一致的长条形带有菱形花纹的焊接点,将铝带的一端与芯片焊接;再用焊接劈刀在第二管脚上压出与铝带宽度一致的长条形带有菱形花纹的焊接点,将铝带的另一端与芯片焊接;所述铝带除焊接点外,其余部位均向上拱起,拱起部位的顶部为平面,所述铝带在芯片正面形成第二散热面,与设置在芯片背面作为第一散热面的引线框架,共同构成双面散热结构,所述铝带向上拱起的高度不超过420um;
在步骤四中,塑封后,铝带拱起部位的顶面距离塑封料的顶面厚度为100um—200um,第一引脚和第二引脚靠近芯片的一端被塑封,另一端裸露在外,构成两排内嵌式引脚。
2.根据权利要求1所述的双面散热带引脚薄型扁平封装功率半导体器件的生产方法,其特征在于:在步骤三中,所述焊接劈刀在芯片上共压出两条相互平行的并与铝带宽度一致的长条形带有菱形花纹的焊接点,除铝带的一端与芯片焊接外,另一端与第二管脚焊接外,铝带的中部也通过焊接点与芯片焊接,从而形成了两个等高的拱起部位。
3.根据权利要求1或2所述的双面散热带引脚薄型扁平封装功率半导体器件的生产方法,其特征在于:所述第二散热面的面积为第二散热面的面积的60%以上。
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110335821A (zh) * | 2019-06-03 | 2019-10-15 | 通富微电子股份有限公司 | 一种具有双面散热的半导体器件及其封装方法 |
CN111341736A (zh) * | 2020-03-19 | 2020-06-26 | 常州星海电子股份有限公司 | 三分体二极管成品管的制备方法及三分体二极管 |
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101495014A (zh) * | 2005-11-18 | 2009-07-29 | 费查尔德半导体有限公司 | 使用引线框和夹片的半导体管芯封装及制造方法 |
CN102842549A (zh) * | 2012-08-23 | 2012-12-26 | 苏州固锝电子股份有限公司 | 四方扁平无引脚的功率mosfet封装体 |
CN103107171A (zh) * | 2011-11-11 | 2013-05-15 | 万国半导体股份有限公司 | 一种倒装芯片的半导体器件 |
CN203026496U (zh) * | 2012-12-28 | 2013-06-26 | 天水华天科技股份有限公司 | 一种多电源ic芯片封装件 |
CN203218250U (zh) * | 2013-02-01 | 2013-09-25 | 意法半导体制造(深圳)有限公司 | 大电流半导体器件以及大电流半导体器件框架 |
CN103972190A (zh) * | 2013-02-01 | 2014-08-06 | 意法半导体制造(深圳)有限公司 | 一种大电流半导体器件及其封装方法 |
US20140332939A1 (en) * | 2010-09-09 | 2014-11-13 | Siliconix Electronic Co., Ltd. | Dual Lead Frame Semiconductor Package and Method of Manufacture |
CN105405833A (zh) * | 2015-12-24 | 2016-03-16 | 江苏长电科技股份有限公司 | 一种多芯片多搭平铺夹芯封装结构及其工艺方法 |
-
2016
- 2016-07-04 CN CN201610516692.4A patent/CN106098565A/zh active Pending
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101495014A (zh) * | 2005-11-18 | 2009-07-29 | 费查尔德半导体有限公司 | 使用引线框和夹片的半导体管芯封装及制造方法 |
US20140332939A1 (en) * | 2010-09-09 | 2014-11-13 | Siliconix Electronic Co., Ltd. | Dual Lead Frame Semiconductor Package and Method of Manufacture |
CN103107171A (zh) * | 2011-11-11 | 2013-05-15 | 万国半导体股份有限公司 | 一种倒装芯片的半导体器件 |
CN102842549A (zh) * | 2012-08-23 | 2012-12-26 | 苏州固锝电子股份有限公司 | 四方扁平无引脚的功率mosfet封装体 |
CN203026496U (zh) * | 2012-12-28 | 2013-06-26 | 天水华天科技股份有限公司 | 一种多电源ic芯片封装件 |
CN203218250U (zh) * | 2013-02-01 | 2013-09-25 | 意法半导体制造(深圳)有限公司 | 大电流半导体器件以及大电流半导体器件框架 |
CN103972190A (zh) * | 2013-02-01 | 2014-08-06 | 意法半导体制造(深圳)有限公司 | 一种大电流半导体器件及其封装方法 |
CN105405833A (zh) * | 2015-12-24 | 2016-03-16 | 江苏长电科技股份有限公司 | 一种多芯片多搭平铺夹芯封装结构及其工艺方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110335821A (zh) * | 2019-06-03 | 2019-10-15 | 通富微电子股份有限公司 | 一种具有双面散热的半导体器件及其封装方法 |
CN110335821B (zh) * | 2019-06-03 | 2021-07-09 | 通富微电子股份有限公司 | 一种具有双面散热的半导体器件及其封装方法 |
CN111341736A (zh) * | 2020-03-19 | 2020-06-26 | 常州星海电子股份有限公司 | 三分体二极管成品管的制备方法及三分体二极管 |
CN113241337A (zh) * | 2020-12-28 | 2021-08-10 | 深圳市信展通电子有限公司 | 新型dfn支架引线结构 |
CN113937009A (zh) * | 2021-10-13 | 2022-01-14 | 重庆平伟伏特集成电路封测应用产业研究院有限公司 | 表贴式双面散热半导体功率器件的封装方法 |
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