CN201435388Y - 一种用于mosfet封装的引线框架 - Google Patents

一种用于mosfet封装的引线框架 Download PDF

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CN201435388Y
CN201435388Y CN2009200913029U CN200920091302U CN201435388Y CN 201435388 Y CN201435388 Y CN 201435388Y CN 2009200913029 U CN2009200913029 U CN 2009200913029U CN 200920091302 U CN200920091302 U CN 200920091302U CN 201435388 Y CN201435388 Y CN 201435388Y
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chip
pin
lead frame
lead
mosfet
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陈泽亚
郑香舜
张长明
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Honor Trust Technology Co Ltd
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Abstract

本实用新型涉及用于MOSFET封装的引线框架，可有效解决原材料浪费，生产成本高，芯片质量差，封装良品率低的问题，其解决的技术方案是，包括有基岛、管脚、导线、焊接区、管脚焊线区，基岛上装有芯片槽，芯片槽内的芯片经导线由管脚焊线区同源级框架管脚相接，芯片槽内的芯片经栅级导线同栅级框架管脚相连，芯片槽内的芯片与漏级框架管脚相连，芯片槽外有封装料封胶体，将芯片封装在封装槽内，本实用新型结构简单、新颖，节省材料，制造成本低，易操作使用，成品率高，是MOSFET封装的引线框架上的创新。

Description

一种用于MOSFET封装的引线框架
一、技术领域
本实用新型涉及半导体生产设备，特别是一种用于MOSFET封装的引线框架。
二、背景技术
近年来，产业的发展、有限的资源及日益严重的地球暖化现象，促使节能的观念逐渐受到重视，为了满足节能和降低功率损耗的需求，需要有着更高的能源转换效率，而有着高效的MOSFET器件正被越来越广泛的应用于汽车、玩具、节能灯及各种电源转换器等领域。这些器件能降低汽车普遍使用的集成启动器、发动机和电子动力方向盘等设备的成本，它们将有助于进一步减少热散发和提升汽车的燃料效能。
图1是目前用于半导体MOSFET器件封装的引线框架及其装配结构实例的平面图。如图1所示，芯片2是经过切割加工后的单个POWER MOSFET器件，通过导热性良好的导电材料连接(例如银胶或焊锡料等)焊接在引线框架的基岛1上面，芯片2通过金属导线3、4(如铝线、金线或铜线)与引线框架的管脚焊线区5连接，然后再将塑封料封胶体以压模方式(molding)填充于集成电路芯片及引线框架周围(通常采用具有一定导热性的塑封料，例如环氧树脂塑封料：epoxy molding compound，EMC)，接着对塑封好的产品成型，去除多余的载体部分，测试完成后便可应用到实际的电路中。此种封装由于MOSFET本身工作原理的关系，栅极Gate承受的电流较小，常采用较细的金线或铜线4作为连接导线，而作为发射极工作的源极Source要满足高电压或大电流输出，故而常采用多条粗铝线3作为连接导线焊接。这样对同一种封装形式，就需要采用不同的金属引线，需要根据金属引线种类选用不同电镀层的引线框架、焊接工具，而且铝线机设备本身价格昂贵，如此会造成原材料的浪费和生产成本高。
其次、由于铝线难以成球，一般为楔形焊接。楔形焊接是通过换能器在超高频的磁场感应下，迅速伸缩产生弹性振动，使钢嘴(WEDGE TOOL)相应振动，同时在钢嘴上施加一定的压力，于是钢嘴在这两种力的共同作用下，带动AL丝在被焊区的金属化层(如AL膜)表面迅速摩擦，使AL丝和AL膜表面产生塑性变形，达到焊接效果。这种形变也破坏了AL层界面的氧化层铝线，同一芯片多次楔焊后会造成芯片内部暗裂。另外，钢嘴(WEDGE TOOL)厚度较大，而管脚焊线区5的面积有限，实际生产中在同一区域多次焊线困难，且易造成虚焊，影响封装的良率及产品可靠性。
再次，对Power MOSFET而言，决定其最大功率损耗是由温度及接触-包装外壳间之热阻所决定，导通时所造成之导通损耗，仍占整体Power MOSFET损耗的大部份，即：若能够有效减少热阻，则Power MOSFET所能承受之的最大功率损耗就可以获得提升。因此，最大改进目标就是减少热阻。各大厂家现仍在致力于降低Power MOSFET之导通电阻，有些厂家采用在晶圆制造时加厚芯片表面的镀铝层厚度或在在封装工艺焊线制程中加多焊线的数量来将内阻rDS(on)降至最低，但不管采用何种方式，都会大大增加成本。在采用现代化沟道技术的低导通电阻器件中，封装电阻占器件总体电阻的40％以上。所以，除了改良开发新的Power MOSFET或工艺技术外，封装的方式亦扮演着重要的角色。现代工艺中也有采用无线凸起连接(wireless bumped connection)，封装rDS(on)可以降至0.1mΩ以下，但此种封装不适于有引线框架的封装。
三、实用新型内容
针对上述情况，为克服现有技术缺陷，本实用新型之目的就是提供一种用于MOSFET封装的引线框架，可有效解决原材料浪费，生产成本高，芯片质量差，封装良品率低的问题，其解决的技术方案是，包括有基岛、管脚、导线、焊接区、管脚焊线区，基岛上装有芯片槽，芯片槽内的芯片经导线由管脚焊线区同源级框架(Source)管脚相接，芯片槽内的芯片经栅级导线同栅级框架(Gate)管脚相连，芯片槽内的芯片与漏级框架(Drain)管脚相连，芯片槽外有封装料封胶体，将芯片封装在封装槽内，与现有的封装工艺相比，节省了封装物料的成本及设备成本，很大程度的提高封装良率及产品的可靠性。其次提高了产品的散热能力，降低了驱动电路的工作温度，由于将引线框架(lead frame)的管脚直接连接到POWER MOSFET芯片的的SOURCE极的表面，降低了封装内阻rDS(on)。能大幅度减少在焊接点及接触点的电阻、更好的减少了封装工艺中结点至外壳的热阻，导通电阻大幅地减少了导通损耗，提高了应用电路的功率密度，因此，具有结构简单、新颖，节省材料，制造成本低，易操作使用，成品率高，是MOSFET封装的引线框架上的创新。
四、附图说明
图1为现有MOSFET封装的引线框架结构主视图。
图2为本实用新型的结构主视图。
图3为本实用新型的结构左剖视图。
图4为本实用新型的另一实施例结构主视图。
图5为图4所示实施例的结构左剖视图。
五、具体实施方式
以下结合附图对本实用新型的具体实施方式作详细说明。
由图2-3所示，本实用新型其结构是，包括有基岛、管脚、导线、焊接区、管脚焊线区，基岛1上装有芯片槽2，芯片槽2内的芯片经导线3由管脚焊线区5同源级框架(Source)6管脚相接，芯片槽2内的芯片经栅级导线4同栅级框架(Gate)8管脚相连，芯片槽2内的芯片与漏级框架(Drain)7管脚相连，芯片槽2外有封装料封胶体10，将芯片封装在封装槽内。
为了保证使用效果，所说的导线3为金属铝导线，经锡球9焊接在芯片槽2内的芯片上；所说的源级框架6管脚呈倾斜状置于基岛的上方，该管脚的底端连接管脚焊线区5及导线3，或金属连接体11及金属片12折弯向下呈直角，与芯片槽2内的芯片表面相平压接在一起。
由图4、5所示，与图2、3所示的引线框架基本结构是相同的，其区别仅在于源级框架6管脚与芯片槽2内的芯片连接形式不同，图2中是由源级框架6的管脚直接同芯片相连，而图4所示的源级框架6的管脚经金属连接体11及金属片12同芯片槽2内的芯片相连，并无本质上的区别，因此，对图2、图5所示的引线框架不再重述。
在上述结构中，通过在POWER MOSFET芯片的SOURCE极上点锡球后，通过压力和温度的作用将延长至引线框架的基岛的上方管脚与SOURCE表面压合在一起，完成焊接。延长至引线框架的基岛的上方管脚形状和大小可根据芯片尺寸进行定做，以满足不同的要求，也可通过在SOURCE端加装连接体装置，用金属片实现与POWER MOSFET的SOURCE的表面连接，得到相同的功用。
与现有的封装工艺相比，本实用新型的优点在于直接将引线框架(leadframe)的SOURCE极管脚通过焊料(锡球)连接到POWER MOSFET芯片的的SOURCE极的表面。这种做法省去了作为发射极工作的源极Source要用多条粗铝线作为连接导线焊接以满足其工作的要求，节省了封装物料的成本。而且针对同一种封装形式，不需要采用不同的金属引线焊接及需要不同电镀层的引线框架，还省去了价格昂贵的铝线机设备，大大节约成本。
其次，由于不采用楔形焊接，实际生产中不用多次焊线，就消除了同一芯片多次楔焊后破坏了AL层界面的氧化层，造成芯片内部暗裂及表面虚焊，可很大程度的提高封装良率及产品的可靠性。
再次，这种封装的散热途径除了通过在本体散热基片加装散热片向外部散热外，还可以通过管脚连接体直接传导出去，使的产品的散热能力有所提高，降低了驱动电路的工作温度。
另外，将引线框架(lead frame)管脚直接连接到POWER MOSFET芯片的的SOURCE极的表面，降低了封装内阻rDS(on)。大幅度减少在焊接点及接触点的电阻、减小结点至外壳的热阻，导通电阻大幅地减少了导通损耗，提高了应用电路的功率密度。

Claims (3)

1、一种用于MOSFET封装的引线框架，包括有基岛、管脚、导线、焊接区、管脚焊线区，其特征在于，基岛(1)上装有芯片槽(2)，芯片槽(2)内的芯片经导线(3)由管脚焊线区(5)同源级框架(6)管脚相接，芯片槽(2)内的芯片经栅级导线(4)同栅级框架(8)管脚相连，芯片槽(2)内的芯片与漏级框架(7)管脚相连，芯片槽(2)外有封装料封胶体(10)。
2、根据权利要求1所述的用于MOSFET封装的引线框架，其特征在于，所说的导线(3)为金属铝导线，经锡球(9)焊接在芯片槽(2)内的芯片上。
3、根据权利要求1所述的用于MOSFET封装的引线框架，其特征在于，所说的源级框架(6)管脚呈倾斜状置于基岛的上方，该管脚的底端连接管脚焊线区(5)及导线(3)，或金属连接体(11)及金属片(12)折弯向下呈直角，与芯片槽(2)内的芯片表面相平压接在一起。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102339808A (zh) * 2011-10-28 2012-02-01 无锡红光微电子有限公司 封装引线框架结构
CN103560123A (zh) * 2013-10-28 2014-02-05 沈健 一种打弯部分倾斜的引线框架
US9589904B2 (en) 2013-02-14 2017-03-07 Infineon Technologies Austria Ag Semiconductor device with bypass functionality and method thereof
CN110581105A (zh) * 2019-07-30 2019-12-17 陈碧霞 一种金属氧化物半导体粘结防挡光滑动的场效应管

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102339808A (zh) * 2011-10-28 2012-02-01 无锡红光微电子有限公司 封装引线框架结构
US9589904B2 (en) 2013-02-14 2017-03-07 Infineon Technologies Austria Ag Semiconductor device with bypass functionality and method thereof
CN103996667B (zh) * 2013-02-14 2017-04-12 英飞凌科技奥地利有限公司 具有旁路功能的半导体器件及其方法
CN103560123A (zh) * 2013-10-28 2014-02-05 沈健 一种打弯部分倾斜的引线框架
CN110581105A (zh) * 2019-07-30 2019-12-17 陈碧霞 一种金属氧化物半导体粘结防挡光滑动的场效应管

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