CN103021994A - 一种aaqfn二次塑封与二次植球优化的封装件及其制作工艺 - Google Patents

一种aaqfn二次塑封与二次植球优化的封装件及其制作工艺 Download PDF

Info

Publication number
CN103021994A
CN103021994A CN2012105822183A CN201210582218A CN103021994A CN 103021994 A CN103021994 A CN 103021994A CN 2012105822183 A CN2012105822183 A CN 2012105822183A CN 201210582218 A CN201210582218 A CN 201210582218A CN 103021994 A CN103021994 A CN 103021994A
Authority
CN
China
Prior art keywords
etching
lead frame
chip
plastic
ball
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2012105822183A
Other languages
English (en)
Inventor
王虎
谌世广
刘卫东
李涛涛
马利
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huatian Technology Xian Co Ltd
Original Assignee
Huatian Technology Xian Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huatian Technology Xian Co Ltd filed Critical Huatian Technology Xian Co Ltd
Priority to CN2012105822183A priority Critical patent/CN103021994A/zh
Publication of CN103021994A publication Critical patent/CN103021994A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明公开了一种AAQFN二次塑封与二次植球优化的封装件及其制作工艺，所述封装件主要由蚀刻后铜引线框架、粘片胶、芯片、键合线、塑封料、蚀刻凹槽、锡球、镍钯金镀层组成。所述制作工艺主要按照以下步骤进行：铜框架半蚀刻、晶圆减薄、晶圆划片、上芯、压焊、一次塑封、框架背面蚀刻、刷锡膏回流、二次塑封、磨屑部分塑封体、锡球电镀镍钯金、二次植球。本发明具有节约封装成本、以及散热性、电性能和共面性好等特点。

Description

一种AAQFN二次塑封与二次植球优化的封装件及其制作工艺
技术领域
本发明涉及于半导体封装技术领域，具体是一种AAQFN二次塑封与二次植球优化的封装件及其制作工艺。
背景技术
随着技术的不断发展，电子封装不但要提供芯片的保护，同时还要在一定的成本下满足不断增加的性能、可靠性、散热、功率分配等要求。
AAQFN封装在成熟的蚀刻工艺技术基础上，从框架设计、材料选择、焊盘结构优化等方面入手，建立完善的封装工艺技术，不断调整优化，突破窄间距（0.4mm）、超薄型（0.5mm 以下）封装技术难点，实现面内I/O 布局列阵AAQFN 封装，形成成套封装工艺技术，在一定的成本下满足了不断增加的性能、可靠性、散热、功率分配等要求。
    以往的AAQFN封装工艺主要是在框架蚀刻凹槽刷Solder mask，然后在引脚植入锡球，而AAQFN二次塑封与二次植球优化在此基础上代替蚀刻凹槽刷Solder mask，采用二次塑封，二次塑封时不用贴膜，将锡球全部封住，然后采用磨屑的方法将二次塑封体去掉一部分，露出锡球横截面，随后在锡球表面电镀镍钯金，再进行二次植球。从而在低成本要求下满足不断增加的性能、可靠性、散热、功率分配等要求，具有明显的技术优势。
发明内容
针对上述封装技术存在的问题，本发明提供了一种AAQFN二次塑封与二次植球优化的封装件及其制作工艺，其在以往AAQFN封装技术的基础上，对产品进行二次塑封与二次植球优化，促进了电子封装技术的发展。
本发明的技术方案是：一种AAQFN二次塑封与二次植球优化的封装件，主要由蚀刻后铜引线框架、粘片胶、芯片、键合线、塑封料、蚀刻凹槽、锡球、镍钯金镀层组成。所述的蚀刻后铜引线框架是半蚀刻处理，其通过粘片胶粘接芯片，芯片通过键合线与蚀刻后铜引线框架的引脚相连，所述蚀刻后铜引线框架、蚀刻后铜引线框架的引脚、芯片和键合线由塑封体包围连接；所述蚀刻凹槽由蚀刻后铜引线框架底部蚀刻后形成，所述锡球由蚀刻后的引脚底部刷锡膏回流后形成，蚀刻凹槽与锡球由塑封体包围连接；所述锡球的横截面由磨屑形成，锡球的横截面有镍钯金电镀层，所述锡球浸锡回流后在镍钯金电镀层上形成。
所述制作工艺主要按照以下步骤进行：铜框架半蚀刻、晶圆减薄、晶圆划片、上芯、压焊、一次塑封、框架背面蚀刻、刷锡膏回流、二次塑封、磨屑部分塑封体、锡球电镀镍钯金、二次植球。
AAQFN二次塑封与二次植球优化在以往技术的基础上进一步改进，无需Solder mask底部填充，二次塑封时不用贴膜，节省了材料的消耗，从而就节约了封装成本；AAQFN二次塑封与二次植球优化通过二次塑封将球全部封住，然后采用磨屑的方法将二次塑封体去掉一部分，露出锡球横截面，在锡表面电镀镍钯金，进行二次植球，可提高导电性、润滑性、耐热性、和表面美观，具有明显的技术优势，能够实现多引脚、高密度、小型薄型化封装，具有散热性、电性能以及共面性好等特点。本发明为无铅、无卤素的环保型先进封装技术，可应用于更大范围的移动、消费电子产品上，满足移动通信和移动计算机领域的便捷式电子机器，如PDA、3G手机、MP3、MP4、MP5等超薄型电子产品发展的需要，是迅速成长起来的一种新型封装技术。
说明书附图
图1 引线框架剖面图；
图2 上芯后产品剖面图；
图3 压焊后产品剖面图；
图4 一次塑封后产品剖面图；
图5框架背面蚀刻后产品剖面图；
图6锡膏回流焊后产品剖面图；
图7二次塑封后产品剖面图；
图8 磨屑后产品剖面图；
图9 锡球截面电镀后产品剖面图；
图10 二次植球后产品剖面图。
图中、1为蚀刻后铜引线框架、2为粘片胶、3为芯片、4为键合线、5和8为塑封体、6为蚀刻凹槽、7和10为锡球、9为镍钯金电镀层。
具体实施方式
下面结合附图对本发明做进一步详细叙述。
如图所示，一种AAQFN二次塑封与二次植球优化的封装件，主要由蚀刻后铜引线框架1、粘片胶2、芯片3、键合线4、塑封料5和8、蚀刻凹槽6、锡球7和10、镍钯金镀层9组成。所述的蚀刻后铜引线框架1是半蚀刻处理，其通过粘片胶2粘接芯片3，芯片3通过键合线4与蚀刻后铜引线框架1的引脚相连，所述蚀刻后铜引线框架1、蚀刻后铜引线框架1的引脚、芯片3和键合线4由塑封体5包围连接；所述蚀刻凹槽6由蚀刻后铜引线框架1底部蚀刻后形成，所述锡球7由蚀刻后的引脚底部刷锡膏回流后形成，蚀刻凹槽6与锡球7由塑封体8包围连接；所述锡球7的横截面由磨屑形成，锡球7的横截面有镍钯金电镀层9，所述锡球10浸锡回流后在镍钯金电镀层9上形成。
如图所示，一种AAQFN二次塑封与二次植球优化的封装件的制作工艺，其按照以下步骤进行：
第一步、铜引线框架蚀刻：将铜引线框架进行半蚀刻，依据芯片pad分布结构，通过成熟的涂胶、曝光、显影、电镀及腐蚀等工艺，在铜板正面蚀刻出载体，互连线，I/O Pad，确定I/O Pad大小，脚间距和它们各自的位置；如图1所示；
第二步、晶圆减薄和划片：在晶圆正面贴上胶膜，然后在专用减薄机上进行减薄达到工艺要求；减薄完的晶圆清洗经检验合格后，去掉正面胶膜，在晶圆背面贴上胶膜后再进行划片，将晶圆划成单个IC芯片；
第三步、上芯：使用专用上料夹，用点胶头均匀的将粘片胶2（导电胶或绝缘胶）点在蚀刻后铜引线框架1的PAD上，吸嘴将承片台上的芯片3吸起放置到已点好粘片胶2的蚀刻后铜引线框架1上，粘片后框架自动送到弹夹中；如图2所示；
第四步、压焊：在专用压焊机上，键合线4采用金线或铜线，通过球焊把芯片3上的焊盘（PAD）和蚀刻后铜引线框架1的引脚相连，形成了电路的电源和信号通道；如图3所示；
第五步、一次塑封：采用塑料包封系统将压焊后的产品自动传送到塑封模具中，用塑封体5对压焊后的产品进行包封，随后进行固化；如图4所示；
第六步、框架背面蚀刻：对蚀刻后铜引线框架1进行背面蚀刻，将选定的露铜部分蚀刻掉，进行引脚分离；如图 5所示；
第七步、刷锡膏回流：在蚀刻后引脚底部进行钢网刷锡膏，形成的锡膏进行回流焊后形成锡球7；如图6所示；
第八步、二次塑封：用塑封体8完全包封锡球7与底部蚀刻凹槽6，随后进行固化；如图7所示；
第九步、磨屑部分塑封体、锡球电镀镍钯金、二次植球：采用磨屑的方法将二次塑封体8去掉一部分，露出锡球7横截面，然后在锡球7横截面上电镀镍钯金形成镍钯金电镀层9，再通过浸锡回流在镍钯金电镀层9上植入锡球10；如图8、图9和图10。

Claims (2)

1.一种AAQFN二次塑封与二次植球优化的封装件，其特征在于：主要由蚀刻后铜引线框架（1）、粘片胶（2）、芯片（3）、键合线（4）、塑封料（5）和（8）、蚀刻凹槽（6）、锡球（7）和（10）、镍钯金电镀层（9）组成；所述的蚀刻后铜引线框架（1）是半蚀刻处理，其通过粘片胶（2）粘接芯片（3），芯片（3）通过键合线（4）与蚀刻后铜引线框架（1）的引脚相连，所述蚀刻后铜引线框架（1）、蚀刻后铜引线框架（1）的引脚、芯片（3）和键合线（4）由塑封体（5）包围连接；所述蚀刻凹槽（6）由蚀刻后铜引线框架（1）底部蚀刻后形成，所述锡球（7）由蚀刻后的引脚底部刷锡膏回流后形成，蚀刻凹槽（6）与锡球（7）由塑封体（8）包围连接；所述锡球（7）的横截面由磨屑形成，锡球（7）的横截面有镍钯金电镀层（9），所述锡球（10）浸锡回流后在镍钯金电镀层（9）上形成。
2.一种AAQFN二次塑封与二次植球优化的封装件的制作工艺，其特征在于：其按照以下步骤进行：
第一步、铜引线框架蚀刻：将铜引线框架进行半蚀刻，依据芯片pad分布结构，通过成熟的涂胶、曝光、显影、电镀及腐蚀等工艺，在铜板正面蚀刻出载体，互连线，I/O Pad，确定I/O Pad大小，脚间距和它们各自的位置；
第二步、晶圆减薄和划片：在晶圆正面贴上胶膜，然后在专用减薄机上进行减薄达到工艺要求；减薄完的晶圆清洗经检验合格后，去掉正面胶膜，在晶圆背面贴上胶膜后再进行划片，将晶圆划成单个IC芯片；
第三步、上芯：使用专用上料夹，用点胶头均匀的将粘片胶（2）（导电胶或绝缘胶）点在蚀刻后铜引线框架（1）的PAD上，吸嘴将承片台上的芯片（3）吸起放置到已点好粘片胶（2）的蚀刻后铜引线框架（1）上，粘片后框架自动送到弹夹中；
第四步、压焊：在专用压焊机上，键合线（4）采用金线或铜线，通过球焊把芯片（3）上的焊盘（PAD）和蚀刻后铜引线框架（1）的引脚相连，形成了电路的电源和信号通道；
第五步、一次塑封：采用塑料包封系统将压焊后的产品自动传送到塑封模具中，用塑封体（5）对压焊后的产品进行包封，随后进行固化；
第六步、框架背面蚀刻：对蚀刻后铜引线框架（1）进行背面蚀刻，将选定的露铜部分蚀刻掉，进行引脚分离；
第七步、刷锡膏回流：在蚀刻后引脚底部进行钢网刷锡膏，形成的锡膏进行回流焊后形成锡球（7）；
第八步、二次塑封：用塑封体（8）完全包封锡球（7）与底部蚀刻凹槽（6），随后进行固化；
第九步、磨屑部分塑封体、锡球电镀镍钯金、二次植球：采用磨屑的方法将二次塑封体（8）去掉一部分，露出锡球（7）横截面，然后在锡球（7）横截面上电镀镍钯金形成镍钯金电镀层（9），再通过浸锡回流在镍钯金电镀层（9）上植入锡球（10）。
CN2012105822183A 2012-12-28 2012-12-28 一种aaqfn二次塑封与二次植球优化的封装件及其制作工艺 Pending CN103021994A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2012105822183A CN103021994A (zh) 2012-12-28 2012-12-28 一种aaqfn二次塑封与二次植球优化的封装件及其制作工艺

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2012105822183A CN103021994A (zh) 2012-12-28 2012-12-28 一种aaqfn二次塑封与二次植球优化的封装件及其制作工艺

Publications (1)

Publication Number Publication Date
CN103021994A true CN103021994A (zh) 2013-04-03

Family

ID=47970424

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2012105822183A Pending CN103021994A (zh) 2012-12-28 2012-12-28 一种aaqfn二次塑封与二次植球优化的封装件及其制作工艺

Country Status (1)

Country Link
CN (1) CN103021994A (zh)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103531486A (zh) * 2013-09-28 2014-01-22 宁波康强电子股份有限公司 一种引线框架的制作方法
CN103730442A (zh) * 2013-12-31 2014-04-16 天水华天科技股份有限公司 带焊球面阵列四边无引脚封装体堆叠封装件及制备方法
CN103730443A (zh) * 2013-12-31 2014-04-16 天水华天科技股份有限公司 带焊球面阵列四边无引脚ic芯片堆叠封装件及生产方法
CN105118787A (zh) * 2015-04-22 2015-12-02 丽智电子(昆山)有限公司 一种采用激光烧铜的产品加工工艺
CN107275225A (zh) * 2017-06-20 2017-10-20 上海图正信息科技股份有限公司 芯片封装模组的制备方法及封装结构
CN107316818A (zh) * 2017-06-20 2017-11-03 上海图正信息科技股份有限公司 芯片封装模组的制备方法及封装结构
CN109037077A (zh) * 2018-06-13 2018-12-18 南通通富微电子有限公司 一种半导体芯片封装方法
CN109065519A (zh) * 2018-06-13 2018-12-21 南通通富微电子有限公司 一种半导体芯片封装器件
CN109065518A (zh) * 2018-06-13 2018-12-21 南通通富微电子有限公司 一种半导体芯片封装阵列
CN112045329A (zh) * 2020-09-07 2020-12-08 中国电子科技集团公司第二十四研究所 一种金属基板上植球的倒装焊工艺方法
CN117116923A (zh) * 2023-10-25 2023-11-24 广东风华芯电科技股份有限公司 一种双通道开关晶体管及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101826501A (zh) * 2009-03-06 2010-09-08 李同乐 高密度接点的无引脚集成电路元件
CN102354691A (zh) * 2011-11-04 2012-02-15 北京工业大学 一种高密度四边扁平无引脚封装及制造方法
CN102365737A (zh) * 2009-03-30 2012-02-29 凸版印刷株式会社 半导体元件用基板的制造方法及半导体器件
CN101958300B (zh) * 2010-09-04 2012-05-23 江苏长电科技股份有限公司 双面图形芯片倒装模组封装结构及其封装方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101826501A (zh) * 2009-03-06 2010-09-08 李同乐 高密度接点的无引脚集成电路元件
CN102365737A (zh) * 2009-03-30 2012-02-29 凸版印刷株式会社 半导体元件用基板的制造方法及半导体器件
CN101958300B (zh) * 2010-09-04 2012-05-23 江苏长电科技股份有限公司 双面图形芯片倒装模组封装结构及其封装方法
CN102354691A (zh) * 2011-11-04 2012-02-15 北京工业大学 一种高密度四边扁平无引脚封装及制造方法

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103531486A (zh) * 2013-09-28 2014-01-22 宁波康强电子股份有限公司 一种引线框架的制作方法
CN103531486B (zh) * 2013-09-28 2016-08-17 宁波康强电子股份有限公司 一种引线框架的制作方法
CN103730442A (zh) * 2013-12-31 2014-04-16 天水华天科技股份有限公司 带焊球面阵列四边无引脚封装体堆叠封装件及制备方法
CN103730443A (zh) * 2013-12-31 2014-04-16 天水华天科技股份有限公司 带焊球面阵列四边无引脚ic芯片堆叠封装件及生产方法
CN103730442B (zh) * 2013-12-31 2016-06-08 天水华天科技股份有限公司 带焊球面阵列四边无引脚封装体堆叠封装件及制备方法
CN103730443B (zh) * 2013-12-31 2016-08-24 天水华天科技股份有限公司 带焊球面阵列四边无引脚ic芯片堆叠封装件及生产方法
CN105118787A (zh) * 2015-04-22 2015-12-02 丽智电子(昆山)有限公司 一种采用激光烧铜的产品加工工艺
CN107316818A (zh) * 2017-06-20 2017-11-03 上海图正信息科技股份有限公司 芯片封装模组的制备方法及封装结构
CN107275225A (zh) * 2017-06-20 2017-10-20 上海图正信息科技股份有限公司 芯片封装模组的制备方法及封装结构
CN109037077A (zh) * 2018-06-13 2018-12-18 南通通富微电子有限公司 一种半导体芯片封装方法
CN109065519A (zh) * 2018-06-13 2018-12-21 南通通富微电子有限公司 一种半导体芯片封装器件
CN109065518A (zh) * 2018-06-13 2018-12-21 南通通富微电子有限公司 一种半导体芯片封装阵列
CN109037077B (zh) * 2018-06-13 2020-12-25 南通通富微电子有限公司 一种半导体芯片封装方法
CN109065519B (zh) * 2018-06-13 2020-12-25 南通通富微电子有限公司 一种半导体芯片封装器件
CN112045329A (zh) * 2020-09-07 2020-12-08 中国电子科技集团公司第二十四研究所 一种金属基板上植球的倒装焊工艺方法
CN112045329B (zh) * 2020-09-07 2022-03-11 中国电子科技集团公司第二十四研究所 一种金属基板上植球的倒装焊工艺方法
CN117116923A (zh) * 2023-10-25 2023-11-24 广东风华芯电科技股份有限公司 一种双通道开关晶体管及其制作方法

Similar Documents

Publication Publication Date Title
CN103021994A (zh) 一种aaqfn二次塑封与二次植球优化的封装件及其制作工艺
CN102005432B (zh) 四面无引脚封装结构及其封装方法
CN102543907B (zh) 一种热增强型四边扁平无引脚倒装芯片封装及制造方法
CN103094235A (zh) 一种应用电镀工艺的aaqfn封装件及其制作工艺
CN101533814B (zh) 芯片级倒装芯片封装构造
CN203055899U (zh) 一种带有铜柱的晶圆减薄的单芯片封装件
CN102231372B (zh) 多圈排列无载体ic芯片封装件及其生产方法
CN102231376B (zh) 多圈排列无载体双ic芯片封装件及其生产方法
CN104538376A (zh) 一种带有铜柱的pop封装结构及其制备方法
CN201435388Y (zh) 一种用于mosfet封装的引线框架
CN102263077A (zh) 一种双扁平无载体无引脚的ic芯片封装件
US9466592B2 (en) Multi-chips in system level and wafer level package structure
CN102222658A (zh) 多圈排列ic芯片封装件及其生产方法
CN103050465A (zh) 一种带有铜柱的晶圆减薄的单芯片封装件及其制作工艺
CN203589006U (zh) 一种aaqfn二次塑封与二次植球优化的封装件
US20130009294A1 (en) Multi-chip package having leaderframe-type contact fingers
CN103094236A (zh) 一种底填料固化后晶圆减薄的单芯片封装件及其制作工艺
CN203260570U (zh) 一种基于框架腐蚀凸点的无载体式新型封装件
CN105161475A (zh) 带有双圈焊凸点的无引脚csp堆叠封装件及其制造方法
CN103021882A (zh) 一种基于磨屑塑封体的扁平封装件制作工艺
CN203103281U (zh) 一种底填料固化后晶圆减薄的单芯片封装件
CN202196776U (zh) 一种扁平无载体无引线引脚外露封装件
CN202394966U (zh) 一种具有接地环的e/LQFP堆叠封装件
CN103107145A (zh) 半导体封装件、预制导线架及其制法
CN102254893A (zh) 一种带双凸点的四边扁平无引脚封装件及其生产方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20130403