CN104538376A - 一种带有铜柱的pop封装结构及其制备方法 - Google Patents

一种带有铜柱的pop封装结构及其制备方法 Download PDF

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CN104538376A
CN104538376A CN201410843212.6A CN201410843212A CN104538376A CN 104538376 A CN104538376 A CN 104538376A CN 201410843212 A CN201410843212 A CN 201410843212A CN 104538376 A CN104538376 A CN 104538376A
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substrate
copper post
pad
encapsulating structure
packaging part
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梁天胜
谌世广
刘卫东
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Huatian Technology Xian Co Ltd
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Huatian Technology Xian Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

本发明公开了一种带有铜柱的POP封装结构,主要由基板、铜柱、焊盘、芯片、凸点、填充胶、塑封料、焊球组成;所述基板上有焊盘,芯片通过凸点与焊盘连接,所述填充胶填充芯片、凸点、焊盘和基板的连接部分,所述基板下表面上有焊盘,焊盘连接有焊球,所述基板上有铜柱,所述塑封料包围芯片、填充胶、基板上表面部分和铜柱,所述铜柱的上表面裸露;所述制备方法为:基板上连接铜柱,塑封时裸露铜柱上表面,上封装体的焊球与铜柱上表面连接。过程中不需要激光开孔,不需要清洗基板和封装结构上表面不需要植球,简化工艺,节约成本,提高了封装效率。

Description

一种带有铜柱的POP封装结构及其制备方法
技术领域
本发明涉及半导体封装领域,尤其涉及一种带有铜柱的POP封装结构及其制备方法。
背景技术
POP封装是一种很典型的半导体堆叠封装,在逻辑电路及存储器领域,其已被作为业界的首选,主要应用于制造高端便携式设备和智能手机使用的先进移动通信平台。传统的POP封装结构,其下封装体与上封装体互联窗口的制备,通常是先对下封装结构进行塑封,然后利用激光烧蚀的方法在下封装体(对应上封装体基板下表面焊球位置)上表面开槽,此凹槽与下封装体上表面焊盘位置相同,露出预先存在的焊球或在凹槽内进行锡膏印刷植球,最后用于和上封装体进行焊接互连。
但是,如上所述方法,在现有的POP的制程过程中,需要在塑封体上开槽以及通过焊料印刷形成互连焊球的方法,制作工艺复杂,且成本较高。
发明内容
针对上述现有技术存在的问题,本发明提供一种带有铜柱的POP封装结构及其制备方法,基板上连接铜柱,塑封时裸露铜柱上表面,上封装体的焊球与铜柱上表面连接。过程中不需要激光开孔,不需要清洗基板和封装结构上表面不需要植球,简化工艺,节约成本,提高了封装效率。
所述封装结构主要由基板、铜柱、焊盘、芯片、凸点、填充胶、塑封料、焊球组成;所述基板上有焊盘,芯片通过凸点与焊盘连接,所述填充胶填充芯片、凸点、焊盘和基板的连接部分,所述基板下表面上有焊盘,焊盘连接有焊球,所述基板上有铜柱,所述塑封料包围芯片、填充胶、基板上表面部分和铜柱,所述铜柱的上表面裸露。
所述封装结构还连接有上封装件,上封装件主要由上封装件芯片,上封装件凸点,上封装件填充胶,上封装件基板、焊盘和上封装件焊球组成;所述上封装件基板通过焊盘、上封装件焊球与铜柱的上表面连接。
所述焊球和上封装件焊球中焊球成份为Sn、SnAg、SnCu、SnPb或者SnAgCu焊料。
一种带有铜柱的POP封装结构的制备方法,具体按照以下步骤进行:
步骤1:基板上焊接焊盘,基板上连接铜柱;
步骤2:在基板上表面的焊盘上倒装贴装带有凸点的芯片,并用填充胶填充四者的连接部分;
步骤3:用塑封料塑封包围芯片、填充胶、基板上表面部分和铜柱,铜柱的上表面裸露;
步骤4:在基板下表面的焊盘上植焊球,形成带有铜柱的POP封装结构。
与所述该POP封装结构将其他封装件作为上封装件连接,所述上封装件基板通过焊盘、上封装件焊球与该封装结构的铜柱的上表面连接,形成两层封装体的堆叠。
所述封装结构不局限于两层封装体进行堆叠,也可为两个以上封装体形成堆叠结构。
附图说明
图1是带有铜柱的基板示意图;
图2是倒装上芯示意图;
图3是塑封示意图;
图4为植球示意图;
图5为堆叠结构的封装件示意图。
图中,1为基板,2为铜柱,3为焊盘,4为芯片,5为凸点,6为填充胶,7为塑封料,8为焊球,9为上封装件芯片,10为上封装件凸点,11为上封装件填充胶,12为上封装件基板、13为上封装件焊球。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚,下面结合附图对本发明的具体实施方式作进一步详细描述。
一种带有铜柱的POP封装结构,主要由基板1、铜柱2、焊盘3、芯片4、凸点5、填充胶6、塑封料7、焊球8组成;所述基板1上有焊盘3,芯片4通过凸点5与焊盘3连接,所述填充胶6填充芯片4、凸点5、焊盘3和基板1的连接部分,所述基板下表面上有焊盘3,焊盘3连接有焊球8,所述基板1上有铜柱2,所述塑封料7包围芯片4、填充胶6、基板1上表面部分和铜柱2,所述铜柱2的上表面裸露。
所述POP封装结构还连接有上封装件,上封装件主要由上封装件芯片9,上封装件凸点10,上封装件填充胶11,上封装件基板12、焊盘和上封装件焊球13组成;所述上封装件基板12通过焊盘、上封装件焊球13与铜柱2的上表面连接。
一种带有铜柱的POP封装结构的制备方法,具体按照以下步骤进行:
1、基板1上焊接焊盘3,基板上连接铜柱2,如图1所示;
2、在基板1上表面的焊盘3上倒装贴装带有凸点5的芯片4,并用填充胶填充6四者的连接部分,如图2所示;
3、用塑封料7塑封包围芯片4、填充胶6、基板1上表面部分和铜柱2,铜柱2的上表面裸露,如图3所示;
4、在基板1下表面的焊盘3上植焊球8,如图4所示;
5、将其他封装件作为上封装件与该POP封装结构连接,所述上封装件基板12通过焊盘、上封装件焊球13与该封装结构的铜柱2的上表面连接,形成两层封装体的堆叠,如图5所示。
所述封装结构不局限于两层封装体进行堆叠,也可为两个以上封装体形成堆叠结构。
以上所述仅为本发明的一个典型实施例,并不用以限制本发明,凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。

Claims (6)

1.一种带有铜柱的POP封装结构,其特征在于,所述封装结构主要由基板(1)、铜柱(2)、焊盘(3)、芯片(4)、凸点(5)、填充胶(6)、塑封料(7)、焊球(8)组成;所述基板(1)上有焊盘(3),芯片(4)通过凸点(5)与焊盘(3)连接,所述填充胶(6)填充芯片(4)、凸点(5)、焊盘(3)和基板(1)的连接部分,所述基板下表面上有焊盘(3),焊盘(3)连接有焊球(8),所述基板(1)上有铜柱(2),所述塑封料(7)包围芯片(4)、填充胶(6)、基板(1)上表面部分和铜柱(2),所述铜柱(2)的上表面裸露。
2.根据权利要求1所示的所述一种带有铜柱的POP封装结构,其特征在于,所述封装结构还连接有上封装件,上封装件主要由上封装件芯片(9),上封装件凸点(10),上封装件填充胶(11),上封装件基板(12)、焊盘和上封装件焊球(13)组成;所述上封装件基板(12)通过焊盘、上封装件焊球(13)与铜柱(2)的上表面连接。
3.根据权利要求1或者2所述的一种带有铜柱的POP封装结构,其特征在于:所述焊球(8)和上封装件焊球(13)中焊球成份为Sn、SnAg、SnCu、SnPb或者SnAgCu焊料。
4.一种带有铜柱的POP封装结构的制备方法,其特征在于,具体按照以下步骤进行:
步骤1:基板(1)上焊接焊盘(3),基板上连接铜柱(2);
步骤2:在基板(1)上表面的焊盘(3)上倒装贴装带有凸点(5)的芯片(4),并用填充胶填充(6)四者的连接部分;
步骤3:用塑封料(7)塑封包围芯片(4)、填充胶(6)、基板(1)上表面部分和铜柱(2),铜柱(2)的上表面裸露;
步骤4:在基板(1)下表面的焊盘(3)上植焊球(8),形成带有铜柱的POP封装结构。
5.根据权利要求4所述的一种带有铜柱的POP封装结构的制备方法,其特征在于,与所述该POP封装结构将其他封装件作为上封装件连接,所述上封装件基板(12)通过焊盘、上封装件焊球(13)与该封装结构的铜柱(2)的上表面连接,形成两层封装体的堆叠。
6.根据权利要求5所述的一种带有铜柱的POP封装结构的制备方法,其特征在于:所述封装结构不局限于两层封装体进行堆叠,也可为两个以上封装体形成堆叠结构。
CN201410843212.6A 2014-12-30 2014-12-30 一种带有铜柱的pop封装结构及其制备方法 Pending CN104538376A (zh)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107742625A (zh) * 2017-09-22 2018-02-27 江苏长电科技股份有限公司 一种元件垂直贴装封装结构及其工艺方法
CN110349861A (zh) * 2019-06-27 2019-10-18 深圳第三代半导体研究院 一种新型PoP封装结构及其制作方法
CN110767648A (zh) * 2019-10-29 2020-02-07 华天科技(西安)有限公司 一种加铜柱型的ssd存储芯片封装结构及其封装方法
CN113764391A (zh) * 2021-07-12 2021-12-07 太极半导体(苏州)有限公司 一种包括垂直导电柱结构的三维半导体层叠封装结构
CN113759633A (zh) * 2016-01-07 2021-12-07 Lg伊诺特有限公司 透镜驱动装置、相机模组及光学设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1625805A (zh) * 2002-02-06 2005-06-08 揖斐电株式会社 半导体芯片安装用基板及其制造方法和半导体模块
US20100258932A1 (en) * 2009-04-08 2010-10-14 Elpida Memory, Inc. Supporting substrate before cutting, semiconductor device, and method of forming semiconductor device
CN104078435A (zh) * 2014-07-15 2014-10-01 南通富士通微电子股份有限公司 Pop封装结构

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1625805A (zh) * 2002-02-06 2005-06-08 揖斐电株式会社 半导体芯片安装用基板及其制造方法和半导体模块
US20100258932A1 (en) * 2009-04-08 2010-10-14 Elpida Memory, Inc. Supporting substrate before cutting, semiconductor device, and method of forming semiconductor device
CN104078435A (zh) * 2014-07-15 2014-10-01 南通富士通微电子股份有限公司 Pop封装结构

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113759633A (zh) * 2016-01-07 2021-12-07 Lg伊诺特有限公司 透镜驱动装置、相机模组及光学设备
CN113759633B (zh) * 2016-01-07 2024-06-14 Lg伊诺特有限公司 透镜驱动装置、相机模组及光学设备
CN107742625A (zh) * 2017-09-22 2018-02-27 江苏长电科技股份有限公司 一种元件垂直贴装封装结构及其工艺方法
CN110349861A (zh) * 2019-06-27 2019-10-18 深圳第三代半导体研究院 一种新型PoP封装结构及其制作方法
CN110767648A (zh) * 2019-10-29 2020-02-07 华天科技(西安)有限公司 一种加铜柱型的ssd存储芯片封装结构及其封装方法
CN113764391A (zh) * 2021-07-12 2021-12-07 太极半导体(苏州)有限公司 一种包括垂直导电柱结构的三维半导体层叠封装结构

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Application publication date: 20150422