CN108231729B - 一种封装基板、芯片封装体及芯片堆叠封装方法 - Google Patents

一种封装基板、芯片封装体及芯片堆叠封装方法 Download PDF

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CN108231729B
CN108231729B CN201711498438.7A CN201711498438A CN108231729B CN 108231729 B CN108231729 B CN 108231729B CN 201711498438 A CN201711498438 A CN 201711498438A CN 108231729 B CN108231729 B CN 108231729B
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CN108231729A (zh
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束方沛
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Nantong Fujitsu Microelectronics Co Ltd
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Abstract

本申请公开了一种封装基板、芯片封装体及芯片堆叠封装方法，涉及芯片封装技术领域。该方法包括：提供第一封装基板，其中，第一封装基板包括至少一个连接柱，连接柱除上表面外设置有树脂保护层；将至少一个芯片倒装于第一封装基板上，并进行焊接互连，形成第一芯片封装体；提供第二芯片封装体，将第一芯片封装体与第二芯片封装体进行堆叠封装，第一芯片封装体通过连接柱与第二芯片封装体形成电连接。通过上述方式，本申请能够制得稳定性和良品率较高的芯片封装体。

Description

一种封装基板、芯片封装体及芯片堆叠封装方法
技术领域
本申请涉及芯片封装技术领域，特别是涉及一种封装基板、芯片封装体及芯片堆叠封装方法。
背景技术
随着集成电路集成度的增加，对于芯片的封装密度要求也越来越高，因此，叠层芯片封装逐渐成为技术发展的主流。现有成熟的三维集成技术主要为堆叠封装(Package onPackage，PoP)，在PoP封装中，上、下封装体通常以焊球作为互联结构实现上、下封装体的导通。
请结合参阅图1和图2，图1是现有技术中PoP封装体的侧面结构示意图，图2是现有技术中PoP封装体的俯视结构示意图。现有的PoP封装工艺一般是先在下封装体11的封装基板111上植焊球112，然后再用塑封材料113对下封装体11进行整体塑封，塑封后再激光穿孔将焊球112露出，以使焊球112能够与上层封装体12电连接。
本申请的发明人在长期的研发过程中，发现现有工艺不仅复杂，工艺要求高，还存在一定的不足，如植球后共面性较差对后端制程良率影响较大；塑封后激光穿孔有打不透的可能，影响产品良率。
发明内容
本申请主要解决的技术问题是提供一种封装基板、芯片封装体及芯片堆叠封装方法，能够制得稳定性和良品率较高的芯片封装体。
为解决上述技术问题，本申请采用的一个技术方案是：提供一种芯片堆叠封装方法，该方法包括：提供第一封装基板，其中，第一封装基板包括至少一个连接柱，连接柱除上表面外设置有树脂保护层；将至少一个芯片倒装于第一封装基板上，并进行焊接互连，形成第一芯片封装体；提供第二芯片封装体，将第一芯片封装体与第二芯片封装体进行堆叠封装，第一芯片封装体通过连接柱与第二芯片封装体形成电连接。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种封装基板，该封装基板包括至少一个连接柱，连接柱除上表面外设置有树脂保护层，连接柱用于芯片封装体之间的电连接。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种芯片封装体，该芯片封装体通过上述的芯片堆叠封装方法制得。
本申请的有益效果是：区别于现有技术的情况，本申请所提供的芯片堆叠封装方法，因封装基板上预先设置有连接柱，且对连接柱做了保护处理，并裸露了用于电连接的上表面；在进行堆叠封装时，不再需要对芯片封装体进行整体塑封，简化了制作工艺，节约了资源，降低制作成本。同时，连接柱相较于现有的焊球，能够减少I/O电信号传输距离提高处理速度，降低能耗；还能够缩小上、下封装体的互连节距，提升I/O互连数量，提高接触良率和可靠性。
附图说明
图1是现有技术中PoP封装体的侧面结构示意图；
图2是现有技术中PoP封装体的俯视结构示意图；
图3是本申请封装基板第一实施方式的侧面结构示意图；
图4是本申请封装基板第二实施方式的侧面结构示意图；
图5是本申请封装基板的制备方法一实施方式的工艺流程图；
图6是本申请芯片封装体第一实施方式的侧面结构示意图；
图7是本申请芯片堆叠封装方法第一实施方式的流程示意图；
图8是本申请芯片堆叠封装方法第一实施方式中芯片倒装工艺流程示意图；
图9是本申请芯片堆叠封装方法第一实施方式中芯片倒装工艺流程示意图。
具体实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。
本申请提供一种封装基板，该封装基板可作为承载平台用于承载芯片，同时为芯片提供电连接、保护、支撑、散热、组装等。请参阅图3，图3是本申请封装基板第一实施方式的侧面结构示意图。如图3所示，在该实施方式中，封装基板30上设置有至少一个连接柱31，连接柱31在进行芯片堆叠封装时可作为连通机构实现上、下封装体的电连接。
具体地，连接柱31除上表面外设置有树脂保护层32，树脂保护层32用于保护连接柱31不被氧化，还能防止与其他元器件电连接短路等。树脂保护层32的材料可以为环氧树脂，或掺杂有填充料的环氧树脂。连接柱31的上表面裸露于树脂保护层32之外，在进行芯片堆叠封装时，连接柱31可以直接与上封装体进行电连接，而不再需要后续的暴露处理。
请参阅图4，图4是本申请封装基板第二实施方式的侧面结构示意图。在该实施方式中，封装基板40中，连接柱31的上表面设置有抗氧化层33，如图4所示，抗氧化层33完全覆盖连接柱31的上表面，以保护其不被氧化。
为了实现电连接导通作用，连接柱31一般选用金属柱，如铜柱、金柱、银柱等，考虑到制作成本及加工工艺，优选地，连接柱31为铜柱。连接柱31的形状一般选用圆柱形、或底表面积略大于上表面积的形状，具体地，根据芯片封装要求，引脚间距大小等适应性设置。连接柱的高度根据芯片的高度决定，略高于芯片的高度。
为制备上述封装基板，本申请还提供一种封装基板的制备方法。请参阅图5，图5是本申请封装基板的制备方法一实施方式的工艺流程图。如图5所示，在该实施方式中，封装基板的制备方法包括如下步骤：
提供一基板，在基板501上制作完成内部线路，形成线路区502，并将需要堆叠的I/0的引脚引出至电连接区503；然后在基板501上覆盖一层负光阻薄膜504；且于负光阻薄膜504上覆盖一块MASK 505并进行曝光、显影后露出需要长铜柱的开口506；再进行镀铜处理得到铜柱507；最后清洗掉多余的负光阻薄膜，制得封装基板50。
在得到封装基板50后，在铜柱的除上表面之外的位置涂覆树脂形成保护层，制得封装基板30。随后还可以对铜柱裸露的上表面进行抗氧化处理，使铜柱的上表面形成有抗氧化层，最终制得封装基板40。在其他实施方式中，也可以采用其他方法制备带有铜柱的封装基板。
本申请所提供的封装基板可作为承载平台用于承载芯片制备芯片封装体。具体地，本申请还提供一种芯片封装体，该芯片封装体通过PoP封装工艺制备而成，请参阅图6，图6是本申请芯片封装体第一实施方式的侧面结构示意图。在该实施方式中，芯片封装体至少包括层叠封装的第一芯片封装体60和第二芯片封装体61，第一芯片封装体60可以称为下封装体、第二芯片封装体61可以称为上封装体。第一芯片封装体60包括已预先设置好连接柱602的第一封装基板601(下封装基板)，连接柱602的上表面裸露于保护层之外，以与第二芯片封装体下表面上的焊球611进行电连接，其中连接柱602与焊球611对应设置。因第一封装基板上已预先设置好连接柱602，且连接柱602除上表面外设置有树脂保护层603，在将第一芯片封装体60与第二芯片封装体61进行封装之前，不再需要对第一芯片封装体60进行整体塑封，精简了封装工艺，同时还有利于芯片表面的散热。
为制备上述芯片封装体，本申请还提供一种芯片堆叠封装方法，通过该方法能够较便捷的制得性能稳定，良率较高的芯片封装体。请参阅图7，图7是本申请芯片堆叠封装方法第一实施方式的流程示意图，如图7所示，在该实施方式中，芯片堆叠封装方法包括如下步骤：
S701：提供第一封装基板，其中，第一封装基板包括至少一个连接柱，且连接柱除上表面外设置有树脂保护层。
第一封装基板601的具体结构和制备方法请参阅上述相关封装基板实施方式的描述，在此不再赘述。第一封装基板601可通过定制由基板厂商提供，也可以是芯片封装厂商按照上述制备方法自行制备。
S702：将至少一个芯片倒装于第一封装基板上，并进行焊接互连，形成第一芯片封装体。
第一封装基板601的上表面可大致分为芯片封装区和电连接区，其中芯片封装区用于安装芯片，电连接区内设置有连接柱，用于与上封装体进行电连接；芯片封装区一般为基板的线路区，而电连接区则设置在芯片封装区以外的地方。
基板的芯片封装区设置有多个焊盘，该焊盘用于与芯片上的金属凸点配合连接，以实现芯片与基板之间的互连。在一实施方式中，基板可以是适配于某种芯片的特制基板，其焊盘与金属凸点的数量一致，且对应设置；在其他实施方式中，基板也可以是用于芯片封装体制备工艺中的通用型基板，且基板上可同时装配多个芯片(这些芯片可以以并排的方式设置，也可以以堆叠的方式设置)，以同时对多个芯片进行快速封装。因此基板上的焊盘数量可以多于芯片上的金属凸点的数量，只要能够保证芯片上的金属凸点均有对应的焊盘与之匹配连接即可。
具体地，请结合参阅图8和9，图8是本申请芯片堆叠封装方法第一实施方式中芯片倒装工艺流程示意图，图9是本申请芯片堆叠封装方法第一实施方式中芯片倒装工艺流程示意图。如图8、9所示，准备芯片，芯片的正面设置有多个金属凸点801，以与基板上的焊盘(图未示)配合连接，实现芯片与基板之间的互连。将正面设置有金属凸点801的芯片以倒扣方式贴装于基板上，其中金属凸点801与基板上相对应的焊盘配合连接。将贴装后的芯片与基板进行焊接互连，制得第一芯片封装体60。
可选地，在将贴装后的芯片与基板进行焊接互连时，可选择回流焊接的工艺。在焊接完成后，利用毛细底部填充技术或模塑底部填充技术向芯片与基板间的空隙填充树脂胶802，底部填充胶是一种低黏度、低温固化的毛细管流动底部下填料(Underfill)，流动速度快，工作寿命长、翻修性能佳。通过采用底部填充可以分散芯片表面承受的应力进而提高了整个产品的可靠性。
S703：提供第二芯片封装体，将第一芯片封装体与第二芯片封装体进行堆叠封装，第一芯片封装体通过连接柱与第二芯片封装体形成电连接。
第二芯片封装体61可以是预先制备完成的芯片封装体，如通过CSP(Chip ScalePackage，CSP)封装工艺制得的CSP芯片封装体等，也可以是通过上述制备第一芯片封装体60的方法制得。
第二芯片封装体61的下表面设置有焊球611，在将第一芯片封装体60与第二芯片封装体61进行堆叠封装时，第二芯片封装体61上的焊球611与第一芯片封装体60上的连接柱602配合连接，实现第一芯片封装体60与第二芯片封装体61之间的互连。
其中，在将第一芯片封装体60与第二芯片封装体61进行堆叠封装之前不需要对第一芯片封装体60进行整体塑封。
可选地，第二芯片封装体61还堆叠有一个或多个芯片封装体，也就是说该芯片封装体不限于两层结构，封装体的个数可根据实际应用适应性设定。
以上方案，本申请所提供的芯片堆叠封装方法，因封装基板上预先设置有连接柱，且对连接柱做了保护处理，并裸露了用于电连接的上表面；在进行堆叠封装时，不再需要对芯片封装体进行整体塑封，简化了制作工艺，节约了资源，降低制作成本。同时，连接柱相较于现有的焊球，能够减少I/O电信号传输距离提高处理速度，降低能耗；还能够缩小上、下封装体的互连节距，提升I/O互连数量，提高接触良率和可靠性。
以上所述仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (10)

1.一种芯片堆叠封装方法，其特征在于，所述方法包括：
提供第一封装基板，其中，所述第一封装基板包括基板以及设置于所述基板上的至少一个连接柱，所述连接柱除上表面外设置有树脂保护层，且所述树脂保护层仅位于所述连接柱上，所述连接柱的上表面没有经过暴露处理，所述连接柱的上表面包括抗氧化层；
将至少一个芯片倒装于所述第一封装基板上，并进行焊接互连，形成第一芯片封装体；
提供第二芯片封装体，将所述第一芯片封装体与所述第二芯片封装体进行堆叠封装，所述第一芯片封装体通过所述连接柱与所述第二芯片封装体形成电连接。
2.根据权利要求1所述的方法，其特征在于，所述将至少一个芯片倒装于所述第一封装基板上，并进行焊接互连之后还包括：向所述芯片与基板间的空隙填充树脂胶。
3.根据权利要求2所述的方法，其特征在于，所述向芯片与基板间的空隙填充树脂胶包括：利用毛细底部填充技术或模塑底部填充技术向芯片与基板间的空隙填充树脂胶。
4.根据权利要求2所述的方法，其特征在于，所述树脂保护层/树脂胶的材料为环氧树脂，或掺杂有填充料的环氧树脂。
5.根据权利要求1所述的方法，其特征在于，所述连接柱为铜柱，所述第一封装基板的制备方法包括：
提供一基板；
在所述基板上覆盖一层负光阻薄膜；
曝光显影后露出需要设置铜柱的开口；
镀铜得到所述铜柱；
除去多余的负光阻薄膜，得到带有铜柱的封装基板。
6.根据权利要求5所述的方法，其特征在于，所述除去多余的负光阻薄膜，得到带有铜柱的封装基板之后还包括：在所述铜柱的除上表面之外的位置涂覆树脂形成保护层。
7.根据权利要求5所述的方法，其特征在于，所述除去多余的负光阻薄膜，得到带有铜柱的基板之后还包括：对所述铜柱的上表面进行抗氧化处理，形成抗氧化层。
8.根据权利要求1所述的方法，其特征在于，所述第二芯片封装体的上面还堆叠有一个或多个芯片封装体。
9.一种封装基板，其特征在于，所述封装基板包括基板以及设置于所述基板上的至少一个连接柱，所述连接柱用于芯片封装体之间的电连接，所述连接柱除上表面外设置有树脂保护层，且所述树脂保护层仅位于所述连接柱上，所述连接柱的上表面没有经过暴露处理，所述连接柱的上表面包括抗氧化层。
10.一种芯片封装体，其特征在于，所述芯片封装体通过如权利要求1～8任一项所述的芯片堆叠封装方法制得。
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