JP5663607B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5663607B2 JP5663607B2 JP2012556664A JP2012556664A JP5663607B2 JP 5663607 B2 JP5663607 B2 JP 5663607B2 JP 2012556664 A JP2012556664 A JP 2012556664A JP 2012556664 A JP2012556664 A JP 2012556664A JP 5663607 B2 JP5663607 B2 JP 5663607B2
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- Prior art keywords
- electrodes
- electrode
- substrate
- insulating film
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims description 45
- 239000000758 substrate Substances 0.000 claims description 84
- 229910052751 metal Inorganic materials 0.000 claims description 33
- 239000002184 metal Substances 0.000 claims description 33
- 230000004888 barrier function Effects 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 13
- 229910045601 alloy Inorganic materials 0.000 claims description 10
- 239000000956 alloy Substances 0.000 claims description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 78
- 238000000034 method Methods 0.000 description 31
- 238000004519 manufacturing process Methods 0.000 description 23
- 229910000679 solder Inorganic materials 0.000 description 18
- 238000005304 joining Methods 0.000 description 11
- 230000008018 melting Effects 0.000 description 11
- 238000002844 melting Methods 0.000 description 11
- 238000003475 lamination Methods 0.000 description 9
- 230000010354 integration Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 239000007772 electrode material Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000007747 plating Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910020888 Sn-Cu Inorganic materials 0.000 description 1
- 229910019204 Sn—Cu Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
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- H01L2224/81935—Reshaping by heating means, e.g. reflowing
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Description
102、202 バリア層
103、203 シード層
104 レジストパターン
105、106、205、206 導電層
107 第1の電極
108 第1の絶縁膜
201 第1の基板
207 第2の電極
208 第2の絶縁膜
Claims (8)
- 第1の基板と、
前記第1の基板上に形成された複数の第1の電極と、
前記複数の第1の電極のそれぞれの側壁上に形成された第1の絶縁膜と、
第2の基板と、
前記第2の基板上における前記第1の基板上の前記複数の第1の電極のそれぞれと対応する位置に形成された複数の第2の電極と、
前記複数の第2の電極のそれぞれの側壁上に形成された第2の絶縁膜とを備え、
前記第1の絶縁膜は、前記複数の第1の電極の間のスペースが埋まらないように形成されており、
前記第2の絶縁膜は、前記複数の第2の電極の間のスペースが埋まらないように形成されており、
前記第1の基板と前記第2の基板とは、前記複数の第1の電極のそれぞれと前記複数の第2の電極のそれぞれとが対向するように配置されていると共に、前記複数の第1の電極のそれぞれと前記複数の第2の電極のそれぞれとは接合されており、
前記複数の第1の電極のそれぞれの側壁上に形成された前記第1の絶縁膜と、前記複数の第2の電極のそれぞれの側壁上に形成された前記第2の絶縁膜とが接触していることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記複数の第1の電極のそれぞれ及び前記複数の第2の電極のそれぞれは、第1の金属を含む第1の導電層と、前記第1の導電層上に形成され且つ前記第1の金属とは異なる第2の金属を含む第2の導電層とを有することを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記第1の金属は銅であり、
前記第2の金属はスズであることを特徴とする半導体装置。 - 請求項2又は3に記載の半導体装置において、
前記複数の第1の電極のそれぞれ及び前記複数の第2の電極のそれぞれは、前記第1の導電層の下に形成されたバリア層をさらに有することを特徴とする半導体装置。 - 請求項4に記載の半導体装置において、
前記バリア層はチタンを含むことを特徴とする半導体装置。 - 請求項1〜5のいずれか1項に記載の半導体装置において、
前記第1の絶縁膜及び前記第2の絶縁膜は酸化膜又は有機膜であることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記複数の第1の電極及び前記複数の第2の電極は、スズを含む合金を含むことを特徴とする半導体装置。 - 請求項7に記載の半導体装置において、
前記合金は銅を含むことを特徴とする半導体装置。
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PCT/JP2011/004218 WO2012107971A1 (ja) | 2011-02-10 | 2011-07-26 | 半導体装置及びその製造方法 |
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JP5664392B2 (ja) * | 2011-03-23 | 2015-02-04 | ソニー株式会社 | 半導体装置、半導体装置の製造方法、及び配線基板の製造方法 |
US20140124877A1 (en) * | 2012-11-02 | 2014-05-08 | Qualcomm Incorporated | Conductive interconnect including an inorganic collar |
KR20200070446A (ko) * | 2013-06-28 | 2020-06-17 | 인텔 코포레이션 | 미세 피치 재분배 라인들의 보존 |
JPWO2015145886A1 (ja) * | 2014-03-25 | 2017-04-13 | パナソニックIpマネジメント株式会社 | 電極パターンの形成方法及び太陽電池の製造方法 |
WO2015194473A1 (ja) * | 2014-06-20 | 2015-12-23 | Jsr株式会社 | はんだ電極の製造方法、積層体の製造方法、積層体および電子部品 |
KR102458034B1 (ko) | 2015-10-16 | 2022-10-25 | 삼성전자주식회사 | 반도체 패키지, 반도체 패키지의 제조방법, 및 반도체 모듈 |
JP6691031B2 (ja) * | 2016-10-05 | 2020-04-28 | 新光電気工業株式会社 | 配線基板及びその製造方法、半導体パッケージ |
CN108231729B (zh) * | 2017-12-29 | 2020-07-14 | 通富微电子股份有限公司 | 一种封装基板、芯片封装体及芯片堆叠封装方法 |
US10740667B2 (en) * | 2018-03-06 | 2020-08-11 | International Business Machines Corporation | Temperature triggered switch |
US11508704B2 (en) * | 2019-12-17 | 2022-11-22 | Seoul Viosys Co., Ltd. | Method of repairing light emitting device and display panel having repaired light emitting device |
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