CN108417550B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN108417550B
CN108417550B CN201710651125.4A CN201710651125A CN108417550B CN 108417550 B CN108417550 B CN 108417550B CN 201710651125 A CN201710651125 A CN 201710651125A CN 108417550 B CN108417550 B CN 108417550B
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bump
semiconductor device
protective layer
electrode
bump electrode
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CN108417550A (zh
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加本拓
右田达夫
渡边慎也
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Kioxia Corp
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Toshiba Memory Corp
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Abstract

本发明的实施方式提供一种已将衬底接合的可靠性提高的半导体装置及其制造方法。实施方式的半导体装置具有：第一半导体衬底，将第一布线电极设置在表面；第一保护层，形成在所述半导体衬底上，且于所述第一布线电极上具有开口部；第一凸块电极，形成在所述第一保护层的开口部；及凸块，与所述第一凸块电极接合，且凸块直径为30μm以下。形成在所述开口部的所述第一凸块电极的底面直径为所述第一保护层的膜厚的1.5倍以下。

Description

半导体装置及其制造方法
[相关申请]
本申请享有以日本专利申请2017-23207号(申请日：2017年2月10日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置及其制造方法。
背景技术
在半导体装置的制造中，当将形成有半导体装置的衬底经由凸块倒片封装连接于形成有其他半导体装置或布线的衬底时，对于预先形成在一衬底表面的电极，连接设置在另一衬底的凸块。此时，存在将电极预先嵌入地形成在形成于衬底表面的开口部，从而电极表面沿着开口部成为凹形状表面的情形。当将凸块接合于凹形状表面的电极时，存在凹部中卷入空气等气体的可能性，从而出现在接合部位产生空洞的情形。
发明内容
本发明的实施方式提供一种已将衬底接合的可靠性提高的半导体装置及其制造方法。
实施方式的半导体装置具有：第一半导体衬底，将第一布线电极设置在表面；第一保护层，形成在所述半导体衬底上，且在所述第一布线电极上具有开口部；第一凸块电极，形成在所述第一保护层的开口部；及凸块，与所述第一凸块电极接合，且凸块直径为30μm以下。形成在所述开口部的所述第一凸块电极的底面直径为所述第一保护层的膜厚的1.5倍以下。
附图说明
图1是说明实施方式的半导体装置的构成的图。
图2(a)～(c)、及图3(a)～(d)是说明图1的半导体装置的制造方法的图。
图4是说明实施方式的变化例的半导体装置的构成的图。
具体实施方式
以下，对于用以实施发明的实施方式进行说明。
(实施方式)
对于本实施方式的半导体装置，参照图1、图2、及图3进行说明。另外，在以下附图的记载中，同一部分以同一符号表示。但，在附图中，厚度与平面尺寸的关系及比率等是示意性表示而与实际情况不同。
对于本实施方式的半导体装置的构成，使用图1进行说明。图1是表示本实施方式的半导体装置的构成的剖视图。
如图1所示，本实施方式的半导体装置1具备第一半导体装置10与第二半导体装置30，且第一半导体装置10与第二半导体装置30通过导电性凸块20而接合，从而分别电性连接。
第一半导体装置10具备硅衬底等第一半导体衬底100、第一布线电极101、第一保护层102、第一阻挡膜103、及第一凸块电极104。
在第一半导体衬底100，虽分别省略图示，但设置有半导体元件、与元件电性连接的Cu等导电布线层、及层间绝缘层。在第一半导体衬底100的表面，形成有经由布线层而与半导体元件连接的第一布线电极101。第一布线电极101是例如包含Al、Cu、Ni、Au、Ag、或该等的合金的导电体。
在第一布线层101上，形成有绝缘性的第一保护层102。第一保护层102包含例如氧化硅膜、氮化硅膜、及聚酰亚胺等的任一单层或该等多个层。第一保护层102的膜厚为5μm。可通过将第一保护层102的膜厚设为5μm以上，而有效地保护形成在半导体衬底100的半导体元件或布线层等的内部结构。在第一保护层102，在第一布线层101上形成有开口部。
在第一保护层102的开口部的底面及侧面、以及第一保护层102的开口部附近的上部，形成有第一阻挡膜103。第一阻挡膜103包含Ti、TiN、Ta、及TaN等的任一单层或该等的积层，且以均等的膜厚形成。另外，也可视情况而不形成第一阻挡膜103。
在第一阻挡膜103上形成有第一凸块电极104，且第一保护层102的开口部被第一凸块电极104填充。第一凸块电极104包含Cu、Ni、Au、Ag、Pd、Al及该等的合金的任一单层或该等的积层，例如为包含镀Cu晶种层与镀Cu层的积层的Cu柱层。
第一凸块电极104的膜厚为3μm。此处，膜厚是指设置在第一保护层102上的第一凸块电极104的膜厚。多个半导体衬底积层而成的半导体装置可通过将凸块电极104的膜厚设为3μm以下，而抑制各半导体衬底间的距离，从而可将半导体装置整体实现小型化。
第一保护层102的开口部的开口直径为5μm以下。当第一阻挡膜103形成在开口部内部时，优选形成有第一阻挡膜103的开口部的开口直径为5μm以下。即，优选嵌入至开口部中的第一凸块电极104底面直径为5μm以下。此处，嵌入至开口部中的第一凸块电极104底面直径在特定的方向上为5μm以下即可，但更优选在任一方向上均为5μm以下。
当如此地通过缩小开口直径而将第一凸块电极104嵌入地形成于开口部时，便可抑制设置在开口部上部的第一凸块电极104表面的凹下量。此处，第一凸块电极104表面的凹下量设为第一凸块电极104的上层表面的最上部与最下部之差。
若将凸块接合的电极表面的凹下量成为3～5μm以上，则在电极与凸块间或凸块内部卷入空气，从而容易产生空洞。若产生空洞，则凸块接合中的电阻增加，或物理接合可靠性恶化。本实施方式中，可通过将嵌入至开口部中的第一凸块电极104底面的直径设为第一保护层102的膜厚以下，而利用第一凸块电极104将开口部充分地关闭，从而可将第一凸块电极104表面的凹下量抑制为1μm以下。进而，即便将嵌入至开口部中的第一凸块电极104底面的直径设为第一保护层102的膜厚的1.5倍以下，也可将第一凸块电极104表面的凹下量抑制为1.5μm以下。
在第一凸块电极104上，形成有凸块20。凸块20的材料包含Cu、Sn、Pb、Au、Ag、Pd、Ni、或该等的合金。凸块20是凸块直径为30μm以下的微型凸块，而且，可通过将与设置在第一半导体装置10的同一表面侧的至少一个其他凸块的距离(凸块间距)设为60μm以下，而将半导体装置整体实现小型化。
一般而言，当凸块直径为80μm、100μm、150μm或比其更大的大小时，在凸块与凸块电极的接合部位所产生的空洞因与凸块的大小相比相对较小，故较少出现接合可靠性成为问题。相反地，在使用凸块直径为30μm以下的微型凸块的情形时，在凸块与凸块电极的接合部位所产生的空洞因相对于凸块的大小，相对地变大，故容易产生接合可靠性的问题。
本实施方式的半导体装置1是通过一面使用微型凸块实现小型化，一面将第一保护层102的膜厚与第一凸块电极104的直径调整为合适的大小，而抑制第一凸块电极104表面的凹下量，因此，可如图1所示，不使凸块与凸块电极的接合部位中产生空洞，或者可充分地抑制接合部位的空洞的大小，因此，可提高接合可靠性。
可隔着凸块20，将第二半导体装置30与第一半导体装置10接合。
第二半导体装置30具备硅衬底等第二半导体衬底300、第二布线电极301、第二保护层302、第二阻挡膜303、及第二凸块电极304。
在第二半导体衬底300，虽分别省略图示，但设置有半导体元件、与元件电性连接的Cu等导电布线层、及层间绝缘层。在第二半导体衬底300的表面，形成有经由Cu布线层而与半导体元件连接的第二布线电极301。第二布线电极301是例如Ni、Au、Cu、Al等导电材。
在第二布线层301上，形成有绝缘性的第二保护层302。第二保护层302包含例如氧化硅膜、氮化硅膜、及聚酰亚胺等的任一单层或该等的多个层。与第一保护层102相同，可通过将第二保护层302的膜厚设为5μm以上而有效地保护半导体衬底上的元件结构。在第二保护层302，在第二布线层301上部形成有开口部。
在第二保护层302的开口部的底面及侧面、以及第二保护层302的开口部附近的上部，形成有第二阻挡膜303。第二阻挡膜303可采用与第一阻挡膜103相同的材料及结构。而且，也可不必形成第二阻挡膜303。
第二凸块电极304是在第二阻挡膜303上，嵌入至第二保护层302的开口部内。第二凸块电极304是与第一凸块电极104相同的材料或结构，且可通过将其膜厚与第一凸块电极104同样地设为3μm以下而将半导体装置整体实现小型化。
在第二凸块电极304上形成有凸块20，且经由凸块20将半导体装置20与半导体装置10电性及物理性地连接。
接着，对于本实施方式的半导体装置的制造方法，使用图2及图3进行说明。图2及图3是表示本实施方式的半导体装置的制造方法的步骤剖视图。
首先，如图2(a)所示，准备第一半导体装置10的第一半导体衬底100。在第一半导体衬底100虽省略图示，但设置有半导体元件、与元件电性连接的Cu等导电布线层、及层间绝缘层。在第一半导体衬底100的表面，形成经由布线层而与半导体元件电性连接的第一布线电极101。进而，在第一半导体衬底100的表面，以将第一布线电极101覆盖的方式，利用CVD法等形成膜厚5μm的第一保护层102。此后，利用光刻法及干刻蚀，在第一保护层102设置开口直径5μm左右的开口部，使第一布线电极101的一部分自开口部露出。
其次，如图2(b)所示，利用溅射法等将第一阻挡膜103形成在第一保护层102的上表面及开口部的底面及侧面。此后，将光刻胶105形成在第一阻挡膜103上之后，利用光刻法在光刻胶105设置开口部，使第一阻挡膜103的一部分露出。
此后，如图2(c)所示，利用电镀法，在光刻胶105的开口部内露出的阻挡膜103上形成第一凸块电极104，由此，将第一凸块电极104嵌入至第一保护层102的开口部中。第一凸块电极104的材料为Cu，且膜厚设为3μm。此时，在第一保护层102的开口部上方，在第一凸块电极104的表面产生微小的凹部，但凹下量得以抑制。
在形成第一凸块电极104之后，将光刻胶105利用灰化去除，进而也将露出的第一阻挡膜103去除。以上，如图2(a)至图2(c)所示地制造第一半导体装置10。
其次，如图3(a)所示，利用与第一半导体装置10相同的方法，制造第二半导体装置30。准备第二半导体衬底300，分别形成第二布线电极301、第二保护层302、第二阻挡膜303、光刻胶305、及第二凸块电极304。
接着，如图3(b)所示，通过电镀，在光刻胶305的开口部的第二凸块电极304上形成Sn合金等焊料层201。在形成焊料层201之后，将光刻胶305及光刻胶305下方的第二阻挡膜303均去除。
接着，如图3(c)所示，通过热处理将焊料层201熔融，在第二半导体装置30上形成凸块20。凸块20是凸块直径为30μm以下的微型凸块。而且，虽省略图示，但凸块20是多个同时地形成在第二半导体衬底300的同一表面侧，且各个凸块间距离设为60μm以下。
最后，如图3(d)所示，通过热压接合，将形成在第二半导体装置30上的凸块20压抵在第一半导体装置10的第一凸块电极104，随后进行冷却，以此，利用凸块20将第一半导体装置10与第一半导体装置30接合。即便在第一凸块电极104表面形成有凹部，凹部的凹下量也较小，因此，不存在将凸块20压接在第一凸块电极104的过程中卷入空气的可能性，从而不产生空洞，因此，可提高接合可靠性。
另外，作为其他凸块接合技术，也已知有将凸块也预先设置在第一半导体装置上，且将第一半导体装置上的凸块与第二半导体装置上的凸块接合的技术。与此相对，本实施方式的半导体装置的制造方法因仅在第二半导体装置上形成凸块且与第一半导体装置接合，因此，可减少焊料使用量。
图4是表示本实施方式的半导体装置的构成的变化例的图。如图4所示，本变化例的半导体装置具有在图1所示的半导体装置的第二半导体装置30上隔着凸块40进而积层第三半导体装置50所得的构成。
第二半导体装置30是在第二半导体衬底300内形成有沿衬底贯通方向延伸的导电性通孔306。通孔306包含Cu等导体材料，且在第一半导体装置10侧的端部，与第二布线电极301电性连接。而且，通孔306也在相反侧的端部，与第二布线电极307电性连接。
在第二布线电极307上，以与第一半导体装置10中的第一保护层102、第一阻挡膜103、及第一凸块电极104相同的构成、材料、尺寸、配置，设置有第二保护层308、第二阻挡膜309、及第二凸块电极310。此处，，第二凸块电极310表面的凹下量与第一凸块电极104表面的凹下量同样地得以充分地抑制。
在第二凸块电极310上接合着导电性凸块40，进而在凸块40上接合着第三半导体装置50。第三半导体装置50的构成是与第二半导体装置30的构成、材料、尺寸、配置相同，具备硅衬底等第三半导体衬底500、第三布线电极501、第三保护层502、第三阻挡膜503、及第三凸块电极504。凸块40将第二凸块电极310与第三凸块电极504间接合，确立第二半导体装置30与第三半导体装置50的电性连接。
以上说明的本变化例的半导体装置可通过设置沿半导体衬底的贯通方向延伸的通孔，而一面紧凑地保持积层而成的3个以上半导体装置，一面实现各自的电性连接。而且，因将凸块接合中的空洞的产生抑制，故可提高接合可靠性。
以上，说明了本发明的实施方式，但本实施方式是作为范例而提示，并无限定发明范围的意图。新颖的实施方式可利用其他各种方式实施，且可在不脱离发明要点的范围内，进行各种省略、置换、变更。该等实施方式或其变化包含于发明的范围或要点中，并且包含于与权利请求的范围中记载的发明及其均等的范围中。
[符号的说明]
1 半导体装置
10 第一半导体装置
20、40 凸块
30 第二半导体装置
50 第三半导体装置
100 第一半导体衬底
101 第一布线电极
102 第一保护层
103 第一阻挡膜
104 第一凸块电极
300 第二半导体衬底
301、307 第二布线电极
302、308 第二保护层
303、309 第二阻挡膜
304、310 第二凸块电极
306 通孔
500 第三半导体衬底
501 第三布线电极
502 第三保护层
503 第三阻挡膜
504 第三凸块电极

Claims (5)

1.一种半导体装置，其特征在于具有：
第一半导体衬底，将第一布线电极设置在表面；
第一保护层，形成在所述半导体衬底上，且在所述第一布线电极上具有开口部；
第一凸块电极，形成在所述第一保护层的开口部；及
凸块，与所述第一凸块电极接合，且凸块直径为30μm以下；
形成在所述开口部的所述第一凸块电极的底面直径为所述第一保护层的膜厚的1.5倍以下，
所述第一凸块电极在表面形成有凹部，
所述第一凸块电极的上层表面的最上部与最下部之差为1.5μm以下，
所述第一保护层的膜厚为5μm以上。
2.根据权利要求1所述的半导体装置，其中形成在所述开口部的所述第一凸块电极的底面直径为所述第一保护层的膜厚以下。
3.根据权利要求1或2所述的半导体装置，其中所述第一凸块电极也形成在所述第一保护层上，且所述第一保护层上的所述第一凸块电极的膜厚为3μm以下。
4.根据权利要求1或2所述的半导体装置，其中所述凸块与设置在所述第一半导体衬底的同一表面侧的其他凸块的距离为60μm以下。
5.一种半导体装置的制造方法，其特征在于：
准备在表面具备具有开口部的第一保护层、及形成在所述开口部的第一凸块电极的半导体衬底，且
在所述第一凸块电极接合凸块直径为30μm以下的凸块，
形成在所述开口部的所述第一凸块电极的底面直径为所述第一保护层的膜厚的1.5倍以下，
所述第一凸块电极在表面形成有凹部，
所述第一凸块电极的上层表面的最上部与最下部之差为1.5μm以下，
所述第一保护层的膜厚为5μm以上。
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