JP5788350B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP5788350B2 JP5788350B2 JP2012066739A JP2012066739A JP5788350B2 JP 5788350 B2 JP5788350 B2 JP 5788350B2 JP 2012066739 A JP2012066739 A JP 2012066739A JP 2012066739 A JP2012066739 A JP 2012066739A JP 5788350 B2 JP5788350 B2 JP 5788350B2
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- insulating film
- interlayer insulating
- film
- semiconductor device
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Description
図1から図3を用い、第1の実施形態に係る半導体装置SDの構成について説明する。この半導体装置SDは、Si、O、CおよびHを含む層間絶縁膜IL1と、層間絶縁膜IL1上に設けられ、Niを含むアンダーバンプメタル膜UBMと、アンダーバンプメタル膜UBM上に設けられたバンプ電極BEと、を備えている。層間絶縁膜IL1のうち、FTIR法によって求められる、波数1030cm−1近傍のSi−Oのピーク高さに対する波数1270cm−1近傍のSi−CH3のピーク高さの比率は0.15以上0.27以下である。また、波数1270cm−1近傍のSi−CH3のピーク高さに対する波数1360cm−1近傍のSi−CH2−Siのピーク高さの比率は0.031以上である。以下、詳細を説明する。
第2の実施形態は、層間絶縁膜IL1のSi−CH3/Si−Oの比率とSi−CH2−Si/Si−CH3の比率とがさらに限定された範囲内である点を除いて、第1の実施形態と同様である。以下、詳細を説明する。
SC 半導体チップ
SUB 半導体基板
LL ローカル配線層
GL グローバル配線層
IL1 層間絶縁膜
IC1 配線
BL1 拡散防止層
IL2 層間絶縁膜
IC2 配線
BL2 拡散防止層
CPL 保護層
CML 金属膜
UBM アンダーバンプメタル膜
BE バンプ電極
DIR 素子分離領域
SR ソース領域
DR ドレイン領域
ER エクステンション領域
GI ゲート絶縁層
GE ゲート電極
SWI 側壁絶縁膜
ILU 下部絶縁膜
VAU コンタクトプラグ
ICU 配線
VA ビア
IP 回路基板
UDF アンダーフィル樹脂
LID リッド
SLB はんだボール
Claims (8)
- Si、O、CおよびHを含む層間絶縁膜と、
前記層間絶縁膜上に設けられ、Niを含むアンダーバンプメタル膜と、
前記アンダーバンプメタル膜上に設けられたバンプ電極と、
を備え、
前記層間絶縁膜のうち、FTIR(Fourier Transform Infrared Spectroscopy)法によって求められる、波数1030cm−1近傍のSi−Oのピーク高さに対する波数1270cm−1近傍のSi−CH3のピーク高さの比率は0.15以上0.27以下であり、
波数1270cm−1近傍のSi−CH3のピーク高さに対する波数1360cm−1近傍のSi−CH2−Siのピーク高さの比率は0.031以上である半導体装置。 - 請求項1に記載の半導体装置において、
前記Si−Oのピーク高さに対する前記Si−CH3のピーク高さの比率は0.16以上0.24以下であり、
前記Si−CH3のピーク高さに対する前記Si−CH2−Siのピーク高さの比率は0.033以上である半導体装置。 - 請求項1に記載の半導体装置において、
前記アンダーバンプメタル膜の厚さは、1.5μm以上3.0μm以下である半導体装置。 - 請求項1に記載の半導体装置において、
前記バンプ電極は、SnおよびAgを含む半導体装置。 - 請求項1に記載の半導体装置において、
前記バンプ電極の高さは、50μm以上100μm以下である半導体装置。 - 請求項1に記載の半導体装置において、
前記層間絶縁膜の比誘電率は、2.5以上3.2以下である半導体装置。 - Si、O、CおよびHを含む層間絶縁膜を形成する層間絶縁膜形成工程と、
前記層間絶縁膜上に、Niを含むアンダーバンプメタル膜を形成する工程と、
前記アンダーバンプメタル膜上にバンプ電極を形成する工程と、
を備え、
前記層間絶縁膜形成工程において、
FTIR(Fourier Transform Infrared Spectroscopy)法によって求められる、波数1030cm−1近傍のSi−Oのピーク高さに対する波数1270cm−1近傍のSi−CH3のピーク高さの比率は0.15以上0.27以下であり、
波数1270cm−1近傍のSi−CH3のピーク高さに対する波数1360cm−1近傍のSi−CH2−Siのピーク高さの比率は0.031以上である前記層間絶縁膜を形成する半導体装置の製造方法。 - 請求項7に記載の半導体装置の製造方法において、
前記アンダーバンプメタル膜を形成する工程において、前記アンダーバンプメタル膜の厚さを1.5μm以上3.0μm以下にする半導体装置の製造方法。
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JP2012066739A JP5788350B2 (ja) | 2012-03-23 | 2012-03-23 | 半導体装置および半導体装置の製造方法 |
TW101147929A TWI593070B (zh) | 2012-03-23 | 2012-12-17 | 半導體裝置及半導體裝置之製造方法 |
US13/767,446 US8736051B2 (en) | 2012-03-23 | 2013-02-14 | Semiconductor device and manufacturing method thereof |
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JP2004253791A (ja) * | 2003-01-29 | 2004-09-09 | Nec Electronics Corp | 絶縁膜およびそれを用いた半導体装置 |
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