TW201340271A - 半導體裝置及半導體裝置之製造方法 - Google Patents

半導體裝置及半導體裝置之製造方法 Download PDF

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Publication number
TW201340271A
TW201340271A TW101147929A TW101147929A TW201340271A TW 201340271 A TW201340271 A TW 201340271A TW 101147929 A TW101147929 A TW 101147929A TW 101147929 A TW101147929 A TW 101147929A TW 201340271 A TW201340271 A TW 201340271A
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Prior art keywords
insulating film
interlayer insulating
film
ratio
wave number
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TW101147929A
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English (en)
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TWI593070B (zh
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Tatsuya Usami
Tomoyuki Nakamura
Naoki Fujimoto
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Renesas Electronics Corp
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Abstract

本發明之課題在於提供一種具有膜強度較高之層間絕緣膜之半導體裝置。本發明之半導體裝置SD包括：層間絕緣膜IL1，其含有Si、O、C及H；凸塊下金屬膜UBM，其係設置於層間絕緣膜IL1上且含有Ni；及凸塊電極BE，其係設置於凸塊下金屬膜UBM上。層間絕緣膜IL1中之藉由FTIR(Fourier Transform Infrared Spectroscopy)法而求出之波數1270 cm-1附近之Si-CH3之峰高度相對於波數1030 cm-1附近之Si-O之峰高度的比率為0.15以上且0.27以下。又，波數1360 cm-1附近之Si-CH2-Si之峰高度相對於波數1270 cm-1附近之Si-CH3之峰高度的比率為0.031以上。

Description

半導體裝置及半導體裝置之製造方法
本發明係關於一種半導體裝置及半導體裝置之製造方法。
近年來，為提高半導體裝置之可靠性，而提出有各種半導體裝置之結構。
於專利文獻1(日本專利特表2008-530821號公報)中，記載有如下所述之介電體材料作為半導體裝置之層間絕緣膜。介電體材料含有Si、C、O及H之原子，且具有立體網狀結構。藉由FTIR(Fourier Transform Infrared Spectroscopy，傅立葉轉換紅外光譜)法而求出之關於CH2或CH3伸縮、SiH伸縮及SiCH3鍵之峰面積處於由介電體膜之厚度而標準化之特定之範圍內。又，介電體材料之多孔率大於20%。藉此，可提供表現出良好之電子特性及機械特性之低介電係數之介電體膜。
於專利文獻2(日本專利特開2006-237278號公報)中記載有如下所述之具有凸塊電極之半導體裝置。半導體裝置包括：焊墊電極、凸塊下金屬膜及Au凸塊電極。凸塊下金屬膜包括TiW膜及Au膜。凸塊下金屬膜之TiW膜及Au膜之厚度係滿足特定之關係式。藉此，於倒裝晶片接合步驟中，可抑制於凸塊下金屬膜上產生龜裂之情況。
[先前技術文獻] [專利文獻]
[專利文獻1]
日本專利特表2008-530821號公報
[專利文獻2]
日本專利特開2006-237278號公報
存在因施加於電極上之應力而導致於位於電極之下方之層間絕緣膜上產生龜裂等不良現象的可能性。為了應對該問題，需要相對於施加於電極上之應力具有耐性之膜強度較高之層間絕緣膜。其他課題及新穎之特徵係根據本發明書之記述及隨附圖式而明確。
根據一實施形態，該半導體裝置包括：層間絕緣膜，其含有Si、O、C及H；凸塊下金屬膜，其係設置於層間絕緣膜上且含有Ni；及凸塊電極，其係設置於凸塊下金屬膜上。層間絕緣膜中之、藉由FTIR法而求出之、波數1270 cm-1附近之Si-CH3之峰高度相對於波數1030 cm-1附近之Si-O之峰高度的比率為0.15以上且0.27以下。又，波數1360 cm-1附近之Si-CH2-Si之峰高度相對於波數1270 cm-1附近之Si-CH3之峰高度的比率為0.031以上。
根據一實施形態，該半導體裝置之製造方法包括以下步驟。形成含有Si、O、C及H之層間絕緣膜(層間絕緣膜形成步驟)。於層間絕緣膜上形成含有Ni之凸塊下金屬膜。於凸塊下金屬膜上形成凸塊電極。於層間絕緣膜形成步驟 中，形成如下所述之層間絕緣膜，即，藉由FTIR法而求出之、波數1270 cm-1附近之Si-CH3之峰高度相對於波數1030 cm-1附近之Si-O之峰高度的比率為0.15以上且0.27以下，波數1360 cm-1附近之Si-CH2-Si之峰高度相對於波數1270 cm-1附近之Si-CH3之峰高度的比率為0.031以上。
根據上述一實施形態，可提供一種具有膜強度較高之層間絕緣膜之半導體裝置。
以下，使用圖式對本發明之實施形態進行說明。再者，於全部之圖式中，對於相同之構成要素標註相同之符號，並適當地省略說明。
(第1實施形態)使用圖1至圖3，對第1實施形態之半導體裝置SD之構成進行說明。該半導體裝置SD包括：層間絕緣膜IL1，其含有Si、O、C及H；凸塊下金屬膜UBM，其係設置於層間絕緣膜IL1上且含有Ni；及凸塊電極BE，其係設置於凸塊下金屬膜UBM上。層間絕緣膜IL1中之，藉由FTIR法而求出之、波數1270 cm-1附近之Si-CH3之峰高度相對於波數1030 cm-1附近之Si-O之峰高度的比率為0.15以上且0.27以下。又，波數1360 cm-1附近之Si-CH2-Si之峰高度相對於波數1270 cm-1附近之Si-CH3之峰高度的比率為0.031以上。以下，對詳情進行說明。
圖1及圖3係表示第1實施形態之半導體裝置SD之構成的剖面圖。圖1係表示經切割之半導體晶片SC之一部分。圖2 係將圖1之A部放大而成之剖面圖。圖3係表示封裝後之半導體裝置SD。
如圖2所示，於半導體基板SUB上設置有具有開口部(未標示符號)之元件分離區域DIR。如下所述，於該開口部上形成有例如MISFET(Metal Insulator Semiconductor Field Effect Transistor，金屬絕緣半導體場效應電晶體)。
半導體基板SUB例如為矽基板。元件分離區域DIR例如為SiO2。元件分離區域DIR係可藉由例如LOCOS(Local Oxidation of Silicon，矽局部氧化)法而形成。或者，元件分離區域DIR亦可藉由STI(Shallow Trench Isolation，淺溝槽隔離)法而形成。
於半導體基板SUB中之、在俯視時彼此離開之位置上設置有源極區域SR及汲極區域DR。與源極區域SR接觸而設置有源極側之延長區域ER，與汲極區域DR接觸而設置有汲極側之延長區域ER。
於夾持於延長區域ER之區域上設置有閘極絕緣層GI。閘極絕緣層GI例如為SiO2、SiON。或者，閘極絕緣層GI例如亦可為含有Hf之高介電係數膜。
於閘極絕緣層GI上設置有閘極電極GE。閘極電極GE例如為多晶矽。或者，閘極電極GE例如亦可為Ti、Ta、Mo、該等之合金、該等金屬之氮化物、或該等金屬與矽之氮化物。
於閘極絕緣層GI及閘極電極GE之側壁上設置有側壁絕緣膜SWI。此外，於半導體基板SUB、閘極電極GE及側壁 絕緣膜SWI上亦可設置有襯絕緣膜(未圖示)。
如圖2所示，於半導體基板SUB、元件分離區域DIR及閘極電極GE上設置有下部絕緣膜ILU。下部絕緣膜ILU亦可藉由與下述層間絕緣膜IL1不同之材料而形成。
於下部絕緣膜ILU上例如與源極區域SR或汲極區域DR接觸而設置有接觸插塞VAU。又，於未圖示之區域中，於下部絕緣膜ILU上與閘極電極GE接觸而設置有接觸插塞VAU。接觸插塞VAU含有例如W(鎢)。於接觸插塞VAU之側面及底面亦可設置有障壁金屬層(未圖示)。
於下部絕緣膜ILU上設置有層間絕緣膜IL1。層間絕緣膜IL1例如為下述之SiCOH膜。於層間絕緣膜IL1上藉由例如單層金屬鑲嵌法而設置有配線ICU。配線ICU係經由接觸插塞VAU而連接於源極區域SR、汲極區域DR或閘極電極GE。配線ICU含有Cu(銅)。
於層間絕緣膜IL1上進而設置有複數個層間絕緣膜IL1。於上層之層間絕緣膜IL1上藉由例如雙道金屬鑲嵌法而設置有配線IC1及通孔VA。配線IC1及通孔VA含有Cu。於配線IC1及通孔VA之側面及底面亦可設置有障壁金屬層(未圖示)。
如圖1所示，於半導體基板SUB上形成有多層配線層。多層配線層包括局部配線層LL及全局配線層GL。局部配線層LL係用以形成電路之配線層，全局配線層GL係用以引繞電源配線及接地配線之配線層。
如上所述，於局部配線層LL上設置有層間絕緣膜IL1。 關於層間絕緣膜IL1之詳情於以下敍述。於局部配線層LL之層間絕緣膜IL1上設置有配線IC1或通孔(未圖示)。
於局部配線層LL之各配線層之間亦可設置有防擴散層BL1。防擴散層BL1例如為SiCN、SiC、SiON、SiCO、SiCON或SiN。
於局部配線層LL之上方設置有全局配線層GL。於全局配線層GL上設置有層間絕緣膜IL2。層間絕緣膜IL2係藉由例如較層間絕緣膜IL1更高密度之材料而形成。層間絕緣膜IL2例如為SiO2、SiOF。
於全局配線層GL之層間絕緣膜IL2上設置有配線IC2或通孔(未圖示)。配線IC2係經由例如通孔而連接於局部配線層LL之配線IC1。於全局配線層GL之各配線層之間亦可設置有防擴散層BL2。
全局配線層GL中之至少位於較最上層更下層之配線IC2或通孔係藉由金屬鑲嵌法而形成。配線IC2及通孔含有Cu。
於全局配線層GL之最上層設有與電極(BE等)接觸之金屬膜CML。金屬膜CML具有作為凸塊電極BE之基座之功能。金屬膜CML例如含有Al。金屬膜CML係經由通孔而連接於位於下層之配線IC2。
於全局配線層GL上設置有保護層CPL。保護層CPL例如為聚醯亞胺。於保護層CPL中之在俯視時與金屬膜CML重疊之位置設置有開口部(未標示符號)。
於開口部設置有凸塊下金屬膜UBM。凸塊下金屬膜 UBM係藉由可抑制構成凸塊電極BE之材料遷移之材料而形成。具體而言，凸塊下金屬膜UBM例如為Ni。
於凸塊下金屬膜UBM上設置有凸塊電極BE。凸塊電極BE係藉由無Pb焊錫材料而形成。此處，凸塊電極BE例如含有Sn及Ag。又，凸塊電極BE之高度為50 μm以上且100 μm以下。可藉由凸塊電極BE為如上所述之構成而將半導體晶片SC穩定地覆晶安裝於電路基板IP上。又，下述之施加於位於凸塊電極BE之下方之層間絕緣膜IL1上之應力係取決於凸塊電極BE之材料、或凸塊電極BE之高度(或體積)。發明者等人確認：於至少凸塊電極BE為如上所述之構成之情形時，可藉由層間絕緣膜IL1具有下述組成而抑制層間絕緣膜IL1之不良。再者，凸塊電極BE之構成並不限定於上述，即便為除上述以外之構成，亦可獲得與第1實施形態相同之效果。
如圖3所示，半導體裝置SD例如為BGA(Ball Grid Array，球狀柵格陣列)型封裝。半導體晶片SC係可藉由例如覆晶安裝而搭載於電路基板IP上。於半導體晶片SC與電路基板IP之間注入有底層填充樹脂UDF。
於電路基板IP及半導體晶片SC上設置有具有凹部之蓋LID。蓋LID之外周部係與電路基板IP接觸。又，蓋LID之凹部之內面係與半導體晶片SC之上表面接觸。蓋LID、電路基板IP及半導體晶片SC係經由接著劑(未圖示)而得以固定。又，於電路基板IP之下表面側設置有焊錫球SLB。
再者，半導體裝置SD之封裝並不限定於BGA型，亦可為 其他封裝形態。
繼而，使用圖4對凸塊下金屬膜UBM之膜厚進行說明。圖4係表示凸塊下金屬膜UBM之厚度與電遷移壽命之關係的圖。圖4係表示於特定之條件下對凸塊下金屬膜UBM之膜厚不同之複數個半導體裝置SD進行電遷移試驗的結果。
圖4之橫軸係表示含有Ni之凸塊下金屬膜UBM之膜厚。圖4之縱軸係以任意單位(a.u.)表示於各個半導體裝置SD中因電遷移而產生不良現象之樣本數成為投入試驗之總樣本數之50%時之時間(T50)。圖中之粗虛線係表示特定之製品之可靠性標準。
如圖4所示，存在如下傾向：伴隨凸塊下金屬膜UBM之膜厚變厚，電遷移壽命(T50)變長。於凸塊下金屬膜UBM之膜厚較薄之情形時，於試驗中凸塊下金屬膜UBM之材料易遷移。其結果，於凸塊下金屬膜UBM上產生空隙。因此，於凸塊下金屬膜UBM之膜厚較薄之情形時，電遷移壽命較短。相對於此，由於凸塊下金屬膜UBM之膜厚較厚之情形與膜厚較薄之情形相比，體積較大，因此伴隨空隙之產生之電阻變化較小。因此，凸塊下金屬膜UBM之膜厚越厚電遷移壽命越長。
此處，於第1實施形態中，凸塊下金屬膜UBM之膜厚例如為1.5 μm以上且3.0 μm以下。可藉由凸塊下金屬膜UBM之膜厚為1.5 μm以上而使電遷移壽命為特定之製品之可靠性標準以上。可藉由凸塊下金屬膜UBM之膜厚為3.0 μm以下而使凸塊電極BE與位於下方之金屬膜CML之接觸電阻 降低。
另一方面，發明者等人發現：於凸塊下金屬膜UBM之膜厚較厚之情形時，因施加於凸塊電極BE上之應力而導致於位於凸塊電極BE之下方之層間絕緣膜IL1上產生如下所述之不良現象。凸塊下金屬膜UBM係藉由較凸塊電極BE更硬之材料而形成。例如於安裝步驟中或於安裝步驟後，於應力被施加於凸塊電極BE上時，因凸塊下金屬膜UBM而應力未得以緩和。因此，於層間絕緣膜IL1上亦施加有應力。此時，存在於位於凸塊電極BE之下方之層間絕緣膜IL1上產生龜裂等不良現象的可能性。
例如於層間絕緣膜IL1之膜強度較低之情形時，即便凸塊下金屬膜UBM之膜厚為1.5 μm以上，亦存在產生龜裂之情形。又，伴隨凸塊下金屬膜UBM之膜厚變厚，而存在層間絕緣膜IL1之不良產生率上升之傾向。
如此，存在如下課題：難以兼顧對構成凸塊電極BE之材料之遷移進行抑制及對層間絕緣膜IL1之不良現象進行抑制。
因此，於第1實施形態中，層間絕緣膜IL1係如下所述藉由FTIR法而求出之Si-CH3/Si-O之比率及Si-CH2-Si/Si-CH3之比率為特定之範圍內。藉此，可獲得膜強度較高之層間絕緣膜。進而，即便凸塊下金屬膜UBM之膜厚為1.5 μm以上且3.0 μm以下，亦可藉由施加於凸塊電極BE上之應力而減少於位於凸塊電極BE之下方之層間絕緣膜上產生之龜裂等之不良產生率。
繼而，對第1實施形態之層間絕緣膜IL1之特性之詳情進行說明。層間絕緣膜IL1含有Si(矽)、O(氧)、C(碳)及H(氫)。再者，層間絕緣膜IL1並非多孔膜。以下，將用作層間絕緣膜IL1之膜記為「SiCOH膜」。
於第1實施形態中，用作層間絕緣膜IL1之SiCOH膜之比介電係數為2.5以上且3.2以下。藉此，可降低配線間電容。
為了獲得具有如上所述之比介電係數之SiCOH膜，而層間絕緣膜IL1中必需取得特定之含量以上之C(碳)原子。發明者等人發現：滿足上述比介電係數之SiCOH膜係於FTIR光譜中具有如下所述之特性。具體而言，藉由FTIR法而求出之、波數1270 cm-1附近之Si-CH3之峰高度相對於波數1030 cm-1附近之Si-O之峰高度的比率(Si-CH3/Si-O之比率)為0.15以上且0.27以下。藉此，可獲得比介電係數為2.5以上且3.2以下之層間絕緣膜IL1。
進而，發明者等人發現：於FTIR光譜中，於如下所述之範圍內可獲得膜強度(下述破裂耐壓)較高之SiCOH膜。具體而言，藉由FTIR法而求出之、波數1360 cm-1附近之Si-CH2-Si之峰高度相對於波數1270 cm-1附近之Si-CH3之峰高度的比率(Si-CH2-Si/Si-CH3之比率)為0.031以上。以下，對詳情進行說明。
此處，將比介電係數為2.5以上且3.2以下之SiCOH膜中之、膜強度相對較低者作為「比較例」，並將膜強度相對較高者作為「第1實施形態」而進行說明。
圖5至圖7係對單層之SiCOH膜進行FTIR測定之結果。圖5係表示波數為2700 cm-1以上且3100 cm-1以下之SiCOH膜之FTIR光譜的圖。如圖5所示，檢測於波數2950 cm-1附近因CH2或CH3而引起之峰。於該例中，第1實施形態中之CH2或CH3之峰形狀係與比較例大致相同。
圖6係表示波數為1240 cm-1以上且1300 cm-1以下之SiCOH膜之FTIR光譜的圖。如圖6所示，檢測於波數1270 cm-1附近因Si-CH3而引起之峰。於該例中，第1實施形態中之Si-CH3之峰形狀係與比較例大致相同。
圖7係表示波數為1345 cm-1以上且1380 cm-1以下之SiCOH膜之FTIR光譜的圖。如圖7所示，檢測於波數1360 cm-1附近因Si-CH2-Si而引起之峰。
波數1360 cm-1附近之因Si-CH2-Si而引起之峰並非利用上述專利文獻1(日本專利特表2008-530821號公報)中記載之介電體膜而檢測(參照專利文獻1之例如圖7)。
尤其是關於該Si-CH2-Si之峰，比較例之膜與第1實施形態之間產生了較明確之差。第1實施形態之Si-CH2-Si之峰高度高於比較例。可知該Si-CH2-Si之峰高度與SiCOH膜之膜強度相關。
圖8係表示Si-CH3/Si-O之比率為0.15以上且0.27以下時之Si-CH2-Si/Si-CH3之比率與SiCOH膜之破裂耐壓之關係的圖。
圖8之橫軸係表示藉由FTIR法而求出之、波數1360 cm-1附近之Si-CH2-Si之峰高度相對於波數1270 cm-1附近之Si- CH3之峰高度的比率(Si-CH2-Si/Si-CH3之比率)。再者，於藉由FTIR而檢測之光譜中之去除背景後之光譜中，求出峰高度之比率。必需注意並非峰面積比率之情況。又，繪製之點上所附記之數值係表示該點之Si-CH2-Si/Si-CH3之數值。
圖8之縱軸係表示藉由奈米壓痕法而測定之SiCOH膜之破裂耐壓Kc(單位MPa．m1/2)。再者，破裂耐壓Kc之測定係使用奈米壓痕儀。又，對單層之SiCOH膜進行測定。
此處，破裂耐壓Kc(單位MPa．m1/2)係可藉由下述式(1)而求出。
α係奈米壓痕儀之壓頭之常數，於三角錐壓頭之情形時為0.016。E為SiCOH膜之楊氏模數，H為SiCOH膜之硬度，P為奈米壓痕儀之最大負重，c為於藉由奈米壓痕儀壓頭而壓入後SiCOH膜上所產生之龜裂長度。
上述之圖5至圖7中作為比較例而表示之SiCOH膜係於圖8中Si-CH2-Si/Si-CH3之比率未達0.031之膜之其中之一。相對於此，作為第1實施形態而表示之SiCOH膜係Si-CH2-Si/Si-CH3之比率為0.031以上之膜之其中之一。
如圖8所示，伴隨Si-CH2-Si/Si-CH3之比率增加，而SiCOH膜之破裂耐壓亦變高。將Si-CH2-Si/Si-CH3之比率為0.031之位置作為邊界，而破裂耐壓急遽地上升。Si-CH2- Si/Si-CH3之比率為0.031以上之情形與該比率未達0.031之情形相比，破裂耐壓較高。
繼而，使用圖9，對因Si-CH2-Si較多而破裂耐壓上升之機制進行說明。圖9係用以說明SiCOH膜中之鍵之模式圖。圖9(a)係表示Si-CH3鍵模式。圖9(b)係表示Si-CH2-Si鍵模式。
如圖9(a)所示，若為Si-CH3鍵支配之SiCOH膜，則起因於例如Si之原料之甲基配位於Si而終止。因此，若為Si-CH3鍵支配之SiCOH膜，則Si彼此之鍵較弱。
另一方面，如圖9(b)所示，若為包含Si-CH2-Si鍵之SiCOH膜，則鄰接之Si原子經由CH2而交聯。藉此，可獲得牢固且穩定之SiCOH膜。因此，認為：於Si-CH2-Si/Si-CH3之比率為0.031以上之情形時，破裂耐壓較高。
如上所述，根據第1實施形態，關於用作層間絕緣膜IL1之SiCOH膜，藉由FTIR法而求出之Si-CH2-Si/Si-CH3之比率為0.031以上。藉此，可獲得具有較高之膜強度之層間絕緣膜IL1。因此，可減少於位於凸塊電極BE之下方之層間絕緣膜IL1上產生之龜裂等之不良產生率。
再者，於半導體裝置SD中，較佳為至少局部配線層LL之層間絕緣膜IL1具有上述之Si-CH2-Si/Si-CH3之比率。再者，全局配線層GL之層間絕緣膜IL2亦可具有上述之Si-CH2-Si/Si-CH3之比率。
繼而，再次使用圖1至圖3，對第1實施形態之半導體裝置SD之製造方法進行說明。第1實施形態之半導體裝置SD 之製造方法包括以下步驟。形成含有Si、O、C及H之層間絕緣膜IL1(層間絕緣膜形成步驟)。於層間絕緣膜IL1上形成含有Ni之凸塊下金屬膜UBM。於凸塊下金屬膜UBM上形成凸塊電極BE。於層間絕緣膜形成步驟中，形成如下所述之層間絕緣膜IL1：藉由FTIR法而求出之波數1270 cm-1附近之Si-CH3之峰高度相對於波數1030 cm-1附近之Si-O之峰高度的比率為0.15以上且0.27以下，波數1360 cm-1附近之Si-CH2-Si之峰高度相對於波數1270 cm-1附近之Si-CH3之峰高度的比率為0.031以上。以下，對詳情進行說明。
首先，如圖2所示，於半導體基板SUB上形成具有開口部之元件分離區域DIR。繼而，於半導體基板SUB上形成閘極絕緣層GI及閘極電極GE。繼而，將閘極絕緣層GI及閘極電極GE作為遮罩，而藉由離子植入而形成延長區域ER。繼而，於閘極絕緣層GI及閘極電極GE之側壁形成側壁絕緣膜SWI。繼而，將側壁絕緣膜SWI、閘極絕緣層GI及閘極電極GE作為遮罩，而藉由離子植入形成源極區域SR及汲極區域DR。
繼而，可藉由例如CVD(Chemical Vapor Deposition，化學氣相沈積)法而於半導體基板SUB、元件分離區域DIR、側壁絕緣膜SWI及閘極電極GE上形成下部絕緣膜ILU。繼而，於下部絕緣膜ILU形成接觸孔(未標示符號)。繼而，藉由例如CVD而於接觸孔內及下部絕緣膜ILU上形成含有W之金屬膜。繼而，藉由CMP(Chemical Mechanical Polishing，化學機械拋光法)而將下部絕緣膜ILU之上部平 坦化。藉此，於下部絕緣膜ILU上形成接觸插塞VAU。
繼而，如圖1所示，形成具有配線IC1及通孔之局部配線層LL。此時，以下述之方式形成含有Si、O、C及H之層間絕緣膜IL1(層間絕緣膜形成步驟)。
於層間絕緣膜形成步驟中，藉由例如平行平板型電漿CVD而形成SiCOH膜作為層間絕緣膜IL1。作為Si原料，例如使用三甲基矽烷。再者，Si原料並不限定於此，亦可為四甲基矽烷、TEOS(Tetraethyl Orthosilicate，原矽酸四乙酯)等。
層間絕緣膜形成步驟中之成膜條件較佳為低壓力或高功率。藉此，提高相對於Si原料之功率效率。此時，Si原料之烴基被分解，而形成Si-CH2-Si鍵。因此，可藉由於低壓力或高功率下形成層間絕緣膜IL1而較容易地形成Si-CH2-Si鍵。
又，較佳為Si原料之相對於總氣體流量之流量比較高。藉此，可使取得C(碳)原子之機率上升。此外，於成膜時亦可將半導體基板SUB加熱。
可藉由調整層間絕緣膜形成步驟中之條件而形成如下所述之層間絕緣膜IL1：Si-CH3/Si-O之比率為0.15以上且0.27以下，Si-CH2-Si/Si-CH3之比率為0.031以上。
繼而，如圖1所示，於層間絕緣膜IL1上形成導孔(未圖示)或配線槽(未圖示)。繼而，於導孔或配線槽之側面、底面、及層間絕緣膜IL1上形成障壁金屬層(未圖示)。繼而，於障壁金屬層上藉由例如鍍敷法而形成通孔(未圖示)或配 線IC1。如此藉由金屬鑲嵌法而形成配線層。
藉由重複進行與該等相同之方法而形成局部配線層LL。於局部配線層LL之各配線層之間亦可形成防擴散層BL1。
繼而，於局部配線層LL之層間絕緣膜IL1上藉由例如CVD而形成層間絕緣膜IL2。藉由金屬鑲嵌法而形成通孔或配線IC2。藉此，於局部配線層LL之上方形成全局配線層GL。於全局配線層GL之各配線層之間亦可形成防擴散層BL2。
繼而，於全局配線層GL之最上層形成含有Al之金屬膜CML。繼而，於全局配線層GL上形成保護層CPL。繼而，於保護層CPL中之在俯視時與金屬膜CML重疊之位置形成開口部(未標示符號)。
繼而，藉由例如濺鍍而於開口部形成凸塊下金屬膜UBM。此時，以例如1.5 μm以上且3.0 μm以下形成凸塊下金屬膜UBM之膜厚。
繼而，藉由例如鍍敷法而於凸塊下金屬膜UBM上形成含有Sn及Ag之凸塊電極BE。再者，亦可藉由印刷法而形成凸塊電極BE。繼而，進行回焊。藉此，形成球狀凸塊電極BE。繼而，將半導體基板SUB切割而形成經分割之半導體晶片SC。
繼而，如圖3所示，將半導體晶片SC搭載於電路基板IP上(安裝步驟)。於安裝步驟中，相對於電路基板IP對半導體晶片SC進行加熱壓接。藉此，將半導體晶片SC之凸塊電極BE與電路基板IP之端子(未圖示)連接。
繼而，於半導體晶片SC及電路基板IP之間注入底層填充樹脂UDF。繼而，使具有凹部之蓋LID接著於電路基板IP及半導體晶片SC上。繼而，於電路基板IP之下表面側形成焊錫球SLB。
根據上述，可獲得第1實施形態之半導體裝置SD。
繼而，一面與比較例進行對比，一面對第1實施形態之效果進行說明。
此處，作為比較例，層間絕緣膜IL1之比介電係數係與第1實施形態相同，考慮層間絕緣膜IL1中之Si-CH2-Si/Si-CH3之比率未達0.031之情形。於比較例之情形時，如上所述，破裂耐壓較低。因此，於比較例中，於例如安裝步驟中，存在如下可能性：因對凸塊電極BE進行加熱壓接時等之負重而導致於位於凸塊電極BE之下方之層間絕緣膜IL1上產生龜裂。又，於安裝後，因半導體基板SUB與電路基板IP之熱膨脹差，而亦存在如下可能性：因凸塊電極上施加有熱應力而產生該龜裂。
相對於此，根據第1實施形態，層間絕緣膜IL1中之、藉由FTIR法而求出之、Si-CH3/Si-O之比率為0.15以上且0.27以下。又，Si-CH2-Si/Si-CH3之比率為0.031以上。
藉此，如上述圖8所示，可藉由層間絕緣膜IL1中之Si-CH2-Si/Si-CH3之比率為0.031以上而提高破裂耐壓。因此，無論凸塊下金屬膜UBM之膜厚如何，均可減少因施加於凸塊電極BE上之應力而引起之層間絕緣膜IL1之龜裂等之不良產生率。
以上，根據第1實施形態，可提供一種具有膜強度較高之層間絕緣膜IL1之半導體裝置SD。
(第2實施形態)第2實施形態係除了如下方面以外均與第1實施形態相同，即，層間絕緣膜IL1之Si-CH3/Si-O之比率與Si-CH2-Si/Si-CH3之比率為被進一步限定之範圍內。以下，對詳情進行說明。
發明者等人發現：可藉由Si-CH3/Si-O之比率與Si-CH2-Si/Si-CH3之比率為被進一步限定之範圍內，而獲得膜強度顯著較高之層間絕緣膜IL1。具體而言，層間絕緣膜IL1中之、藉由FTIR法而求出之、波數1270 cm-1附近之Si-CH3之峰高度相對於波數1030 cm-1附近之Si-O之峰高度的比率為0.16以上且0.24以下。又，波數1360 cm-1附近之Si-CH2-Si之峰高度相對於波數1270 cm-1附近之Si-CH3之峰高度的比率為0.033以上。以下，對詳情進行說明。
再者，於第2實施形態中，用作層間絕緣膜IL1之SiCOH膜之比介電係數為2.9以上且3.15以下。
圖10係表示Si-CH3之Si-O之比率為0.16以上且0.24以下時之Si-CH2-Si/Si-CH3之比率與破裂耐壓之關係的圖。如圖10所示，Si-CH2-Si/Si-CH3之比率為0.033以上之情形與該比率為0.029以下之情形相比，破裂耐壓顯著較高。具體而言，於Si-CH2-Si/Si-CH3之比率為0.033以上之情形時之破裂耐壓為於該比率為0.029以下之情形時之約兩倍以上。
圖11係表示凸塊下金屬膜UBM之厚度與於層間絕緣膜 IL1中所產生之不良產生率之關係的圖。圖11之橫軸係半導體裝置SD之凸塊下金屬膜UBM之膜厚(μm)。圖11之縱軸係表示於進行特定之熱循環試驗後之層間絕緣膜IL1上所產生之不良產生率。如上所述，該「不良」係指因於凸塊電極上施加有熱應力而導致於位於凸塊電極BE之下方之層間絕緣膜IL1上產生龜裂。
於圖11中，黑色菱形標記係表示層間絕緣膜IL1之Si-CH2-Si/Si-CH3之比率為0.029以下之比較例之半導體裝置SD之結果。中空方形標記係表示層間絕緣膜IL1之Si-CH2-Si/Si-CH3之比率為0.033以上之第2實施形態之半導體裝置SD之結果。再者，凸塊下金屬膜UBM含有Ni。
如圖11所示，若為層間絕緣膜IL1之Si-CH2-Si/Si-CH3之比率為0.029以下之比較例之半導體裝置SD，則存在伴隨凸塊下金屬膜UBM之膜厚上升，而不良產生率上升之傾向。
如圖4所示，為了電遷移壽命滿足特定之製品中之可靠性標準，而凸塊下金屬膜UBM之膜厚必需為1.5 μm以上。但是，如圖11所示，於比較例中，於凸塊下金屬膜UBM之膜厚為1.5 μm以上時，存在於層間絕緣膜IL1上產生龜裂之可能性。
相對於此，若為層間絕緣膜IL1之Si-CH2-Si/Si-CH3之比率為0.033以上之第2實施形態之半導體裝置SD，則無論凸塊下金屬膜UBM之膜厚如何，不良產生率均為0。即，對於電遷移壽命滿足特定之製品中之可靠性標準之凸塊下金 屬膜UBM之膜厚，於位於凸塊電極BE之下方之層間絕緣膜上不會產生龜裂等不良現象。因此，於第2實施形態中，可抑制構成凸塊電極BE之材料之遷移，並且可顯著地抑制層間絕緣膜IL1之不良現象。
第2實施形態之半導體裝置SD之製造方法係除了如下方面以外，均與第1實施形態相同，即，層間絕緣膜形成步驟中之成膜條件為被進一步限定之範圍內。
於第2實施形態之層間絕緣膜形成步驟中，例如於以下條件下形成層間絕緣膜IL1。具體而言，例如壓力為2 Torr以上且4 Torr以下。RF(射頻，Radio frequency)功率為500 W以上且1500 W以下。再者，由於功率係取決於裝置，因此並不限定於上述範圍。Si原料之相對於總氣體流量之流量比為0.5以上且0.7以下。又，基板溫度為330℃以上且400℃以下。
根據第2實施形態，可獲得與第1實施形態相同之效果。進而，根據第2實施形態，無論凸塊下金屬膜UBM之膜厚如何，均可顯著地抑制於位於凸塊電極BE之下方之層間絕緣膜上產生龜裂等不良現象之情況。
以上，根據實施形態具體地對由本發明者完成之發明進行了說明，但本發明並不限定於上述實施形態，於不脫離其主旨之範圍內可進行各種變更。
BE‧‧‧凸塊電極
BL1‧‧‧防擴散層
BL2‧‧‧防擴散層
CML‧‧‧金屬膜
CPL‧‧‧保護層
DIR‧‧‧元件分離區域
DR‧‧‧汲極區域
ER‧‧‧延長區域
GE‧‧‧閘極電極
GI‧‧‧閘極絕緣層
GL‧‧‧全局配線層
IC1‧‧‧配線
IC2‧‧‧配線
ICU‧‧‧配線
IL1‧‧‧層間絕緣膜
IL2‧‧‧層間絕緣膜
ILU‧‧‧下部絕緣膜
IP‧‧‧電路基板
LID‧‧‧蓋
LL‧‧‧局部配線層
SC‧‧‧半導體晶片
SD‧‧‧半導體裝置
SLB‧‧‧焊錫球
SR‧‧‧源極區域
SUB‧‧‧半導體基板
SWI‧‧‧側壁絕緣膜
UBM‧‧‧凸塊下金屬膜
UDF‧‧‧底層填充樹脂
VA‧‧‧通孔
VAU‧‧‧接觸插塞
圖1係表示第1實施形態之半導體裝置之構成的剖面圖。
圖2係將圖1之A部放大而成之剖面圖。
圖3係表示第1實施形態之半導體裝置之構成的剖面圖。
圖4係表示凸塊下金屬膜之厚度與電遷移壽命之關係的圖。
圖5係表示波數為2700 cm-1以上且3100 cm-1以下之SiCOH膜之FTIR光譜的圖。
圖6係表示波數為1240 cm-1以上且1300 cm-1以下之SiCOH膜之FTIR光譜的圖。
圖7係表示波數為1345 cm-1以上且1380 cm-1以下之SiCOH膜之FTIR光譜的圖。
圖8係表示Si-CH3之Si-O之比率為0.15以上且0.27以下時之Si-CH2-Si/Si-CH3之比率與SiCOH膜之破裂耐壓之關係的圖。
圖9(a)、(b)係用以說明SiCOH膜中之鍵之模式圖。
圖10係表示Si-CH3之Si-O之比率為0.16以上且0.24以下時之Si-CH2-Si/Si-CH3之比率與破裂耐壓之關係的圖。
圖11係表示凸塊下金屬膜之厚度與層間絕緣膜上所產生之不良率之關係的圖。
BE‧‧‧凸塊電極
BL1‧‧‧防擴散層
BL2‧‧‧防擴散層
CML‧‧‧金屬膜
CPL‧‧‧保護層
GL‧‧‧全局配線層
IC1‧‧‧配線
IC2‧‧‧配線
IL1‧‧‧層間絕緣膜
IL2‧‧‧層間絕緣膜
LL‧‧‧局部配線層
SC‧‧‧半導體晶片
SD‧‧‧半導體裝置
SUB‧‧‧半導體基板
UBM‧‧‧凸塊下金屬膜

Claims (8)

  1. 一種半導體裝置，其包括：層間絕緣膜，其含有Si、O、C及H；凸塊下金屬膜，其係設置於上述層間絕緣膜上且含有Ni；及凸塊電極，其係設置於上述凸塊下金屬膜上；且上述層間絕緣膜中之藉由FTIR(Fourier Transform Infrared Spectroscopy)法而求出之波數1270 cm-1附近之Si-CH3之峰高度相對於波數1030 cm-1附近之Si-O之峰高度的比率為0.15以上且0.27以下，波數1360 cm-1附近之Si-CH2-Si之峰高度相對於波數1270 cm-1附近之Si-CH3之峰高度的比率為0.031以上。
  2. 如請求項1之半導體裝置，其中上述Si-CH3之峰高度相對於上述Si-O之峰高度的比率為0.16以上且0.24以下，上述Si-CH2-Si之峰高度相對於上述Si-CH3之峰高度的比率為0.033以上。
  3. 如請求項1之半導體裝置，其中上述凸塊下金屬膜之厚度為1.5 μm以上且3.0 μm以下。
  4. 如請求項1之半導體裝置，其中上述凸塊電極含有Sn及Ag。
  5. 如請求項1之半導體裝置，其中上述凸塊電極之高度為50 μm以上且100 μm以下。
  6. 如請求項1之半導體裝置，其中上述層間絕緣膜之比介電係數為2.5以上且3.2以下。
  7. 一種半導體裝置之製造方法，其包括：形成含有Si、O、C及H之層間絕緣膜之層間絕緣膜形成步驟；於上述 層間絕緣膜上形成含有Ni之凸塊下金屬膜之步驟；及於上述凸塊下金屬膜上形成凸塊電極之步驟；且於上述層間絕緣膜形成步驟中，形成如下所述之上述層間絕緣膜：藉由FTIR(Fourier Transform Infrared Spectroscopy)法而求出之波數1270 cm-1附近之Si-CH3之峰高度相對於波數1030 cm-1附近之Si-O之峰高度的比率為0.15以上且0.27以下，波數1360 cm-1附近之Si-CH2-Si之峰高度相對於波數1270 cm-1附近之Si-CH3之峰高度比率為0.031以上。
  8. 如請求項7之半導體裝置之製造方法，其中於形成上述凸塊下金屬膜之步驟中，使上述凸塊下金屬膜之厚度為1.5 μm以上且3.0 μm以下。
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