TWI783264B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI783264B
TWI783264B TW109130967A TW109130967A TWI783264B TW I783264 B TWI783264 B TW I783264B TW 109130967 A TW109130967 A TW 109130967A TW 109130967 A TW109130967 A TW 109130967A TW I783264 B TWI783264 B TW I783264B
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bump
bump electrode
electrode
semiconductor device
opening
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TW109130967A
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TW202117969A (zh
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加本拓
右田達夫
渡辺慎也
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日商鎧俠股份有限公司
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Abstract

本發明之實施形態係提供一種基板接合之可靠性提昇之半導體裝置及其製造方法。  實施形態之半導體裝置具有：第一半導體基板，其於表面設置有第一配線電極；第一保護層，其係形成於上述半導體基板上，且於上述第一配線電極上具有開口部；第一凸塊電極，其係形成於上述第一保護層之開口部；及凸塊，其係與上述第一凸塊電極接合，且凸塊直徑為30 μm以下。形成於上述開口部之上述第一凸塊電極之底面直徑係上述第一保護層之膜厚之1.5倍以下。

Description

半導體裝置及其製造方法
本發明之實施形態係關於一種半導體裝置及其製造方法。
於半導體裝置之製造中，當將形成有半導體裝置之基板經由凸塊覆晶連接於形成有其他半導體裝置或配線之基板時，對於預先形成於一基板表面之電極，連接設置於另一基板之凸塊。此時，存在將電極預先嵌入地形成於基板表面上所形成之開口部，從而電極表面沿著開口部成為凹形狀表面之情形。當將凸塊接合於凹形狀表面之電極時，存在凹部中捲入空氣等氣體之虞，從而出現於接合部位產生空隙之情形。
本發明之實施形態係提供一種基板接合之可靠性提昇之半導體裝置及其製造方法。  實施形態之半導體裝置具有：第一半導體基板，其於表面設置有第一配線電極；第一保護層，其係形成於上述半導體基板上，且於上述第一配線電極上具有開口部；第一凸塊電極，其係形成於上述第一保護層之開口部；及凸塊，其係與上述第一凸塊電極接合，且凸塊直徑為30 μm以下。形成於上述開口部之上述第一凸塊電極之底面直徑係上述第一保護層之膜厚之1.5倍以下。
以下，對於用以實施發明之實施形態進行說明。  (實施形態)  對於本實施形態之半導體裝置，參照圖1、圖2、及圖3進行說明。再者，於以下圖式之記載中，同一部分以同一符號表示。但，於圖式中，厚度與平面尺寸之關係及比率等係模式性表示而與實際情形不同。  對於本實施形態之半導體裝置之構成，使用圖1進行說明。圖1係表示本實施形態之半導體裝置之構成之剖視圖。  如圖1所示，本實施形態之半導體裝置1具備第一半導體裝置10與第二半導體裝置30，且第一半導體裝置10與第二半導體裝置30藉由導電性凸塊20而接合，從而分別電性連接。  第一半導體裝置10具備矽基板等第一半導體基板100、第一配線電極101、第一保護層102、第一障壁膜103(對應第一電極膜)、及第一凸塊電極104。  於第一半導體基板100，雖分別省略圖示，但設置有半導體元件、與元件電性連接之Cu等導電配線層、及層間絕緣層。於第一半導體基板100之表面，形成有經由配線層而與半導體元件連接之第一配線電極101。第一配線電極101係例如包含Al、Cu、Ni、Au、Ag、或該等之合金之導電體。  於第一配線層101上，形成有絕緣性之第一保護層102。第一保護層102包含例如氧化矽膜、氮化矽膜、及聚醯亞胺等之任一單層或該等之複數層。第一保護層102之膜厚為5 μm。可藉由將第一保護層102之膜厚設為5 μm以上，而有效地保護形成於半導體基板100之半導體元件或配線層等之內部結構。於第一保護層102，在第一配線層101上形成有開口部。  於第一保護層102之開口部之底面及側面、以及第一保護層102之開口部附近之上部，形成有第一障壁膜103。第一障壁膜103包含Ti、TiN、Ta、及TaN等之任一單層或該等之積層，且以均等之膜厚形成。再者，亦可視情形不形成第一障壁膜103。  於第一障壁膜103上形成有第一凸塊電極104，且第一保護層102之開口部被第一凸塊電極104嵌入。第一凸塊電極104包含Cu、Ni、Au、Ag、Pd、Al及該等之合金之任一單層或該等之積層，例如為包含鍍Cu籽晶層與鍍Cu層之積層之Cu柱層。  第一凸塊電極104之膜厚為3 μm。此處，膜厚係指設置於第一保護層102上之第一凸塊電極104之膜厚。複數個半導體基板積層而成之半導體裝置可藉由將凸塊電極104之膜厚設為3 μm以下，而抑制各半導體基板間之距離，從而可將半導體裝置整體小型化。  第一保護層102之開口部之開口直徑為5 μm以下。於第一障壁膜103形成於開口部內部之情形時，較佳為形成有第一障壁膜103之開口部之開口直徑為5 μm以下。即，若嵌入至開口部中之第一凸塊電極104底面直徑為5 μm以下則較佳。此處，嵌入至開口部中之第一凸塊電極104底面直徑於特定之方向上為5 μm以下即可，但更佳為於任一方向上均為5 μm以下。  藉由如此地縮小開口直徑而於將第一凸塊電極104嵌入形成於開口部時，可抑制設置於開口部上部之第一凸塊電極104表面之凹陷量。此處，第一凸塊電極104表面之凹陷量設為第一凸塊電極104之上層表面之最上部與最下部之差。  若將凸塊接合之電極表面之凹陷量成為3～5 μm以上，則於電極與凸塊間或凸塊內部捲入空氣，從而容易產生空隙。若產生空隙，則凸塊接合中之電阻增加，或物理接合可靠性惡化。本實施形態中，可藉由將嵌入至開口部中之第一凸塊電極104底面之直徑設為第一保護層102之膜厚以下，而利用第一凸塊電極104將開口部充分地蓋住，從而可將第一凸塊電極104表面之凹陷量抑制為1 μm以下。進而，即便將嵌入至開口部中之第一凸塊電極104底面之直徑設為第一保護層102之膜厚之1.5倍以下，亦可將第一凸塊電極104表面之凹陷量抑制為1.5 μm以下。  於第一凸塊電極104上，形成有凸塊20。凸塊20之材料包含Cu、Sn、Pb、Au、Ag、Pd、Ni、或該等之合金。凸塊20係凸塊直徑為30 μm以下之微型凸塊，又，藉由將與設置於第一半導體裝置10之同一表面側之至少一個其他凸塊之距離(凸塊間距)設為60 μm以下，可使半導體裝置整體小型化。  一般而言，於凸塊直徑為80 μm、100 μm、150 μm或大於150 μm之大小之情形時，於凸塊與凸塊電極之接合部位所產生之空隙因與凸塊之大小相比相對較小，故接合可靠性成為問題之情形較少。相反地，於使用凸塊直徑為30 μm以下之微型凸塊之情形時，於凸塊與凸塊電極之接合部位所產生之空隙因相對於凸塊之大小，相對地變大，故容易產生接合可靠性之問題。  本實施形態之半導體裝置1係藉由一面使用微型凸塊實現小型化，一面將第一保護層102之膜厚與第一凸塊電極104之直徑調整為適當大小，而抑制第一凸塊電極104表面之凹陷量，因此，可如圖1所示，於凸塊與凸塊電極之接合部位中不產生空隙，或者可充分地抑制接合部位之空隙之大小，因此，可提昇接合可靠性。  可經由凸塊20，將第二半導體裝置30與第一半導體裝置10接合。  第二半導體裝置30具備矽基板等第二半導體基板300、第二配線電極301、第二保護層302、第二障壁膜303、及第二凸塊電極304。  於第二半導體基板300，雖分別省略圖示，但設置有半導體元件、與元件電性連接之Cu等導電配線層、及層間絕緣層。於第二半導體基板300之表面，形成有經由Cu配線層而與半導體元件連接之第二配線電極301。第二配線電極301係例如Ni、Au、Cu、Al等導電材。  於第二配線層301上，形成有絕緣性之第二保護層302。第二保護層302包含例如氧化矽膜、氮化矽膜、及聚醯亞胺等之任一單層或該等之複數層。與第一保護層102同樣地，可藉由將第二保護層302之膜厚設為5 μm以上而有效地保護半導體基板上之元件結構。於第二保護層302，在第二配線層301上部形成有開口部。  於第二保護層302之開口部之底面及側面、以及第二保護層302之開口部附近之上部，形成有第二障壁膜303。第二障壁膜303可採用與第一障壁膜103相同之材料及結構。又，亦可不必形成第二障壁膜303。  第二凸塊電極304係於第二障壁膜303上，嵌入至第二保護層302之開口部內。第二凸塊電極304係與第一凸塊電極104相同之材料或結構，且可藉由將其膜厚與第一凸塊電極104同樣地設為3 μm以下而將半導體裝置整體小型化。  於第二凸塊電極304上形成有凸塊20，且經由凸塊20將半導體裝置20與半導體裝置10電性及物理性地連接。  繼而，對於本實施形態之半導體裝置之製造方法，使用圖2及圖3進行說明。圖2及圖3係表示本實施形態之半導體裝置之製造方法之步驟剖視圖。  首先，如圖2(a)所示，準備第一半導體裝置10之第一半導體基板100。於第一半導體基板100雖省略圖示，但設置有半導體元件、與元件電性連接之Cu等導電配線層、及層間絕緣層。於第一半導體基板100之表面，形成經由配線層而與半導體元件電性連接之第一配線電極101。進而，於第一半導體基板100之表面，以將第一配線電極101覆蓋之方式，利用CVD法等形成膜厚5 μm之第一保護層102。此後，利用微影法及乾式蝕刻，於第一保護層102設置開口直徑5 μm左右之開口部，使第一配線電極101之一部分自開口部露出。  其次，如圖2(b)所示，利用濺鍍法等將第一障壁膜103形成於第一保護層102之上表面及開口部之底面及側面。此後，將光阻劑105形成於第一障壁膜103上之後，利用微影法於光阻劑105設置開口部，使第一障壁膜103之一部分露出。  此後，如圖2(c)所示，利用電鍍法，於光阻劑105之開口部內露出之障壁膜103上形成第一凸塊電極104，藉此，將第一凸塊電極104嵌入至第一保護層102之開口部中。第一凸塊電極104之材料為Cu，且膜厚設為3 μm。此時，於第一保護層102之開口部上方，在第一凸塊電極104之表面產生微小之凹部，但凹陷量得以抑制。  於形成第一凸塊電極104之後，將光阻劑105利用灰化去除，進而亦將露出之第一障壁膜103去除。以上，如圖2(a)至圖2(c)所示地製造第一半導體裝置10。  其次，如圖3(a)所示，利用與第一半導體裝置10相同之方法，製造第二半導體裝置30。準備第二半導體基板300，分別形成第二配線電極301、第二保護層302、第二障壁膜303、光阻劑305、及第二凸塊電極304。  繼而，如圖3(b)所示，藉由電鍍，於光阻劑305之開口部之第二凸塊電極304上形成Sn合金等焊料層201。於形成焊料層201之後，將光阻劑305及光阻劑305下方之第二障壁膜303均去除。  繼而，如圖3(c)所示，藉由熱處理而將焊料層201熔融，於第二半導體裝置30上形成凸塊20。凸塊20係凸塊直徑為30 μm以下之微型凸塊。又，雖省略圖示，但凸塊20係複數個同時地形成於第二半導體基板300之同一表面側，且各個凸塊間距離設為60 μm以下。  最後，如圖3(d)所示，藉由熱壓接合，將形成於第二半導體裝置30上之凸塊20壓抵於第一半導體裝置10之第一凸塊電極104，隨後進行冷卻，藉此，利用凸塊20將第一半導體裝置10與第一半導體裝置30接合。即便於第一凸塊電極104表面形成有凹部，凹部之凹陷量亦較小，因此，不存在將凸塊20壓接於第一凸塊電極104之過程中捲入空氣之虞，從而不產生空隙，因此，可提昇接合可靠性。  再者，作為其他凸塊接合技術，亦已知有將凸塊亦預先設置於第一半導體裝置上，且將第一半導體裝置上之凸塊與第二半導體裝置上之凸塊接合之技術。與此相對，本實施形態之半導體裝置之製造方法因僅於第二半導體裝置上形成凸塊且與第一半導體裝置接合，因此，可減少焊料使用量。  圖4係表示本實施形態之半導體裝置之構成之變化例之圖。如圖4所示，本變化例之半導體裝置具有於圖1所示之半導體裝置之第二半導體裝置30上介隔凸塊40進而積層第三半導體裝置50所得之構成。  第二半導體裝置30係於第二半導體基板300內形成有於基板貫通方向上延伸之導電性通孔306。通孔306包含Cu等導體材料，且於第一半導體裝置10側之端部，與第二配線電極301電性連接。又，通孔306亦於相反側之端部，與第二配線電極307電性連接。  於第二配線電極307上，以與第一半導體裝置10中之第一保護層102、第一障壁膜103、及第一凸塊電極104相同之構成、材料、尺寸、配置，設置有第二保護層308、第二障壁膜309、及第二凸塊電極310。此處，第二凸塊電極310表面之凹陷量與第一凸塊電極104表面之凹陷量同樣地得以充分抑制。  於第二凸塊電極310上接合著導電性凸塊40，進而於凸塊40上接合著第三半導體裝置50。第三半導體裝置50之構成係與第二半導體裝置30之構成、材料、尺寸、配置相同，且具備矽基板等第三半導體基板500、第三配線電極501、第三保護層502、第三障壁膜503、及第三凸塊電極504。凸塊40係將第二凸塊電極310與第三凸塊電極504間接合，確立第二半導體裝置30與第三半導體裝置50之電性連接。  以上說明之本變化例之半導體裝置可藉由設置沿半導體基板之貫通方向延伸之通孔，而一面緊湊地保持積層而成之3個以上半導體裝置，一面實現各自之電性連接。又，因將凸塊接合中之空隙之產生抑制，故可提昇接合可靠性。  以上，說明了本發明之實施形態，但本實施形態係作為示例而提示，並無限定發明範圍之意圖。新穎之實施形態可利用其他各種形態實施，且可於不脫離發明要點之範圍內，進行各種省略、置換、變更。該等實施形態或其變化包含於發明之範圍或要點中，並且包含於與權利請求之範圍中記載之發明及其均等之範圍中。 [相關申請] 本申請享有以日本專利申請2017-23207號(申請日：2017年2月10日)為基礎申請之優先權。本申請藉由參照該基礎申請而包含基礎申請之全部內容。
1:半導體裝置10:第一半導體裝置20,40:凸塊30:第二半導體裝置50:第三半導體裝置100:第一半導體基板101:第一配線電極102:第一保護層103:第一障壁膜104:第一凸塊電極105,305:光阻劑201:焊料層300:第二半導體基板301,307:第二配線電極302,308:第二保護層303,309:第二障壁膜304,310:第二凸塊電極306:通孔500:第三半導體基板501:第三配線電極502:第三保護層503:第三障壁膜504:第三凸塊電極
圖1係說明實施形態之半導體裝置之構成之圖。  圖2(a)～圖3(d)係說明圖1之半導體裝置之製造方法之圖。  圖4係說明實施形態之變化例之半導體裝置之構成之圖。
1:半導體裝置
10:第一半導體裝置
20:凸塊
30:第二半導體裝置
100:第一半導體基板
101:第一配線電極
102:第一保護層
103:第一障壁膜
104:第一凸塊電極
300:第二半導體基板
301:第二配線電極
302:第二保護層
303:第二障壁膜
304:第二凸塊電極

Claims (7)

  1. 一種半導體裝置，其特徵在於包含：第一半導體基板，其於表面設置有第一配線電極；第一保護層，其係形成於上述第一半導體基板上，且於上述第一配線電極上具有第一開口部；第一凸塊電極，其形成於上述第一保護層之上述第一開口部；第二半導體基板，其於表面設置有第二配線電極；第二保護層，其係形成於上述第二半導體基板上，且於上述第二配線電極上具有第二開口部，該第二開口部之徑大於上述第一開口部；第二凸塊電極，其形成於上述第二保護層之上述第二開口部；及凸塊，其係接合於上述第一凸塊電極及上述第二凸塊電極，且凸塊直徑為30μm以下；形成於上述第一開口部之上述第一凸塊電極之底面直徑為上述第一保護層之膜厚之1.5倍以下；上述第一凸塊電極係於表面形成凹部；上述第一凸塊電極之上層表面之最上部與最下部之差為1.5μm以下；上述第一保護層之膜厚為5μm以上；上述第二凸塊電極係於表面形成凹部；上述第二凸塊電極之上層表面之最上部與最下部之差大於上述第一凸塊電極之上層表面之最上部與最下部之差。
  2. 如請求項1之半導體裝置，其中形成於上述第一開口部之上述第一凸塊電極之底面直徑為上述第一保護層之膜厚以下。
  3. 如請求項1之半導體裝置，其中上述第一凸塊電極之上層表面之最上部與最下部之差為1.0μm以下。
  4. 如請求項1至3中任一項之半導體裝置，其中上述第一凸塊電極亦形成於上述第一保護層上，且上述第一保護層上之上述第一凸塊電極之膜厚為3μm以下。
  5. 如請求項1至3中任一項之半導體裝置，其中上述凸塊與設置於上述第一半導體基板之同一表面側之其他凸塊之距離為60μm以下。
  6. 如請求項4之半導體裝置，其中上述凸塊與設置於上述第一半導體基板之同一表面側之其他凸塊之距離為60μm以下。
  7. 一種半導體裝置之製造方法，其特徵在於：準備第一半導體基板，該第一半導體基板於表面具備：具有第一開口部之第一保護層、及形成於上述第一開口部之第一凸塊電極；準備第二半導體基板，該第二半導體基板於表面具備：具有第二開口部之第二保護層、及形成於上述第二開口部之第二凸塊電極，上述第二開口部係大於上述第一開口部之徑；上述第一凸塊電極與上述第二凸塊電極相向，且於上述第一凸塊電 極及上述第二凸塊電極之間，將凸塊直徑為30μm以下之凸塊接合於上述第一凸塊電極及上述第二凸塊電極；且形成於上述第一開口部之上述第一凸塊電極之底面直徑為上述第一保護層之膜厚之1.5倍以下；於上述第一凸塊電極之表面形成凹部；上述第一凸塊電極之上層表面之最上部與最下部之差為1.5μm以下；上述第一保護層之膜厚為5μm以上；於上述第二凸塊電極之表面形成凹部；上述第二凸塊電極之上層表面之最上部與最下部之差大於上述第一凸塊電極之上層表面之最上部與最下部之差。
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