WO2014142075A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2014142075A1
WO2014142075A1 PCT/JP2014/056185 JP2014056185W WO2014142075A1 WO 2014142075 A1 WO2014142075 A1 WO 2014142075A1 JP 2014056185 W JP2014056185 W JP 2014056185W WO 2014142075 A1 WO2014142075 A1 WO 2014142075A1
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WIPO (PCT)
Prior art keywords
wiring
electrodes
semiconductor chip
bump
pad electrodes
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PCT/JP2014/056185
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English (en)
French (fr)
Inventor
片桐　光昭
優 長谷川
聡 伊佐
Original Assignee
ピーエスフォー ルクスコ エスエイアールエル
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Application filed by ピーエスフォー ルクスコ エスエイアールエル filed Critical ピーエスフォー ルクスコ エスエイアールエル
Priority to US14/773,817 priority Critical patent/US9589921B2/en
Priority to DE112014001274.2T priority patent/DE112014001274T5/de
Priority to KR1020157028308A priority patent/KR20150128919A/ko
Publication of WO2014142075A1 publication Critical patent/WO2014142075A1/ja

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a semiconductor device including a semiconductor chip and a wiring structure provided on the main surface thereof.
  • Many semiconductor devices are composed of a semiconductor chip and a package for housing it.
  • the package is provided with external terminals and a wiring structure for connecting pad electrodes provided on the semiconductor chip and external terminals.
  • a rigid package substrate made of resin or the like functions as a wiring structure (see Patent Document 1).
  • WLP wafer level package
  • a wiring structure is directly formed on the main surface of a semiconductor chip without using a rigid substrate.
  • the power supply wiring is formed thick to increase the cross-sectional area or It is conceivable to increase the number of power supply wiring layers by increasing the number of power supply wiring layers, that is, increasing the number of wiring layers formed on the semiconductor chip.
  • forming the power supply wiring thickly requires a change in the manufacturing process of the semiconductor chip in order to form a thick conductor, and increasing the number of wiring layers is a new mask pattern. There is a need to do it from the formation, which is not realistic from the viewpoint of cost.
  • a semiconductor device includes a semiconductor chip having a plurality of first pad electrodes and a plurality of second pad electrodes, and a wiring structure provided on the semiconductor chip, the wiring structure comprising: A plurality of external terminals, a plurality of wiring patterns that electrically connect the plurality of external terminals and the plurality of first pad electrodes, respectively, and any of the plurality of external terminals in the wiring structure And a bridge wiring that electrically connects the plurality of second pad electrodes in common without being connected to each other.
  • the bridge wiring provided in the wiring structure assists the wiring in the semiconductor chip, the impedance of the predetermined wiring can be reduced.
  • FIG. 1 is a schematic cross-sectional view for explaining the structure of a semiconductor device 10 according to a first embodiment of the present invention.
  • 3 is a schematic plan view for explaining a layout of bump electrodes 110 provided on a semiconductor chip 100.
  • FIG. 2 is a schematic plan view showing a pad electrode 120.
  • FIG. FIG. 3 is a schematic cross-sectional view along the line AA ′ shown in FIG. 2.
  • FIG. 5 is a schematic plan view for explaining the shapes of bump electrodes 110a to 110c.
  • FIG. 6 is a schematic cross-sectional view along the line BB ′ shown in FIG. 5. It is a schematic sectional view showing the shape of a bump electrode 110X. It is a schematic sectional view for explaining a state in which a solder layer 113 is melted.
  • FIG. 4 is a schematic plan view for explaining a conductive pattern formed on one surface 210a of an insulating base 210.
  • FIG. It is a figure which shows an example of the layout of the external terminal 260 provided in the other surface 210b of the insulating base material 210.
  • FIG. 4 is a schematic diagram for explaining an example of a connection relationship between a semiconductor chip 100 and a wiring board 200.
  • FIG. 6 is a schematic diagram for explaining another example of the connection relationship between the semiconductor chip 100 and the wiring substrate 200.
  • FIG. 5 is a process diagram for explaining a production process of a bump electrode 110.
  • FIG. 5 is a process diagram for explaining a production process of a bump electrode 110.
  • FIG. 5 is a process diagram for explaining a production process of a bump electrode 110.
  • FIG. 6 is a process diagram for explaining a process of flip-chip mounting the semiconductor chip 100 on the wiring board 200.
  • FIG. It is a schematic sectional drawing for demonstrating the structure of the semiconductor chip 100a used in 2nd Embodiment.
  • FIG. 5 is a schematic plan view for explaining the shapes of bump electrodes 110a to 110c.
  • FIG. 20 is a schematic cross-sectional view taken along the line CC ′ shown in FIG. It is a typical top view for demonstrating the 1st example of the relationship between the pad electrode 120b and the uppermost wiring layer. It is a typical top view for explaining the 2nd example of the relation between pad electrode 120b and the uppermost wiring layer.
  • FIG. 4 is a schematic cross-sectional view for explaining the structure of the semiconductor device 20.
  • FIG. It is a schematic plan view for explaining an example in which a back surface bump 170c of a semiconductor chip 100b is short-circuited by a bridge wiring 290a.
  • FIG. shows the layout of the main surface of the semiconductor chip 100c used in 4th Embodiment.
  • It is a schematic plan view for explaining a conductive pattern formed on the wiring board 200b.
  • 3 is a schematic plan view showing a layout of a bridge wiring 290c formed in a wiring layer 320.
  • FIG. It is a schematic diagram for demonstrating the connection relation of the semiconductor chip 100e and the wiring board 200d.
  • FIG. 1 is a schematic cross-sectional view for explaining the structure of a semiconductor device 10 according to a first embodiment of the present invention.
  • the semiconductor device 10 includes a semiconductor chip 100 and a wiring board 200 on which the semiconductor chip 100 is flip-chip mounted.
  • the semiconductor chip 100 is a one-chip device in which a large number of elements such as transistors are integrated on a semiconductor substrate made of silicon (Si) or the like.
  • the type of the semiconductor chip 100 is not particularly limited, and may be a memory device such as a DRAM (Dynamic Random Access Memory) or a logic device such as a CPU (Central Processing Unit), or a sensor. It may be an analog device such as.
  • the wiring board 200 is a circuit board that functions as a wiring structure.
  • the insulating base 210 made of glass epoxy having a thickness of 0.2 mm
  • the connection electrode 220 formed on one surface 210a of the insulating base 210, and the insulating base 210 are insulated.
  • the connection electrode 220 and the land pattern 230 are connected to each other via a wiring pattern 240 provided on the insulating substrate 210.
  • the wiring pattern 240 may be formed on one or the other surface of the insulating base 210 or may be formed on the inner layer of the insulating base 210.
  • connection electrode 220 is an electrode to which the bump electrode 110 provided on the semiconductor chip 100 is bonded.
  • the land pattern 230 is connected to an external terminal 260 made of a solder ball.
  • An underfill 270 is filled between the wiring substrate 200 and the semiconductor chip 100, and a sealing resin 280 is provided so as to cover the semiconductor chip 100.
  • the first type of bump electrode 110 a is provided in a substantially central region of the semiconductor chip 100 and is electrically connected to the external terminal 260 via the wiring pattern 240.
  • the second type of bump electrode 110 b is provided in the vicinity of the outer peripheral region of the semiconductor chip 100 and is electrically connected to the external terminal 260 through the wiring pattern 240.
  • the third type of bump electrode 110 c is provided in the vicinity of the outer peripheral region of the semiconductor chip 100, but is not electrically connected to any external terminal 260.
  • the fourth type of bump electrode 110 d is a dummy bump electrode provided in the vicinity of the outer peripheral region of the semiconductor chip 100 and is not electrically connected to any external terminal 260. As shown in FIG.
  • the pad electrode 120 is provided on the base of the bump electrodes 110a to 110c, but the pad electrode corresponding to the dummy bump electrode 110d is not provided, and the outermost layer of the semiconductor chip 100 is formed. It is formed on the upper surface of the covering protective film 130.
  • FIG. 2 is a schematic plan view for explaining the layout of the bump electrodes 110 provided on the semiconductor chip 100.
  • FIG. 3 is a schematic plan view showing the pad electrode 120 that is the base of the bump electrode 110.
  • FIG. 4 is a schematic cross-sectional view along the line AA ′ shown in FIG.
  • the bump electrodes 110a are arranged in two rows in the X direction at a substantially central portion in the Y direction of the semiconductor chip 100.
  • the bump electrode 110a is used for signal input / output and external power supply potential supply.
  • the pad electrode 120a corresponding to the bump electrode 110a has a slightly larger planar size than the bump electrode 110a.
  • the bump electrodes 110 b to 110 d are arranged in the vicinity of the outer peripheral region of the semiconductor chip 100.
  • the bump electrode 110b is used for supplying an external power supply potential
  • the bump electrode 110c is used for connection to a bridge wiring described later.
  • the pad electrodes 120b and 120c corresponding to the bump electrodes 110b and 110c have a slightly smaller planar size than the corresponding bump electrodes 110b and 110c.
  • the semiconductor chip 100 made of silicon or the like and the wiring board 200 made of resin or the like have greatly different coefficients of thermal expansion, so that the wiring board 200 is warped when the temperature changes, and the semiconductor chip 100 is peeled off from the wiring board 200.
  • the bump electrodes 110b and 110c are disposed in the vicinity of the outer peripheral region of the semiconductor chip 100 where peeling is likely to occur, thereby increasing the bonding strength between the two.
  • the dummy bump electrode 110d is used exclusively for the purpose of increasing the bonding strength. Therefore, as shown in FIGS. 3 and 4, the pad electrode corresponding to the dummy bump electrode 110d is unnecessary.
  • FIG. 5 is a schematic plan view for explaining the shapes of the bump electrodes 110a to 110c
  • FIG. 6 is a schematic cross-sectional view along the line BB ′ shown in FIG.
  • the planar shape of the bump electrode 110a is a square, whereas the planar shape of the bump electrodes 110b and 110c is a circle.
  • the dummy bump electrode 110d also has a circular planar shape.
  • the length of one side of the bump electrode 110a and the diameter of the bump electrodes 110b and 110c are designed to be substantially equal.
  • the bump electrode 110a has a larger cross-sectional area in the direction parallel to the main surface of the semiconductor chip 100 than the bump electrodes 110b and 110c. This means that the square bump electrodes 110a arranged at a predetermined interval (pitch) can be arranged with the closest density and lower resistance than the bump electrodes 110b and 110c.
  • the planar shape of the pad electrode 120a corresponding to the bump electrode 110a is also a quadrangle, and its size is slightly larger than that of the bump electrode 110a. For this reason, the outer peripheral part of the pad electrode 120a is not covered with the bump electrode 110a.
  • the planar shape of the pad electrodes 120b and 120c corresponding to the bump electrodes 110b and 110c is a quadrangle, but the size is smaller than that of the bump electrodes 110b and 110c. For this reason, the pad electrodes 120b and 120c are entirely covered with the bump electrodes 110b and 110c.
  • the contact resistance between the bump electrode 110a and the pad electrode 120a is lower than the contact resistance between the bump electrodes 110b and 110c and the pad electrodes 120b and 120c. Can be supplied with low resistance.
  • the pad electrode 120a is designed to be large is to enable the probe of the tester to be contacted in order to perform a test in a wafer state.
  • the pad electrodes 120b and 120c are designed to have a small area because they do not come into contact with the probe in the wafer state test. Further, as shown in FIG. 3, the pad electrodes 120b and 120c are arranged in the vicinity of the outer peripheral region of the semiconductor chip 100 which is not the pad area, and it is difficult to secure a large-area pad in the wiring layer. Is also present.
  • the planar shape of the bump electrode 110a is a square, whereas the planar shape of the bump electrodes 110b to 110d is a circle.
  • the reason why the planar shape of the bump electrode 110a is a quadrangle is that the cross-sectional area in the direction parallel to the main surface of the semiconductor chip 100 can be maximized when the plurality of bump electrodes 110a are arranged at a predetermined pitch. . This makes it possible to transmit and receive signals and supply power via the bump electrodes 110a with low resistance.
  • the reason why the planar shape of the bump electrodes 110b to 110d is circular is to increase the bonding strength.
  • planar shape of the bump electrodes 110b to 110d is a quadrangle
  • the planar shape of the bump electrodes 110b to 110d is circular
  • stress is not concentrated at a specific location, so that even if the wiring substrate 200 is warped, it is difficult to peel off.
  • the planar shapes of the bump electrodes 110a to 110d are designed as described above.
  • the planar shape of the bump electrodes 110b to 110d is not limited to a circular shape, and any shape is preferable as long as stress concentration hardly occurs.
  • a polygon having both obtuse angles such as a regular hexagon and a regular octagon is also preferable.
  • the bump electrodes 110 a to 110 c include UBM (under barrier metal) layers 111 in contact with the pad electrodes 120 a to 120 c, pillar portions 112 erected on the UBM layers 111, and pillar portions 112. And a solder layer 113 provided on the end face 112a.
  • the UBM layer 111 is made of a laminated film of Ti and Cu, for example, and the pillar portion 112 is made of Cu, for example.
  • the dummy bump electrode 110d has the same structure as the bump electrodes 110a to 110c shown in FIG. 6 except that the corresponding pad electrode 120 does not exist.
  • bump electrode 110a, 110b, 110c, 110d when making the pillar part 112 of bump electrode 110a, 110b, 110c, 110d by plating, since these are formed simultaneously, bump electrode 110a, 110b, 110c formed on pad electrode 120a, 120b, 120c.
  • the position of the upper end surface 112a of the pillar portion 112 of the insulating film bump electrode 110d is higher than the upper end surface 112a of the pillar portion 112.
  • the pillar portion 112 of the bump electrode 110d is formed to have a smaller diameter than the pillar portions 112 of the other bump electrodes 110a, 110b, and 110c.
  • the pillar portion 112 of the bump electrode 110d has a small diameter, the area of the upper end surface a of the pillar portion 112 is smaller than the area of the upper end portion a of the pillar portion 112 of the other bump electrodes 110a, 110b, and 110c. This is because the height of the solder bump formed thereon after reflow is reduced, and the height of the pillar portion 112 can be absorbed. As a result, the bump electrodes 110a, 110b, 110c, and 110d including the solder layer 113 after reflow have substantially the same height.
  • FIG. 7 is a schematic cross-sectional view showing the shape of the improved bump electrode 110X.
  • the bump electrode 110X shown in FIG. 7 has an inverted trapezoidal cross section, and therefore the angle formed by the upper end surface 112a and the side surface 112b of the pillar portion 112 is an acute angle.
  • the bump electrode 110X having such a shape is used, when the semiconductor chip 100 is flip-chip connected to the wiring substrate 200, the solder layer 113 melted by reflow does not easily go around the side surface 112b of the pillar portion 112. The molten solder layer 113 is deformed into a hemispherical shape as shown in FIG. 8 due to surface tension.
  • the solder layer 113 when the solder layer 113 is thick, the molten solder layer 113 spills from the upper end surface 112a of the pillar portion 112, and the side surface 112b. May wrap around. However, if the angle formed by the upper end surface 112a and the side surface 112b is set to an acute angle, the solder layer 113 is unlikely to wrap around, so that connection failure or short circuit failure due to the spillage of the solder layer 113 can be prevented.
  • the side surface 112b of the pillar portion 112 does not need to be entirely inclined, and only the upper portion of the side surface 112b in contact with the upper end surface 112a is inclined as shown in FIG.
  • the other parts may be vertical.
  • the upper side of the side surface 112 b that is in contact with the upper end surface 112 a is inclined so that the diameter increases as it goes upward, and the lower side of the side surface 112 b that is in contact with the UBM layer 111 is downward.
  • the spindle shape may be inclined in the direction in which the diameter increases. In short, it is sufficient that the angle formed by the upper end surface 112a of the pillar portion 112 and the side surface 112b in the portion in contact with the pillar portion 112 is an acute angle.
  • FIG. 11 is a schematic plan view for explaining a conductive pattern formed on one surface 210a of the insulating base 210.
  • FIG. A broken line 100 ⁇ / b> X illustrated in FIG. 11 is a mounting area of the semiconductor chip 100.
  • connection electrodes 220 As shown in FIG. 11, a plurality of connection electrodes 220, a plurality of wiring patterns 240, and two bridge wirings 290 are provided on one surface 210 a of the insulating base 210. More specifically, of the connection electrodes 220, the connection electrode 220 a bonded to the bump electrode 110 a is connected to the through-hole conductor 221 through the wiring pattern 240.
  • the through-hole conductor 221 is a conductor provided through the insulating base 210 and is connected to the land pattern 230 and the external terminal 260 provided on the other surface 210 b of the insulating base 210.
  • FIG. 12 is a diagram showing an example of the layout of the external terminals 260 provided on the other surface 210b of the insulating base 210.
  • FIG. 12 the other surface 210b of the insulating base 210 is provided with a wiring pattern 240 that connects the through-hole conductor 221 and the land pattern 230 (external terminal 260).
  • connection electrodes 220 the connection electrodes 220 c joined to the bump electrodes 110 c are commonly connected via the bridge wiring 290.
  • the bridge wiring 290 is not connected to the other wiring pattern 240 and is therefore not connected to any external terminal 260.
  • the plurality of bump electrodes 110c are electrically short-circuited with each other.
  • the bump electrode 110b and the dummy bump electrode 110d are directly connected to a large-area power supply pattern 241 provided on one surface 210a of the insulating base 210.
  • FIG. 13 is a schematic diagram for explaining a connection relationship between the semiconductor chip 100 and the wiring substrate 200.
  • the semiconductor chip 100 includes an internal voltage generation circuit 140 that generates an internal power supply potential VINT.
  • the internal voltage generation circuit 140 receives external power supply potentials VDD and VSS supplied via the external terminal 260 and generates the internal power supply potential VINT based on the external power supply potentials VDD and VSS. Since the internal power supply potential VINT is a potential generated inside the semiconductor chip 100 and is not supplied from the outside, the capability of the internal voltage generation circuit 140 is designed based on the load of the circuit using the internal power supply potential VINT. .
  • the internal power supply depends on the planar position in the semiconductor chip 100.
  • the potential drop of the potential VINT may increase. Such a potential drop is designed to be reduced as much as possible by constructing the power supply wiring network in the semiconductor chip 100 in a mesh shape.
  • the potential is reduced. The decrease may not be sufficiently suppressed.
  • the wiring that supplies such an internal power supply potential VINT is bypassed by the bridge wiring 290.
  • the bridge wiring 290 is a wiring provided on the wiring board 200 side, the film thickness thereof is much thicker than the wiring provided inside the semiconductor chip 100. For this reason, the bridge wiring 290 has a very low resistance.
  • the wiring bypassed using the bridge wiring 290 in the present invention is not limited to the wiring that supplies the internal power supply potential VINT.
  • the wiring bypassed using the bridge wiring 290 in the present invention is not limited to the wiring that supplies the internal power supply potential VINT.
  • FIG. 14 it is possible to connect a wiring for supplying the external power supply potential VSS to the bump electrode 110 c inside the semiconductor chip 100, thereby bypassing the wiring by a bridge wiring 290.
  • the power supply wiring is connected to the bump electrode 110c in the vicinity of each circuit 150A.
  • the influence of noise can be reduced.
  • FIGS. 16 (a) to 16 (c) are process diagrams for explaining the manufacturing process of the bump electrodes 110a and 110c.
  • the uppermost wiring layer included in the semiconductor chip 100 is patterned to form pad electrodes 120a and 120c.
  • a material for the pad electrodes 120a and 120c aluminum is preferably used.
  • the pad electrodes 120a and 120c are covered with a protective film 130 made of a passivation film or a polyimide film so that a part of the pad electrodes 120a and 120c is exposed.
  • the reason why the sizes of the pad electrode 120a and the pad electrode 120c are different depends on whether or not it is necessary to contact the probe of the tester as already described. The test using the probe is performed in the state shown in FIG.
  • the UBM layer 111 is formed on the entire surface.
  • the UBM layer 111 can be formed by sputtering Ti and Cu in this order.
  • a resist film 160 is formed on the surface of the UBM layer 111.
  • the thickness of the resist film 160 is not particularly limited, but is, for example, about 20 ⁇ m.
  • a mask M in which an opening having a predetermined pattern is formed is placed on the semiconductor chip 100, and exposure and development are performed, whereby openings 160a, 160c is formed.
  • a positive resist is illustrated here, a negative resist may be used.
  • the openings 160a and 160c are provided at positions where the bump electrodes 110a and 110c are to be formed.
  • the inner walls of the openings 160a and 160c are substantially vertical. However, the inner walls of the openings 160a and 160c can be inclined by adjusting the focus position during exposure.
  • the pillar portion 112 and the solder layer 113 are formed on the UBM layer 111 exposed at the openings 160a and 160c by performing electroplating. Then, after removing the resist film 160 as shown in FIG. 16B, the UBM layer 111 that is not covered by the pillar portion 112 is removed as shown in FIG. 110c is completed.
  • the bump electrodes 110a and 110c also have a cross-sectional shape reflecting this, and the bump electrode 110X shown in FIGS. 7 to 10 is manufactured. It becomes possible to do.
  • the bump electrodes 110a and 110c are formed simultaneously. Needless to say, the other bump electrodes 110b and 110d are formed at the same time. As already described, the dummy bump electrode 110d is formed on the protective film 130 because the corresponding pad electrode 120 does not exist. After the bump electrodes 110a to 110d are formed, when the semiconductor chip 100 is reflowed at a predetermined temperature, for example, about 240 ° C., the solder layer 113 is melted, and the solder layer 113 becomes hemispherical due to surface tension.
  • a predetermined temperature for example, about 240 ° C.
  • the above process may be performed with respect to each semiconductor chip 100, normally, it is collectively performed with respect to many semiconductor chips 100 in a wafer state.
  • the semiconductor chip 100 is separated into pieces by dicing the wafer.
  • the separated semiconductor chip 100 is flip-chip mounted on the wiring board 200 as described below.
  • FIG. 17A to 17E are process diagrams for explaining a process of flip-chip mounting the semiconductor chip 100 on the wiring board 200.
  • FIG. 17A to 17E are process diagrams for explaining a process of flip-chip mounting the semiconductor chip 100 on the wiring board 200.
  • a large-area insulating base 210X on which a plurality of semiconductor chips 100 can be mounted is prepared, and connection electrodes 220, land patterns 230, solder resists 250, and the like are formed on both surfaces thereof.
  • the broken line D shown to Fig.17 (a) is a dicing line cut
  • the semiconductor chip 100 is bonded to the mounting region defined on the surface of the insulating base 210 by flip chip bonding.
  • Flip chip bonding is performed in an aligned state so that the bump electrode 110 provided on the semiconductor chip 100 and the connection electrode 220 provided on the insulating base 210 are joined. Specifically, the back surface of the semiconductor chip 100 is sucked and held with a bonding tool (not shown), and the bump electrode 110 and the connection electrode 220 are joined while applying a load at a high temperature of about 240 ° C. Thereafter, the underfill 270 is filled in the gap between the wiring substrate 200 and the semiconductor chip 100. The underfill 270 is supplied to a position near the end of the semiconductor chip 100 by a dispenser (not shown), for example, so that the supplied underfill material is filled in a gap between the wiring substrate 200 and the semiconductor chip 100 by capillary action.
  • a dispenser not shown
  • the underfill 270 is filled, the underfill 270 is cured by curing at a predetermined temperature, for example, about 150 ° C., and a fillet as shown in FIG. 17B is formed.
  • a predetermined temperature for example, about 150 ° C.
  • NCP NonasteConductive Paste
  • the entire surface of the wiring substrate 200 is covered with a sealing resin 280 so that the semiconductor chip 100 is embedded, and then, on the land pattern 230 as shown in FIG. External terminals 260 made of solder balls are mounted. Then, as shown in FIG. 17E, if the wiring board 200 is cut along the dicing line D, a plurality of semiconductor devices 10 can be obtained.
  • the underfill 270 is used to fill the gap between the wiring substrate 200 and the semiconductor chip 100 in advance.
  • the gap is filled during molding using a technique such as mold underfill (MUF). Technology may be used.
  • the semiconductor device 10 since the semiconductor device 10 according to the present embodiment has the bridge wiring 290 provided on the wiring substrate 200, the plurality of pad electrodes 120 c provided on the semiconductor chip 100 are bypassed by the bridge wiring 290. . Thereby, the impedance of an arbitrary wiring connected to the pad electrode 120c, for example, a wiring to which an internal power supply potential is supplied can be greatly reduced.
  • FIG. 18 is a schematic cross-sectional view for explaining the structure of the semiconductor chip 100a used in the second embodiment.
  • two minute pad electrodes 120b and 120c are assigned to the bases of the bump electrodes 110b and 110c, respectively. Since the other points are the same as those of the semiconductor chip 100 used in the first embodiment, the same elements are denoted by the same reference numerals, and redundant description is omitted.
  • the wiring board 200 used in the present embodiment is the same as that in the first embodiment.
  • FIG. 19 is a schematic plan view for explaining the shapes of the bump electrodes 110a to 110c
  • FIG. 20 is a schematic cross-sectional view along the line CC ′ shown in FIG.
  • the planar shapes of the bump electrodes 110a, 110b, and 110c are the same as those in the first embodiment.
  • the number of the pad electrodes 120a corresponding to the bump electrodes 110a is one, whereas the number of the pad electrodes 120b and 120c corresponding to the bump electrodes 110b and 110c is two. These two pad electrodes 120b and 120c are covered with corresponding bump electrodes 110b and 110c, respectively.
  • FIG. 21 is a schematic plan view for explaining a first example of the relationship between the pad electrode 120b and the uppermost wiring layer.
  • power supply wirings 411 to 413 extending in the X direction are provided in the uppermost wiring layer.
  • the power supply wirings 411 and 413 are wirings supplied with the power supply potential VDD
  • the power supply wiring 412 is a wiring supplied with the ground potential VSS.
  • the wiring to which the power supply potential VDD is supplied and the wiring to which the ground potential VSS is supplied are often arranged alternately.
  • a part of the power supply wiring 412 is used as two pad electrodes 120b. These two pad electrodes 120 b are arranged in the X direction along the power supply wiring 412.
  • the wiring width of the power supply wiring 412 is not particularly enlarged at a portion corresponding to the pad electrode 120b. Therefore, the other power supply wirings 411 and 413 are not pressed by the pad electrode 120b.
  • the connection resistance can be reduced even if the planar size of the pad electrode 120b is very small.
  • FIG. 22 is a schematic plan view for explaining a second example of the relationship between the pad electrode 120b and the uppermost wiring layer.
  • power supply wirings 421 to 423 extending in the X direction are provided in the uppermost wiring layer.
  • the power supply wirings 421 and 423 are wirings to which the ground potential VSS is applied
  • the power supply wiring 422 is a wiring to which the power supply potential VDD is applied.
  • the wiring to which the power supply potential VDD is applied and the wiring to which the ground potential VSS is applied are alternately arranged.
  • a part of the power supply wiring 421 and a part of the power supply wiring 423 are used as the pad electrode 120b. These two pad electrodes 120b are arranged in the Y direction so as to straddle the power supply wiring 422.
  • the power supply wirings 421 and 423 are not particularly expanded in the width corresponding to the pad electrode 120b. Therefore, the other power supply wiring 422 is not pressed by the pad electrode 120b.
  • one bump electrode 110b can be assigned to two different power supply wirings 421 and 423.
  • the two different power supply wirings 421 and 423 are wirings to which the same potential is applied, but are wirings formed separately from each other in the uppermost wiring layer. Therefore, they are short-circuited in other wiring layers located in lower layers.
  • the connection resistance is reduced even if the planar size of the pad electrode 120b is very small. be able to. Further, as in the example shown in FIG. 22, one bump electrode 110b can be assigned to two different wirings.
  • two pad electrodes 120b and 120c are assigned to the bump electrodes 110b and 110c, respectively, but three or more pad electrodes 120b and 120c may be assigned. Further, it is not essential to assign the plurality of pad electrodes 120b and 120c to all the bump electrodes 110b and 110c, and the plurality of pad electrodes 120b and 120c may be assigned only to some of the bump electrodes 110b and 110c.
  • FIG. 23 is a schematic cross-sectional view for explaining the structure of the semiconductor chip 100b used in the third embodiment.
  • FIG. 24 is a schematic cross-sectional view for explaining the structure of the semiconductor device 20 in which a plurality of semiconductor chips 100 b are stacked on the wiring substrate 200.
  • the semiconductor chip 100b used in this embodiment is different from the semiconductor chip 100 used in the first embodiment in that a through electrode 120X corresponding to the pad electrode 120a is provided.
  • the through electrode 120 ⁇ / b> X is provided through the semiconductor substrate S made of silicon or the like, and is electrically connected to a back surface bump 170 a provided on the back surface of the semiconductor substrate S.
  • the through electrodes 120X corresponding to the other pad electrodes 120b and 120c are not provided, dummy back surface bumps 170b to 170d are provided on the back surface of the semiconductor substrate S at a position overlapping the bump electrodes 110b to 110d in plan view. ing.
  • a plurality of semiconductor chips 100b having such a structure can be mounted on the wiring board 200 in a stacked state.
  • an example in which two semiconductor chips 100b are stacked is shown, but it is also possible to stack three or more semiconductor chips 100b.
  • the back surface bumps 170a to 170d of the semiconductor chip 100b located in the lower layer are joined to the bump electrodes 110a to 110d located in the upper layer.
  • the impedance of the wiring that supplies the internal power supply potential VINT can be reduced by the bridge wiring 290, for example, as in the first embodiment described above.
  • the upper layer semiconductor chip 100b is not directly mounted on the wiring substrate 200, the above effect cannot be obtained.
  • the back surface bump 170c of each semiconductor chip 100b is formed by the bridge wiring 290a as shown in FIG. If short-circuited, the same effect as that of the first embodiment can be obtained for the upper semiconductor chip 100b.
  • the bridge wiring 290a formed on the back surface of the semiconductor chip 100b may be formed at the same time in the formation process of the back surface bumps 170a to 170d.
  • the planar shape of the bump electrode 110a and the back surface bump 170a is also circular. This is because the planar shape of the through electrode 120X is circular.
  • FIG. 26 is a schematic plan view showing the layout of the main surface of the semiconductor chip 100c used in the fourth embodiment.
  • FIG. 27 is a schematic plan view for explaining a conductive pattern formed on the wiring board 200b used in the fourth embodiment.
  • a broken line 100X shown in FIG. 27 is a mounting area of the semiconductor chip 100c.
  • bump electrodes 110a are arranged along the outer periphery.
  • a plurality of bump electrodes 110c are arranged so as to be surrounded by the bump electrodes 110a.
  • the semiconductor chip 100c is not easily peeled off due to a temperature change. Therefore, unlike the first embodiment, the dummy bump electrode 110d is not provided, but the dummy bump electrode 110d may be provided.
  • connection electrodes 220a and 220c are provided at positions corresponding to the bump electrodes 110a and 110c.
  • the connection electrode 220c joined to the bump electrode 110c is commonly connected via the bridge wiring 290b.
  • the bridge wiring 290 b is not connected to the other wiring pattern 240, and thus is not connected to any external terminal 260. Thereby, also in this embodiment, it becomes possible to acquire the same effect as a 1st embodiment mentioned above.
  • the layout of the bump electrode 110 on the semiconductor chip is not particularly limited.
  • FIG. 28 is a schematic cross-sectional view for explaining the structure of the semiconductor device 40 according to the fifth embodiment of the present invention.
  • the semiconductor device 40 according to the present embodiment includes a semiconductor chip 100d and a wiring structure 300 formed on the main surface thereof.
  • the semiconductor device 40 according to the present embodiment has a structure called a so-called wafer level package (WLP), and does not use a rigid insulating base as in the first to fourth embodiments.
  • WLP wafer level package
  • the wiring structure 300 includes a first insulating film 310 covering the main surface of the semiconductor chip 100d, a wiring layer 320 formed on the surface of the first insulating film 310, a second insulating film 330 covering the wiring layer 320, 2 and an external terminal 340 formed on the surface of the insulating film 330.
  • the first insulating film 310 is provided with a plurality of through holes that expose the pad electrode 120, and the pad electrode 120 and the wiring layer 320 are electrically connected through the through holes.
  • the second insulating film 330 is provided with a plurality of through holes that expose the wiring layer 320, and the wiring layer 320 and the external terminal 340 are electrically connected through the through holes.
  • the wiring layer 320 plays a role of converting the electrode pitch of the pad electrode 120 into the electrode pitch of the external terminal 340.
  • FIG. 29 is a schematic plan view showing a layout of the bridge wiring 290 c formed in the wiring layer 320.
  • pad electrodes 120a to 120c are indicated by broken lines.
  • the bridge wiring 290c formed in the wiring layer 320 is provided so as to short-circuit the plurality of pad electrodes 120c.
  • the bridge wiring 290c is not connected to any external terminal 340.
  • the semiconductor device according to the present invention is not limited to a structure in which a semiconductor chip is flip-chip connected to a rigid wiring substrate, but has a structure called a wafer level package as shown in the fifth embodiment.
  • the present invention can also be applied to a semiconductor device.
  • the present invention is not limited to this.
  • a predetermined pad electrode 120e to the connection electrode 220e, it can be drawn out to the wiring 290e on the wiring board 200d, thereby enabling probing even after flip-chip connection. Probing may be performed directly on the wiring 290e or may be performed on a test pad TP provided at the end of the wiring 290e.
  • the pad electrode 120 provided on the semiconductor chip 100e cannot be probed, so the operation test is performed on the external terminal 260 provided on the wiring board 200d. Need to be done through. However, the pad electrode 120e that is not connected to the external terminal 260 cannot be monitored. In order to solve this problem, as shown in FIG. 30, if the pad electrode 120e not connected to the external terminal 260 is drawn out to the wiring 290e on the wiring board 200d, probing is possible. In the example shown in FIG. 30, the test circuit 190 provided in the semiconductor chip 100e is connected to the pad electrode 120e, whereby the test circuit 190 is operated even after flip-chip connection or generated by the test circuit 190. Signal or potential level can be monitored.

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Abstract

【課題】半導体チップ内に設けられた所定の配線のインピーダンスを低下させる。 【解決手段】複数のパッド電極１１０ａ，１１０ｃを有する半導体チップ１００と、半導体チップ１００上に設けられた配線構造体である配線基板２００とを備える。配線基板２００は、複数の外部端子２６０と、外部端子２６０とパッド電極１１０ａとをそれぞれ電気的に接続する複数の配線パターン２４０と、配線基板２００内において外部端子２６０のいずれにも電気的に接続されることなく、複数のパッド電極１１０ｃを電気的に共通接続するブリッジ配線２９０とを有する。本発明によれば、配線構造体に設けられたブリッジ配線２９０が半導体チップ１００内の配線を補助することから、所定の配線のインピーダンスを低下させることが可能となる。

Description

半導体装置
　本発明は半導体装置に関し、特に、半導体チップとその主面上に設けられた配線構造体とを備える半導体装置に関する。
　多くの半導体装置は、半導体チップとこれを収容するパッケージによって構成される。パッケージには外部端子が設けられるとともに、半導体チップに設けられたパッド電極と外部端子とを接続する配線構造体を備えている。一般的なパッケージにおいては、樹脂などからなるリジッドなパッケージ基板が配線構造体として機能する（特許文献１参照）。また、リジッドな基板を用いることなく、半導体チップの主面上に配線構造体を直接形成するウェハレベルパッケージ（ＷＬＰ）と呼ばれるパッケージも存在する。
特開２０１２－３３６１３号公報
　近年においては、ＤＲＡＭ（Dynamic Random Access Memory）などの半導体チップは高速化及び高機能化しているため、半導体チップ内における電源電位の安定性が従来にも増して重要となっている。電源電位を安定化させるためには、電源用の外部端子の数を増やす方法が考えられるが、外部端子の数や配列は規格などによって多くの場合あらかじめ定められているため、電源用の外部端子の数を自由に増加させることは困難である。また、外部から供給される外部電源電位とは異なる内部電源電位を安定化させたい場合には、電源用の外部端子を増やしても効果が期待できない。
　そのため、電源電位の安定性を高めるため、電源用の配線のインピーダンスを低下させることが必要となるが、インピーダンスを低下させるためには、電源用配線の断面積を大きくするために厚く形成する又は、電源用配線層の数を増やす、すなわち、半導体チップに形成された配線層の層数を増加させて電源用配線層を増やすことが考えられる。しかしながら、電源用配線を厚く形成することは、導電体を厚く形成するために半導体チップの製造プロセスに変更を加える必要性があり、また配線層の層数を増やすことは、新たなマスクパターンの形成から行なう必要性があり、コストの面から現実的ではない。
　本発明による半導体装置は、複数の第１のパッド電極及び複数の第２のパッド電極を有する半導体チップと、前記半導体チップ上に設けられた配線構造体と、を備え、前記配線構造体は、複数の外部端子と、前記複数の外部端子と前記複数の第１のパッド電極とをそれぞれ電気的に接続する複数の配線パターンと、前記配線構造体内において前記複数の外部端子のいずれにも電気的に接続されることなく、前記複数の第２のパッド電極を電気的に共通接続するブリッジ配線とを有することを特徴とする。
　本発明によれば、配線構造体に設けられたブリッジ配線が半導体チップ内の配線を補助することから、所定の配線のインピーダンスを低下させることが可能となる。
本発明の第１の実施形態による半導体装置１０の構造を説明するための模式的な断面図である。 半導体チップ１００に設けられたバンプ電極１１０のレイアウトを説明するための略平面図である。 パッド電極１２０を示す略平面図である。 図２に示すＡ－Ａ'線に沿った略断面図である。 バンプ電極１１０ａ～１１０ｃの形状を説明するための略平面図である。 図５に示すＢ－Ｂ'線に沿った略断面図である。 バンプ電極１１０Ｘの形状を示す略断面図である。 はんだ層１１３が溶融した状態を説明するための略断面図である。 バンプ電極１１０Ｘの変形例の形状を示す略断面図である。 バンプ電極１１０Ｘの別の変形例の形状を示す略断面図である。 絶縁基材２１０の一方の表面２１０ａに形成された導電パターンを説明するための略平面図である。 絶縁基材２１０の他方の表面２１０ｂに設けられた外部端子２６０のレイアウトの一例を示す図である。 半導体チップ１００と配線基板２００との接続関係の一例を説明するための模式図である。 半導体チップ１００と配線基板２００との接続関係の他の例を説明するための模式図である。 バンプ電極１１０の作製工程を説明するための工程図である。 バンプ電極１１０の作製工程を説明するための工程図である。 配線基板２００に半導体チップ１００をフリップチップ実装する工程を説明するための工程図である。 第２の実施形態にて用いる半導体チップ１００ａの構造を説明するための略断面図である。 バンプ電極１１０ａ～１１０ｃの形状を説明するための略平面図である。 図１９に示すＣ－Ｃ'線に沿った略断面図である。 パッド電極１２０ｂと最上層の配線層との関係の第１の例を説明するための模式的な平面図である。 パッド電極１２０ｂと最上層の配線層との関係の第２の例を説明するための模式的な平面図である。 第３の実施形態にて用いる半導体チップ１００ｂの構造を説明するための略断面図である。 半導体装置２０の構造を説明するための略断面図である。 半導体チップ１００ｂの裏面バンプ１７０ｃをブリッジ配線２９０ａによって短絡した例を説明するための略平面図である。 第４の実施形態において用いる半導体チップ１００ｃの主面のレイアウトを示す略平面図である。 配線基板２００ｂに形成された導電パターンを説明するための略平面図である。 本発明の第５の実施形態による半導体装置４０の構造を説明するための略断面図である。 配線層３２０に形成されたブリッジ配線２９０ｃのレイアウトを示す略平面図である。 半導体チップ１００ｅと配線基板２００ｄとの接続関係を説明するための模式図である。
　以下、添付図面を参照しながら、本発明の好ましい実施の形態について詳細に説明する。
　図１は、本発明の第１の実施形態による半導体装置１０の構造を説明するための模式的な断面図である。
　図１に示すように、本実施形態による半導体装置１０は、半導体チップ１００と、半導体チップ１００がフリップチップ実装された配線基板２００とを備えている。半導体チップ１００は、シリコン（Ｓｉ）などからなる半導体基板上にトランジスタなどの素子が多数集積されてなる１チップのデバイスである。半導体チップ１００の種類については特に限定されず、ＤＲＡＭ（Dynamic Random Access Memory）などのメモリ系デバイスであっても構わないし、ＣＰＵ（Central Processing Unit）などのロジック系デバイスであっても構わないし、センサなどのアナログ系デバイスであっても構わない。
　配線基板２００は配線構造体として機能する回路基板であり、例えば０．２ｍｍ厚のガラスエポキシならなる絶縁基材２１０と、絶縁基材２１０の一方の表面２１０ａに形成された接続電極２２０と、絶縁基材２１０の他方の表面２１０ｂに形成されたランドパターン２３０とを備える。接続電極２２０とランドパターン２３０とは、絶縁基材２１０に設けられた配線パターン２４０を介して相互に接続されている。配線パターン２４０は、絶縁基材２１０の一方又は他方の表面に形成されていても構わないし、絶縁基材２１０の内層に形成されていても構わない。絶縁基材２１０の一方及び他方の表面のうち、接続電極２２０やランドパターン２３０が形成されていない部分は、ソルダーレジスト２５０によって覆われている。接続電極２２０は、半導体チップ１００に設けられたバンプ電極１１０が接合される電極である。また、ランドパターン２３０には、はんだボールからなる外部端子２６０が接続される。そして、配線基板２００と半導体チップ１００との間にはアンダーフィル２７０が充填され、さらに半導体チップ１００を覆うように封止樹脂２８０が設けられる。
　本実施形態においては、半導体チップ１００に４種類のバンプ電極１１０が設けられている。１種類目のバンプ電極１１０ａは、半導体チップ１００の略中央領域に設けられており、配線パターン２４０を介して外部端子２６０に電気的に接続されている。２種類目のバンプ電極１１０ｂは、半導体チップ１００の外周領域近傍に設けられており、配線パターン２４０を介して外部端子２６０に電気的に接続されている。３種類目のバンプ電極１１０ｃは、半導体チップ１００の外周領域近傍に設けられているが、いずれの外部端子２６０にも電気的に接続されていない。４種類目のバンプ電極１１０ｄは、半導体チップ１００の外周領域近傍に設けられたダミーのバンプ電極であり、いずれの外部端子２６０にも電気的に接続されていない。図１に示すように、バンプ電極１１０ａ～１１０ｃの下地にはパッド電極１２０が設けられている一方、ダミーのバンプ電極１１０ｄに対応するパッド電極は設けられておらず、半導体チップ１００の最表層を覆う保護膜１３０の上面に形成されている。
　図２は、半導体チップ１００に設けられたバンプ電極１１０のレイアウトを説明するための略平面図である。また、図３は、バンプ電極１１０の下地となるパッド電極１２０を示す略平面図である。図４は、図２に示すＡ－Ａ'線に沿った略断面図である。
　図２に示すように、バンプ電極１１０ａは、半導体チップ１００のＹ方向における略中央部においてＸ方向に２列に配列されている。バンプ電極１１０ａは、信号の入出力や外部電源電位の供給に用いられる。図２～図４に示すように、バンプ電極１１０ａに対応するパッド電極１２０ａは、バンプ電極１１０ａよりもやや平面サイズが大きい。
　一方、バンプ電極１１０ｂ～１１０ｄは、半導体チップ１００の外周領域近傍に配列されている。バンプ電極１１０ｂは外部電源電位の供給に用いられ、バンプ電極１１０ｃは後述するブリッジ配線への接続に用いられる。図３及び図４に示すように、バンプ電極１１０ｂ，１１０ｃに対応するパッド電極１２０ｂ，１２０ｃは、対応するバンプ電極１１０ｂ，１１０ｃよりもやや平面サイズが小さい。これらバンプ電極１１０ｂ，１１０ｃは、上述した機能の他、半導体チップ１００と配線基板２００との接合強度を高める役割も果たす。
　つまり、シリコンなどからなる半導体チップ１００と樹脂などからなる配線基板２００は互いに熱膨張率が大きく異なるため、温度が変化すると配線基板２００に反りが生じ、配線基板２００から半導体チップ１００が剥がれてしまうおそれがある。このような現象を防止すべく、剥がれが生じやすい半導体チップ１００の外周領域近傍にバンプ電極１１０ｂ，１１０ｃを配置することによって、両者間の接合強度を高めている。尚、ダミーのバンプ電極１１０ｄは、専ら接合強度を高める目的で用いられている。したがって、図３及び図４に示すように、ダミーのバンプ電極１１０ｄに対応するパッド電極は不要である。
　図５はバンプ電極１１０ａ～１１０ｃの形状を説明するための略平面図であり、図６は図５に示すＢ－Ｂ'線に沿った略断面図である。
　図５に示すように、バンプ電極１１０ａの平面形状は四角形であるのに対し、バンプ電極１１０ｂ，１１０ｃの平面形状は円形である。図示しないが、ダミーのバンプ電極１１０ｄについても平面形状は円形である。ここで、バンプ電極１１０ａの一辺の長さと、バンプ電極１１０ｂ，１１０ｃの直径はほぼ等しくなるよう設計されている。このため、半導体チップ１００の主面と平行な方向における断面積は、バンプ電極１１０ｂ，１１０ｃよりもバンプ電極１１０ａの方が大きい。このことは、所定の間隔（ピッチ）で配置されている四角形のバンプ電極１１０ａを、バンプ電極１１０ｂ、１１０ｃよりも最密且つ低抵抗で配置できることを意味している。
　また、バンプ電極１１０ａに対応するパッド電極１２０ａの平面形状も四角形であり、そのサイズはバンプ電極１１０ａよりもやや大きい。このため、パッド電極１２０ａの外周部分はバンプ電極１１０ａには覆われていない。これに対し、バンプ電極１１０ｂ，１１０ｃに対応するパッド電極１２０ｂ，１２０ｃの平面形状は四角形であるが、そのサイズはバンプ電極１１０ｂ，１１０ｃよりも小さい。このため、パッド電極１２０ｂ，１２０ｃは全面がバンプ電極１１０ｂ，１１０ｃによって覆われた状態である。以上の構成により、バンプ電極１１０ａとパッド電極１２０ａとの接触抵抗は、バンプ電極１１０ｂ，１１０ｃとパッド電極１２０ｂ，１２０ｃとの接触抵抗よりも低くなるため、パッド電極１２０ａを介した信号の送受信や電源の供給を低抵抗に行うことができる。
　パッド電極１２０ａの面積が大きく設計されている一つの理由は、ウェハ状態でのテストを行うためにテスタのプローブを接触可能とするためである。これに対し、パッド電極１２０ｂ，１２０ｃは、ウェハ状態でのテストにおいてプローブを接触させることがないため、その面積が小さく設計されている。また、図３に示すように、パッド電極１２０ｂ，１２０ｃはパッドエリアではない半導体チップ１００の外周領域近傍に配置されており、当該配線層に大面積のパッドを確保することが困難であるという理由も存在する。
　上述の通り、バンプ電極１１０ａの平面形状は四角形であるのに対し、バンプ電極１１０ｂ～１１０ｄの平面形状は円形である。バンプ電極１１０ａの平面形状が四角形である理由は、複数のバンプ電極１１０ａを所定のピッチで配列した場合、半導体チップ１００の主面と平行な方向における断面積を最大とすることができるからである。これにより、バンプ電極１１０ａを介した信号の送受信や電源の供給を低抵抗に行うことが可能となる。これに対し、バンプ電極１１０ｂ～１１０ｄの平面形状が円形である理由は、接合強度を高めるためである。つまり、バンプ電極１１０ｂ～１１０ｄの平面形状が四角形であると、配線基板２００に反りが生じた場合、バンプ電極の角の部分に応力が集中し、ここから剥がれが生じやすくなってしまう。これに対し、バンプ電極１１０ｂ～１１０ｄの平面形状を円形とすれば、特定の箇所に応力が集中しないことから、配線基板２００に反りが生じた場合であっても剥がれが生じにくくなる。このような理由から、バンプ電極１１０ａ～１１０ｄの平面形状を上記の通りに設計しているのである。尚、バンプ電極１１０ｂ～１１０ｄの平面形状については円形に限られず、応力集中が生じにくい形状であれば、いずれの形状であっても好ましい。例えば、正六角形や正八角形のように内角がいずれも鈍角である多角形もまた好ましい。
　次に、バンプ電極１１０の断面形状について説明する。図６に示すように、バンプ電極１１０ａ～１１０ｃは、パッド電極１２０ａ～１２０ｃと接するＵＢＭ（アンダーバリアメタル）層１１１と、ＵＢＭ層１１１上に立設されたピラー部１１２と、ピラー部１１２の上端面１１２ａに設けられたはんだ層１１３とを有する。ＵＢＭ層１１１は例えばＴｉとＣｕの積層膜からなり、ピラー部１１２は例えばＣｕからなる。図６に示すバンプ電極１１０ａ～１１０ｃは四角柱状又は円柱状であり、したがって、ピラー部１１２の上端面１１２ａと側面１１２ｂとが成す角はほぼ直角である。図示しないが、ダミーのバンプ電極１１０ｄについては、対応するパッド電極１２０が存在しない他は、図６に示したバンプ電極１１０ａ～１１０ｃと同様の構造を有している。
　なお、バンプ電極１１０ａ、１１０ｂ、１１０ｃ、１１０ｄのピラー部１１２をメッキで作る場合には、これらが同時に形成されるため、パッド電極１２０ａ、１２０ｂ、１２０ｃ上に形成されるバンプ電極１１０ａ、１１０ｂ、１１０ｃのピラー部１１２の上端面１１２ａよりも絶縁膜バンプ電極１１０ｄのピラー部１１２の上端面１１２ａの位置が高くなる。この場合、バンプ電極１１０ｄのピラー部１１２は他のバンプ電極１１０ａ、１１０ｂ、１１０ｃのピラー部１１２に対してその直径が小さくなるように形成される。バンプ電極１１０ｄのピラー部１１２の直径が小さく形成されることによって、ピラー部１１２の上端面ａの面積が他のバンプ電極１１０ａ、１１０ｂ、１１０ｃのピラー部１１２の上端部ａの面積よりも小さくなり、この上に形成される半田バンプのリフロー後の高さが低くなり、ピラー部１１２の高さを吸収することができるからである。これによって、リフロー後のはんだ層１１３を含むバンプ電極１１０ａ、１１０ｂ、１１０ｃ、１１０ｄの高さは略同一となる。
　図７は、改良されたバンプ電極１１０Ｘの形状を示す略断面図である。図７に示すバンプ電極１１０Ｘは断面が逆台形状であり、したがって、ピラー部１１２の上端面１１２ａと側面１１２ｂとが成す角が鋭角とされている。このような形状を有するバンプ電極１１０Ｘを用いれば、半導体チップ１００を配線基板２００にフリップチップ接続する際、リフローにより溶融したはんだ層１１３がピラー部１１２の側面１１２ｂに回り込みにくくなる。溶融したはんだ層１１３は、表面張力によって図８に示すように半球形に変形するが、はんだ層１１３の厚みが厚い場合、溶融したはんだ層１１３がピラー部１１２の上端面１１２ａからこぼれ、側面１１２ｂに回り込むことがある。しかしながら、上端面１１２ａと側面１１２ｂとが成す角を鋭角としておけば、このようなはんだ層１１３の回り込みが生じにくくなるため、はんだ層１１３のこぼれによる接続不良やショート不良を防止することができる。
　尚、上記の効果を得るためには、ピラー部１１２の側面１１２ｂが全体的に傾斜している必要はなく、図９に示すように、側面１１２ｂのうち上端面１１２ａと接する上部のみが傾斜し、その他の部分は垂直であっても構わない。或いは、図１０に示すように、側面１１２ｂのうち上端面１１２ａと接する上部については上方へ向かうほど径が拡大する方向に傾斜し、側面１１２ｂのうちＵＢＭ層１１１と接する下部については下方へ向かうほど径が拡大する方向に傾斜するスピンドル形状であっても構わない。要するに、ピラー部１１２の上端面１１２ａと、これに接する部分における側面１１２ｂとが成す角が鋭角であれば足りる。
　図１１は、絶縁基材２１０の一方の表面２１０ａに形成された導電パターンを説明するための略平面図である。図１１に示す破線１００Ｘは、半導体チップ１００の搭載エリアである。
　図１１に示すように、絶縁基材２１０の一方の表面２１０ａには、複数の接続電極２２０と、複数の配線パターン２４０と、２つのブリッジ配線２９０とが設けられている。より具体的に説明すると、接続電極２２０のうち、バンプ電極１１０ａに接合される接続電極２２０ａは、配線パターン２４０を介してスルーホール導体２２１に接続されている。スルーホール導体２２１は、絶縁基材２１０を貫通して設けられた導体であり、絶縁基材２１０の他方の表面２１０ｂに設けられたランドパターン２３０及び外部端子２６０に接続される。
　図１２は、絶縁基材２１０の他方の表面２１０ｂに設けられた外部端子２６０のレイアウトの一例を示す図である。図１２に示すように、絶縁基材２１０の他方の表面２１０ｂには、スルーホール導体２２１とランドパターン２３０（外部端子２６０）とを接続する配線パターン２４０が設けられている。
　図１１に戻って、接続電極２２０のうち、バンプ電極１１０ｃに接合される接続電極２２０ｃは、ブリッジ配線２９０を介して共通接続されている。ブリッジ配線２９０は、他の配線パターン２４０に接続されておらず、したがって、いずれの外部端子２６０にも接続されない。このようなブリッジ配線２９０により、複数のバンプ電極１１０ｃは互いに電気的に短絡されることになる。
　尚、バンプ電極１１０ｂやダミーのバンプ電極１１０ｄについては、絶縁基材２１０の一方の表面２１０ａに設けられた大面積の電源パターン２４１に直接接続される。
　図１３は、半導体チップ１００と配線基板２００との接続関係を説明するための模式図である。
　図１３に示すように、半導体チップ１００には内部電源電位ＶＩＮＴを生成する内部電圧生成回路１４０が含まれている。内部電圧生成回路１４０は、外部端子２６０を介して供給される外部電源電位ＶＤＤ，ＶＳＳを受け、これに基づいて内部電源電位ＶＩＮＴを生成する。内部電源電位ＶＩＮＴは、半導体チップ１００の内部で生成される電位であり外部からは供給されないため、内部電源電位ＶＩＮＴを使用する回路の負荷に基づいて内部電圧生成回路１４０の能力が設計されている。しかしながら、内部電源電位ＶＩＮＴを使用する回路が半導体チップ１００内において分散配置されていたり、非常の多くの回路において内部電源電位ＶＩＮＴを使用したりするケースでは、半導体チップ１００内の平面位置によって内部電源電位ＶＩＮＴの電位低下が大きくなることがある。このような電位低下は、半導体チップ１００内の電源配線網をメッシュ状に構築することによってできる限り低減されるよう設計されるが、高速化や高機能化が進んだ半導体チップ１００においては、電位低下を十分に抑制できないことがある。
　本実施形態では、このような内部電源電位ＶＩＮＴを供給する配線をブリッジ配線２９０によってバイパスしている。つまり、半導体チップ１００内の電源配線網だけでなく、配線基板２００に設けられたブリッジ配線２９０を追加的に用いることにより、内部電源電位ＶＩＮＴを供給する配線のインピーダンスを低下させている。しかも、ブリッジ配線２９０は配線基板２００側に設けられる配線であることから、その膜厚は半導体チップ１００の内部に設けられる配線に比べて非常に厚い。このため、ブリッジ配線２９０は非常に低抵抗であり、このようなブリッジ配線２９０を用いて内部電源電位ＶＩＮＴを供給する配線をバイパスさせることにより、内部電源電位ＶＩＮＴの電位低下を大幅に低減することが可能となる。
　但し、本発明においてブリッジ配線２９０を用いてバイパスする配線は、内部電源電位ＶＩＮＴを供給する配線に限定されない。例えば、図１４に示すように、半導体チップ１００の内部において外部電源電位ＶＳＳを供給する配線をバンプ電極１１０ｃに接続し、これにより当該配線をブリッジ配線２９０によってバイパスすることも可能である。これは、例えば電源ノイズの影響を受けやすい回路１５０Ａが分散配置されている一方、電源ノイズの発生源となりうる回路１５０Ｂが存在する場合に、各回路１５０Ａの近傍において電源配線をバンプ電極１１０ｃに接続し、これにより複数の回路１５０Ａ間において電源配線をバイパスさせれば、ノイズの影響を低減することが可能となる。
　次に、バンプ電極１１０の作製工程について説明する。
　図１５（ａ）～（ｄ）及び図１６（ａ）～（ｃ）は、バンプ電極１１０ａ，１１０ｃの作製工程を説明するための工程図である。
　まず、図１５（ａ）に示すように、半導体チップ１００に含まれる最上層の配線層をパターニングすることにより、パッド電極１２０ａ，１２０ｃを形成する。パッド電極１２０ａ，１２０ｃの材料としては、アルミニウムを用いることが好ましい。その後、パッド電極１２０ａ，１２０ｃの一部が露出するよう、これらをパッシベーション膜やポリイミド膜で構成される保護膜１３０で覆う。パッド電極１２０ａとパッド電極１２０ｃのサイズが異なっている理由は、既に説明したとおり、テスタのプローブを接触させる必要があるか否かの違いによる。プローブを用いたテストは、図１５（ａ）に示す状態で行われる。
　次に、図１５（ｂ）に示すように、全面にＵＢＭ層１１１を形成する。ＵＢＭ層１１１の形成は、Ｔｉ及びＣｕをこの順にスパッタリングすることにより行うことができる。次に図１５（ｃ）に示すように、ＵＢＭ層１１１の表面にレジスト膜１６０を形成する。レジスト膜１６０の厚さについては特に限定されないが、例えば２０μｍ程度である。
　次に、図１５（ｄ）に示すように、所定のパターンを有する開口が形成されたマスクＭを半導体チップ１００上に配置し、露光及び現像を行うことで、レジスト膜１６０に開口部１６０ａ，１６０ｃを形成する。ここではポジ型レジストを想定して図示しているが、ネガ型レジストでも構わない。開口部１６０ａ，１６０ｃは、バンプ電極１１０ａ，１１０ｃを形成すべき位置に設けられる。図１５（ｄ）に示す例では、開口部１６０ａ，１６０ｃの内壁がほぼ垂直であるが、露光時におけるフォーカス位置の調整などによって、開口部１６０ａ，１６０ｃの内壁を傾斜させることも可能である。
　次に、図１６（ａ）に示すように、電気めっきを行うことによって開口部１６０ａ，１６０ｃにて露出しているＵＢＭ層１１１上にピラー部１１２及びはんだ層１１３を形成する。そして、図１６（ｂ）に示すようにレジスト膜１６０を除去した後、図１６（ｃ）に示すようにピラー部１１２に覆われていない部分のＵＢＭ層１１１を除去することにより、バンプ電極１１０ａ，１１０ｃが完成する。尚、フォーカス位置の調整などによって開口部１６０ａ，１６０ｃの内壁を傾斜させた場合、バンプ電極１１０ａ，１１０ｃの断面形状もこれを反映した形状となり、図７～図１０に示したバンプ電極１１０Ｘを作製することが可能となる。
　尚、上記の説明ではバンプ電極１１０ａ，１１０ｃを同時に形成しているが、他のバンプ電極１１０ｂ，１１０ｄについてもこれらと同時に形成されることは言うまでもない。既に説明したとおり、ダミーのバンプ電極１１０ｄは対応するパッド電極１２０が存在しないため、保護膜１３０の上に形成される。これらのバンプ電極１１０ａ～１１０ｄを形成した後、半導体チップ１００を所定温度、例えば２４０℃程度でリフローするとはんだ層１１３が溶融し、表面張力によってはんだ層１１３が半球形となる。
　尚、以上の工程は、個々の半導体チップ１００に対して行っても構わないが、通常は、ウェハ状態で多数の半導体チップ１００に対して一括して行われる。そして、上記の工程が終了した後、ウェハをダイシングすることによって半導体チップ１００が個片化される。個片化された半導体チップ１００は、次に説明するように配線基板２００にフリップチップ実装される。
　図１７（ａ）～図１７（ｅ）は、配線基板２００に半導体チップ１００をフリップチップ実装する工程を説明するための工程図である。
　まず、図１７（ａ）に示すように、複数の半導体チップ１００を搭載可能な大面積の絶縁基材２１０Ｘを用意し、その両面に接続電極２２０、ランドパターン２３０及びソルダーレジスト２５０等を形成する。尚、図１７（ａ）に示す破線Ｄは、その後の工程で切断されるダイシングラインである。次に、図１７（ｂ）に示すように、絶縁基材２１０の表面に定義された搭載領域に半導体チップ１００をフリップチップボンディングによって接合する。
　フリップチップボンディングは、半導体チップ１００に設けられたバンプ電極１１０と絶縁基材２１０に設けられた接続電極２２０とが接合するよう、位置合わせされた状態で行う。具体的には、半導体チップ１００の裏面を図示しないボンディングツールで吸着保持し、２４０℃程度の高温で荷重を印加しながら、バンプ電極１１０と接続電極２２０とを接合させる。その後、配線基板２００と半導体チップ１００との間の隙間に、アンダーフィル２７０を充填する。アンダーフィル２７０は、例えば図示しないディスペンサー等により半導体チップ１００の端部近傍位置に供給することで、供給されたアンダーフィル材が毛細管現象により配線基板２００と半導体チップ１００との間の隙間に充填される。
　アンダーフィル２７０を充填した後、所定の温度、例えば１５０℃程度でキュアすることにより、アンダーフィル２７０が硬化され、図１７（ｂ）に示すようなフィレットが形成される。尚、アンダーフィル２７０の代わりに、ＮＣＰ（Non Conductive Paste）を用いても構わない。
　次に、図１７（ｃ）に示すように、半導体チップ１００が埋め込まれるよう配線基板２００の全面を封止樹脂２８０で覆った後、図１７（ｄ）に示すように、ランドパターン２３０上にはんだボールからなる外部端子２６０を搭載する。そして、図１７（ｅ）に示すように、ダイシングラインＤに沿って配線基板２００を切断すれば、複数の半導体装置１０を多数個取りすることができる。
　なお、上記では、予めアンダーフィル２７０によって配線基板２００と半導体チップ１００との間の隙間を充填するものについて説明したが、モールドアンダーフィル（ＭＵＦ）等の技術を使い、モールド時に当該隙間を充填する技術を用いても良い。
　以上説明したように、本実施形態による半導体装置１０は、配線基板２００にブリッジ配線２９０が設けられていることから、半導体チップ１００に設けられた複数のパッド電極１２０ｃをブリッジ配線２９０によってバイパスされる。これにより、パッド電極１２０ｃに接続される任意の配線、例えば、内部電源電位が供給される配線のインピーダンスを大幅に低下させることが可能となる。
　次に、本発明の第２の実施形態について説明する。
　図１８は、第２の実施形態にて用いる半導体チップ１００ａの構造を説明するための略断面図である。
　図１８に示すように、本実施形態にて用いる半導体チップ１００ａにおいては、バンプ電極１１０ｂ，１１０ｃの下地にそれぞれ２つの微小なパッド電極１２０ｂ，１２０ｃが割り当てられている。その他の点については、第１の実施形態にて用いる半導体チップ１００と同じであることから、同一の要素には同一の符号を付し、重複する説明は省略する。また、本実施形態において用いる配線基板２００は、第１の実施形態と同じである。
　図１９はバンプ電極１１０ａ～１１０ｃの形状を説明するための略平面図であり、図２０は図５に示すＣ－Ｃ'線に沿った略断面図である。
　図１９及び図２０に示すように、バンプ電極１１０ａ，１１０ｂ，１１０ｃの平面形状は第１の実施形態と同じである。しかしながら、バンプ電極１１０ａに対応するパッド電極１２０ａがそれぞれ１個であるのに対し、バンプ電極１１０ｂ，１１０ｃに対応するパッド電極１２０ｂ，１２０ｃはそれぞれ２個である。これら２個のパッド電極１２０ｂ，１２０ｃは、それぞれ対応するバンプ電極１１０ｂ，１１０ｃに覆われている。
　図２１は、パッド電極１２０ｂと最上層の配線層との関係の第１の例を説明するための模式的な平面図である。
　図２１に示す例では、最上層の配線層にＸ方向へ延在する電源配線４１１～４１３が設けられている。このうち、電源配線４１１，４１３は電源電位ＶＤＤが与えられる配線であり、電源配線４１２は接地電位ＶＳＳが与えられる配線である。このように、電源電位ＶＤＤが与えられる配線と接地電位ＶＳＳが与えられる配線とは、交互に配置されることが多い。
　そして、図２１に示す例では、電源配線４１２の一部が２箇所のパッド電極１２０ｂとして用いられる。これら２つのパッド電極１２０ｂは、電源配線４１２に沿ってＸ方向に配列されている。電源配線４１２は、パッド電極１２０ｂに相当する箇所において特に配線幅が拡大されておらず、したがって、パッド電極１２０ｂによって他の電源配線４１１，４１３が圧迫されることはない。しかも、１つのバンプ電極１１０ｂに対して２つのパッド電極１２０ｂが割り当てられていることから、パッド電極１２０ｂの平面サイズが微小であっても、接続抵抗を低減することが可能となる。
　図２２は、パッド電極１２０ｂと最上層の配線層との関係の第２の例を説明するための模式的な平面図である。
　図２２に示す例では、最上層の配線層にＸ方向へ延在する電源配線４２１～４２３が設けられている。このうち、電源配線４２１，４２３は接地電位ＶＳＳが与えられる配線であり、電源配線４２２は電源電位ＶＤＤが与えられる配線である。このように、本例においても、電源電位ＶＤＤが与えられる配線と接地電位ＶＳＳが与えられる配線とが交互に配置されている。
　そして、図２２に示す例では、電源配線４２１の一部と電源配線４２３の一部がそれぞれパッド電極１２０ｂとして用いられる。これら２つのパッド電極１２０ｂは、電源配線４２２を跨ぐようにＹ方向に配列されている。電源配線４２１，４２３は、パッド電極１２０ｂに相当する箇所において特に配線幅が拡大されておらず、したがって、パッド電極１２０ｂによって他の電源配線４２２が圧迫されることはない。本例においては、異なる２つの電源配線４２１，４２３に対して１つのバンプ電極１１０ｂが割り当てることができる。ここで、異なる２つの電源配線４２１，４２３とは、同電位が与えられる配線であるものの、当該最上層の配線層においては互いに分離して形成された配線である。したがって、より下層に位置する他の配線層においてこれらは短絡されている。
　このように、本実施形態によれば、１つのバンプ電極１１０ｂに対して２つのパッド電極１２０ｂを割り当てていることから、パッド電極１２０ｂの平面サイズが微小であっても接続抵抗を低抵抗化することができる。また、図２２に示す例のように、異なる２つの配線に対して１つのバンプ電極１１０ｂを割り当てることも可能となる。
　尚、図２１及び図２２においては、バンプ電極１１０ｂとパッド電極１２０ｂとの関係について説明したが、バンプ電極１１０ｃとパッド電極１２０ｃとの関係についても同様である。
　このように、本実施形態においては、上述した第１の実施形態と同様の効果を得ることができるとともに、１つのバンプ電極１１０ｂ，１１０ｃに対して２つのパッド電極１２０ｂ，１２０ｃを割り当てていることから、これらパッド電極１２０ｂ，１２０ｃの平面サイズが微小であっても接続抵抗を低抵抗化することができる。
　尚、本実施形態では、バンプ電極１１０ｂ，１１０ｃにそれぞれ２個のパッド電極１２０ｂ，１２０ｃを割り当てているが、３個以上のパッド電極１２０ｂ，１２０ｃを割り当てても構わない。また、全てのバンプ電極１１０ｂ，１１０ｃに複数のパッド電極１２０ｂ，１２０ｃを割り当てることは必須でなく、一部のバンプ電極１１０ｂ，１１０ｃにのみ複数のパッド電極１２０ｂ，１２０ｃを割り当てても構わない。
　次に、本発明の第３の実施形態について説明する。
　図２３は、第３の実施形態にて用いる半導体チップ１００ｂの構造を説明するための略断面図である。また、図２４は、複数の半導体チップ１００ｂが配線基板２００上に積層されてなる半導体装置２０の構造を説明するための略断面図である。
　図２３に示すように、本実施形態にて用いる半導体チップ１００ｂは、パッド電極１２０ａに対応する貫通電極１２０Ｘが備えられている点において、第１の実施形態にて用いた半導体チップ１００と相違している。貫通電極１２０Ｘはシリコンなどからなる半導体基板Ｓを貫通して設けられており、半導体基板Ｓの裏面に設けられた裏面バンプ１７０ａに電気的に接続されている。他のパッド電極１２０ｂ，１２０ｃに対応する貫通電極１２０Ｘは設けられていないが、平面視でバンプ電極１１０ｂ～１１０ｄと重なる位置における半導体基板Ｓの裏面には、ダミーの裏面バンプ１７０ｂ～１７０ｄが設けられている。
　このような構造を有する半導体チップ１００ｂは、図２４に示すように、複数個積層した状態で配線基板２００上に搭載することができる。図２４に示す例では２個の半導体チップ１００ｂを積層した例を示しているが、３個以上の半導体チップ１００ｂを積層することも可能である。図２４に示すように、下層に位置する半導体チップ１００ｂの裏面バンプ１７０ａ～１７０ｄは、上層に位置するバンプ電極１１０ａ～１１０ｄと接合される。
　かかる構成により、最下層の半導体チップ１００ｂについては、上述した第１の実施形態と同様、ブリッジ配線２９０によって、例えば内部電源電位ＶＩＮＴを供給する配線のインピーダンスを低下させることが可能となる。一方、上層の半導体チップ１００ｂについては、配線基板２００上に直接搭載されないことから、上記の効果を得ることはできないが、各半導体チップ１００ｂの裏面バンプ１７０ｃを図２５に示すようにブリッジ配線２９０ａによって短絡しておけば、上層の半導体チップ１００ｂについても第１の実施形態と同様の効果を得ることができる。半導体チップ１００ｂの裏面に形成するブリッジ配線２９０ａは、裏面バンプ１７０ａ～１７０ｄの形成工程において同時に形成すればよい。尚、本実施形態では、バンプ電極１１０ａ及び裏面バンプ１７０ａについても平面形状を円形としている。これは、貫通電極１２０Ｘの平面形状が円形であることに起因している。
　次に、本発明の第４の実施形態について説明する。
　図２６は、第４の実施形態において用いる半導体チップ１００ｃの主面のレイアウトを示す略平面図である。また、図２７は、第４の実施形態において用いる配線基板２００ｂに形成された導電パターンを説明するための略平面図である。図２７に示す破線１００Ｘは、半導体チップ１００ｃの搭載エリアである。
　図２６に示すように、本実施形態において用いる半導体チップ１００ｃは、外周に沿ってバンプ電極１１０ａが配列されている。そして、バンプ電極１１０ｃについては、これらバンプ電極１１０ａに取り囲まれるように複数個配置されている。本実施形態においては、半導体チップ１００ｃの外周に沿ってバンプ電極１１０ａが配列されていることから、温度変化による半導体チップ１００ｃの剥がれは生じにくい。このため、第１の実施形態とは異なりダミーのバンプ電極１１０ｄは設けられていないが、ダミーのバンプ電極１１０ｄを設けても構わない。
　配線基板２００ｂについては、図２７に示すように、バンプ電極１１０ａ，１１０ｃに対応する位置に接続電極２２０ａ，２２０ｃが設けられる。そして、バンプ電極１１０ｃに接合される接続電極２２０ｃは、ブリッジ配線２９０ｂを介して共通接続されている。第１の実施形態と同様、ブリッジ配線２９０ｂは他の配線パターン２４０に接続されておらず、したがって、いずれの外部端子２６０にも接続されない。これにより、本実施形態においても上述した第１の実施形態と同じ効果を得ることが可能となる。
　このように、本発明においては、半導体チップ上におけるバンプ電極１１０のレイアウトについては特に制限されるものではない。
　次に、本発明の第５の実施形態について説明する。
　図２８は、本発明の第５の実施形態による半導体装置４０の構造を説明するための略断面図である。
　図２８に示すように、本実施形態による半導体装置４０は、半導体チップ１００ｄとその主面に形成された配線構造体３００によって構成されている。本実施形態による半導体装置４０はいわゆるウェハレベルパッケージ（ＷＬＰ）と呼ばれる構造であり、第１～第４の実施形態のようにリジッドな絶縁基材は用いられない。
　配線構造体３００は、半導体チップ１００ｄの主面を覆う第１絶縁膜３１０と、第１絶縁膜３１０の表面に形成された配線層３２０と、配線層３２０を覆う第２絶縁膜３３０と、第２絶縁膜３３０の表面に形成された外部端子３４０とを備える。第１絶縁膜３１０にはパッド電極１２０を露出させる複数の貫通孔が設けられており、これら貫通孔を介してパッド電極１２０と配線層３２０とが電気的に接続される。同様に、第２絶縁膜３３０には配線層３２０を露出させる複数の貫通孔が設けられており、これら貫通孔を介して配線層３２０と外部端子３４０とが電気的に接続される。配線層３２０は、パッド電極１２０の電極ピッチを外部端子３４０の電極ピッチに変換する役割を果たす。
　図２９は、配線層３２０に形成されたブリッジ配線２９０ｃのレイアウトを示す略平面図である。図２９において、破線で示されているのはパッド電極１２０ａ～１２０ｃである。
　図２９に示すように、配線層３２０に形成されたブリッジ配線２９０ｃは、複数のパッド電極１２０ｃを短絡させるように設けられている。これにより、第１～第４の実施形態と同様、ブリッジ配線２９０ｃによって例えば内部電源電位ＶＩＮＴを供給する配線のインピーダンスを低下させることが可能となる。ブリッジ配線２９０ｃは、いずれの外部端子３４０にも接続されない。
　このように、本発明による半導体装置は、半導体チップをリジッドな配線基板上にフリップチップ接続した構造に限定されるものではなく、第５の実施形態に示すようにいわゆるウェハレベルパッケージと呼ばれる構造を持つ半導体装置にも適用することが可能である。
　以上、本発明の好ましい実施形態について説明したが、本発明は、上記の実施形態に限定されることなく、本発明の主旨を逸脱しない範囲で種々の変更が可能であり、それらも本発明の範囲内に包含されるものであることはいうまでもない。
　例えば、上記の各実施形態では、ブリッジ配線を介して複数のパッド電極を短絡させることによって、所定の配線のインピーダンスを低下させた例について説明したが、本発明がこれに限定されるものではなく、図３０に示すように所定のパッド電極１２０ｅを接続電極２２０ｅに接合させることによって、配線基板２００ｄ上の配線２９０ｅに引き出し、これによってフリップチップ接続後においてもプロービングを可能とすることもできる。プロービングは、配線２９０ｅに対して直接行っても構わないし、配線２９０ｅの末端に設けたテスト用パッドＴＰに対して行っても構わない。
　つまり、半導体チップ１００ｅを配線基板２００ｄにフリップチップ接続した後は、半導体チップ１００ｅに設けられたパッド電極１２０に対してプロービングすることはできないため、動作テストは配線基板２００ｄに設けられた外部端子２６０を介して行う必要がある。しかしながら、外部端子２６０に接続されないパッド電極１２０ｅについてはモニタリングが不可能となってしまう。この問題を解決すべく、図３０に示すように、外部端子２６０に接続されないパッド電極１２０ｅを配線基板２００ｄ上の配線２９０ｅに引き出せば、プロービングが可能となる。図３０に示す例では、半導体チップ１００ｅに設けられたテスト回路１９０がパッド電極１２０ｅに接続されており、これによりフリップチップ接続後においてもテスト回路１９０を動作させ、又は、テスト回路１９０によって生成される信号或いは電位レベルをモニタすることが可能となる。
１０，２０，４０　　半導体装置
１００，１００ａ，１００ｂ，１００ｃ，１００ｄ，１００ｅ　　半導体チップ
１００Ｘ　半導体チップの搭載領域
１１０ａ～１１０ｄ，１１０Ｘ　　バンプ電極
１１１　　ＵＢＭ層
１１２　　ピラー部
１１２ａ　ピラー部の上端面
１１２ｂ　ピラー部の側面
１１３　　はんだ層
１２０ａ～１２０ｃ，１２０ｅ　　パッド電極
１２０Ｘ　貫通電極
１３０　　保護膜
１４０　　内部電圧生成回路
１５０Ａ，１５０Ｂ　　回路
１６０　　レジスト膜
１６０ａ，１６０ｃ　　開口部
１７０ａ～１７０ｄ　　裏面バンプ
１９０　　テスト回路
２００，２００ｂ，２００ｄ　　配線基板（配線構造体）
２１０，２１０Ｘ　　絶縁基材
２１０ａ　絶縁基材の一方の表面
２１０ｂ　絶縁基材の他方の表面
２２０ａ，２２０ｃ，２２０ｅ　　接続電極
２２１　　スルーホール導体
２３０　　ランドパターン
２４０　　配線パターン
２４１　　電源パターン
２５０　　ソルダーレジスト
２６０，３４０　　外部端子
２７０　　アンダーフィル
２８０　　封止樹脂
２９０，２９０ａ，２９０ｂ，２９０ｃ　　ブリッジ配線
２９０ｅ　配線
３００　　配線構造体
３１０　　第１絶縁膜
３２０　　配線層
３３０　　第２絶縁膜
４１１～４１３，４２１～４２３　　電源配線
Ｄ　　　　ダイシングライン
Ｍ　　　　マスク
Ｓ　　　　半導体基板
ＴＰ　　　テスト用パッド

Claims (13)

  1. 　複数の第１のパッド電極及び複数の第２のパッド電極を有する半導体チップと、
    　前記半導体チップ上に設けられた配線構造体と、を備え、
    　前記配線構造体は、複数の外部端子と、前記複数の外部端子と前記複数の第１のパッド電極とをそれぞれ電気的に接続する複数の配線パターンと、前記配線構造体内において前記複数の外部端子のいずれにも電気的に接続されることなく、前記複数の第２のパッド電極を電気的に共通接続するブリッジ配線とを有することを特徴とする半導体装置。
  2. 　前記複数の第２のパッド電極には、互いに同じ電源電位が現れることを特徴とする請求項１に記載の半導体装置。
  3. 　前記半導体チップは、前記複数の第１のパッド電極を介して供給される外部電源電位を受けて内部電源電位を生成する内部電圧発生回路をさらに有し、
    　前記複数の第２のパッド電極には、前記内部電源電位が現れることを特徴とする請求項２に記載の半導体装置。
  4. 　前記複数の第２のパッド電極には、前記複数の第１のパッド電極を介して供給される外部電源電位と同じ電位が現れることを特徴とする請求項２に記載の半導体装置。
  5. 　前記複数の第１のパッド電極の面積は、前記複数の第２のパッド電極の面積よりも大きいことを特徴とする請求項１に記載の半導体装置。
  6. 　前記半導体チップは、前記複数の第１のパッド電極上にそれぞれ形成された複数の第１のバンプ電極と、前記複数の第２のパッド電極上にそれぞれ形成された複数の第２のバンプ電極とをさらに有し、
    　前記配線構造体は、絶縁基材と、前記複数の第１のバンプ電極にそれぞれ接合された複数の第１の接続電極と、前記複数の第２のバンプ電極にそれぞれ接合された複数の第２の接続電極とをさらに有し、
    　前記複数の外部端子は、前記絶縁基材の一方の表面に形成され、
    　前記複数の第１及び第２のバンプ電極は、前記絶縁基材の他方の表面に形成され、
    　前記複数の配線パターンは、前記複数の第１の接続電極と前記複数の外部端子とを電気的に接続し、
    　前記ブリッジ配線は、前記複数の第２の接続電極を電気的に共通接続することを特徴とする請求項１に記載の半導体装置。
  7. 　前記複数の第１のバンプ電極は前記半導体チップの主面の中央領域に配置され、前記複数の第２のバンプ電極は前記半導体チップの前記主面の外周領域に配置されていることを特徴とする請求項６に記載の半導体装置。
  8. 　前記複数の第１のバンプ電極の平面形状は四角形であり、前記複数の第２のバンプ電極の平面形状は内角がいずれも鈍角である多角形又は円形であることを特徴とする請求項７に記載の半導体装置。
  9. 　前記複数の第１及び第２のバンプ電極のそれぞれは、対応する前記第１又は第２のパッド電極上に立設されたピラー部と、前記ピラー部の上端面に設けられたはんだ層とを含み、
    　前記ピラー部の前記上端面と、前記上端面に接する側面とが成す角が鋭角であることを特徴とする請求項６に記載の半導体装置。
  10. 　前記半導体チップは、前記複数の第１のパッド電極上にそれぞれ形成された複数の第１のバンプ電極と、前記複数の第２のパッド電極に含まれる２以上の前記第２のパッド電極を覆うように設けられ、前記２以上の第２のパッド電極に共通接続された第２のバンプ電極とをさらに有することを特徴とする請求項１に記載の半導体装置。
  11. 　前記２以上の第２のパッド電極の一つは、前記半導体チップの最上層の配線層に形成された第１の配線に設けられ、
    　前記２以上の第２のパッド電極の他の一つは、前記最上層の配線層に形成され、少なくとも前記最上層の配線層において前記第１の配線とは分離して形成された第２の配線に設けられていることを特徴とする請求項１０に記載の半導体装置。
  12. 　前記第１の配線と前記第２の配線は、前記最上層の配線層とは異なる配線層を介して短絡されていることを特徴とする請求項１１に記載の半導体装置。
  13. 　前記配線構造体は、前記複数の第１及び第２のパッド電極が形成された前記半導体チップの主面を覆う絶縁層と、前記絶縁層を貫通して設けられ、前記複数の第１及び第２のパッド電極を露出させる複数の貫通孔とをさらに有し、
    　前記配線パターン及び前記ブリッジ配線は、前記第１の絶縁層上及び前記複数の貫通孔内に設けられた導電体からなることを特徴とする請求項１に記載の半導体装置。
PCT/JP2014/056185 2013-03-13 2014-03-10 半導体装置 WO2014142075A1 (ja)

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