JP6680705B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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JP6680705B2
JP6680705B2 JP2017023207A JP2017023207A JP6680705B2 JP 6680705 B2 JP6680705 B2 JP 6680705B2 JP 2017023207 A JP2017023207 A JP 2017023207A JP 2017023207 A JP2017023207 A JP 2017023207A JP 6680705 B2 JP6680705 B2 JP 6680705B2
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Prior art keywords
bump
semiconductor device
protective layer
electrode
opening
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JP2018129475A (ja
Inventor
拓 加本
拓 加本
達夫 右田
達夫 右田
渡辺　慎也
慎也 渡辺
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Kioxia Corp
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Kioxia Corp
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Priority to JP2017023207A priority Critical patent/JP6680705B2/ja
Priority to TW109130967A priority patent/TWI783264B/zh
Priority to TW106124853A priority patent/TWI720233B/zh
Priority to CN201710651125.4A priority patent/CN108417550B/zh
Priority to US15/694,998 priority patent/US10115689B2/en
Publication of JP2018129475A publication Critical patent/JP2018129475A/ja
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Description

本発明の実施形態は、半導体装置及びその製造方法に関する。
半導体装置の製造において、半導体装置が形成された基板を他の半導体装置や配線が形成された基板にバンプを介してフリップチップ接続する際、一方の基板表面に予め形成された電極に対して他方の基板に設けられたバンプを接続する。このとき電極は基板表面に形成された開口部に埋め込まれて形成されており、電極表面は開口部に沿って凹形状表面となることがある。凹形状表面の電極にバンプを接合する際、凹部において空気等の気体をかみ込むおそれがあり、接合箇所にボイドが発生する場合がある。
特開２００７−２５０５６１号公報
本実施形態が解決しようとする課題は、基板接合の信頼性を高めた半導体装置及びその製造方法を提供する。
実施形態の半導体装置は、第一の配線電極が表面に設けられた第一の半導体基板と、前記半導体基板上に形成され、前記第一の配線電極上に開口部を有する第一の保護層と、前記第一の保護層の開口部に形成された第一のバンプ電極と、前記第一のバンプ電極に接合されたバンプ径が３０μｍ以下のバンプと、を有する。前記開口部に形成された前記第一のバンプ電極の底面の径は前記第一の保護層の膜厚の１．５倍以下である。前記第一のバンプ電極は表面に凹部が形成され、前記第一のバンプ電極の上層表面の最上部と最下部との差が１．５μｍ以下である。前記第一の保護層の膜厚は５μｍ以上である
実施形態に係る半導体装置の構成を説明する図。 図１の半導体装置の製造方法を説明する図。 図１の半導体装置の製造方法を説明する図. 実施形態の変形例に係る半導体装置の構成を説明する図。
以下、発明を実施するための実施形態について説明する。
（実施形態）
本実施形態に係る半導体装置について図１、図２、及び図３を参照して説明する。なお、以下の図面の記載において、同一部分は同一符号で表している。ただし、図面は厚さと平面寸法との関係、比率等は現実のものとは異なり、模式的なものである。
本実施形態に係る半導体装置の構成について図１を用いて説明する。図１は本実施形態の半導体装置の構成を示す断面図である。
図１に示すように、本実施形態に係る半導体装置１は、第一の半導体装置１０と第二の半導体装置３０とを有し、第一の半導体装置１０と第二の半導体装置３０とが導電性のバンプ２０により接合され、各々電気的に接続されている。
第一の半導体装置１０は、シリコン基板等の第一の半導体基板１００、第一の配線電極１０１、第一の保護層１０２、第一のバリア膜１０３、及び第一のバンプ電極１０４を備えている。
第一の半導体基板１００には、それぞれ図示を省略するが半導体素子、素子と電気的に接続されたＣｕ等の導電配線層、及び層間絶縁層が設けられている。第一の半導体基板１００の表面には、配線層を介して半導体素子と接続された第一の配線電極１０１が形成されている。第一の配線電極１０１は、たとえばＡｌ、Ｃｕ、Ｎｉ、Ａｕ、Ａｇ、またはそれらの合金からなる導電体である。
第一の配線層１０１上には、絶縁性の第一の保護層１０２が形成されている。第一の保護層１０２は、たとえば、シリコン酸化膜、シリコン窒化膜、およびポリイミド等のいずれか単層またはそれらの複数層で構成される。第一の保護層１０２の膜厚は５μｍである。第一の保護層１０２の膜厚を５μｍ以上にすることで半導体基板１００に形成された半導体素子や配線層等の内部構造を効果的に保護することができる。第一の保護層１０２には、第一の配線層１０１上に開口部が形成されている。
第一の保護層１０２の開口部の底面並びに側面、及び第一の保護層１０２の開口部近傍の上部には、第一のバリア膜１０３が形成されている。第一のバリア膜１０３は、Ｔｉ、ＴｉＮ、Ｔａ、及びＴａＮ等のいずれか単層またはそれらの積層で構成され、均等の膜厚で形成される。なお場合によっては第一のバリア膜１０３を形成しなくともよい。
第一のバリア膜１０３上には第一のバンプ電極１０４が形成され、第一の保護層１０２の開口部は第一のバンプ電極１０４により埋められる。第一のバンプ電極１０４は、Ｃｕ、Ｎｉ、Ａｕ、Ａｇ、Ｐｄ、Ａｌ及びそれらの合金、のいずれか単層またはそれらの積層で構成され、たとえば、Ｃｕめっきシード層とＣｕめっき層の積層から構成されるＣｕピラー層である。
第一のバンプ電極１０４の膜厚は３μｍである。ここで膜厚は、第一の保護層１０２上に設けられた第一のバンプ電極１０４の膜厚をいう。複数の半導体基板が積層された半導体装置では、バンプ電極１０４の膜厚を３μｍ以下とすることによって、各半導体基板間の距離を抑えることができ半導体装置全体を小型化することができる。
第一の保護層１０２の開口部の開口径は５μｍ以下である。第一のバリア膜１０３が開口部内部に形成されている場合は、第一のバリア膜１０３が形成された開口部の開口径が５μｍ以下であれば好ましい。すなわち、開口部に埋め込まれた第一のバンプ電極１０４底面の径が５μｍ以下であれば好ましい。ここで開口部に埋め込まれた第一のバンプ電極１０４底面の径は、特定の方向において５μｍ以下であればよいが、いずれの方向においても５μｍ以下であればさらに好ましい。
このように開口径を小さくすることで、第一のバンプ電極１０４を開口部に埋め込み形成する際に、開口部上部に設けられる第一のバンプ電極１０４表面の凹み量を抑制できる。ここで第一のバンプ電極１０４表面の凹み量は、第一のバンプ電極１０４の上層表面の最上部と最下部の差とする。
バンプを接合する電極表面の凹み量が３〜５μｍ以上になると、電極とバンプ間またはバンプ内部で空気をかみこみ、ボイドが発生し易い。ボイドが発生すると、バンプ接合における電気抵抗が増加したり、物理的な接合信頼性が悪化したりする。本実施形態では、開口部に埋め込まれた第一のバンプ電極１０４底面の径を第一の保護層１０２の膜厚以下にすることで、開口部を第一のバンプ電極１０４で十分に閉じることができ、第一のバンプ電極１０４表面の凹み量を１μｍ以下に抑えることができる。さらに、開口部に埋め込まれた第一のバンプ電極１０４底面の径を第一の保護層１０２の膜厚の１．５倍以下としても、第一のバンプ電極１０４表面の凹み量を１．５μｍ以下に抑えることができる。
第一のバンプ電極１０４上には、バンプ２０が形成されている。バンプ２０の材料は、Ｃｕ，Ｓｎ、Ｐｂ、Ａｕ、Ａｇ、Ｐｄ、Ｎｉ、またはこれらの合金で構成される。バンプ２０は、バンプ径が３０μｍ以下のマイクロバンプであり、また第一の半導体装置１０の同一表面側に設けられた少なくとも一つの他のバンプとの距離（バンプピッチ）を６０μｍ以下と小さくすることで、半導体装置全体を小型化できる。
一般にバンプ径が、８０μｍ、１００μｍ、１５０μｍもしくはそれ以上の大きさの場合には、バンプとバンプ電極との接合箇所に生じるボイドはバンプの大きさに比べて相対的に小さいため接合信頼性が問題になることは少ない。反対に、バンプ径が３０μｍ以下のマイクロバンプを用いる場合、バンプとバンプ電極との接合箇所に生じるボイドがバンプの大きさに対して相対的に大きくなるため接合信頼性の問題が生じやすい。
本実施形態に係る半導体装置１では、マイクロバンプを用いて小型化を図りつつ、第一の保護層１０２の膜厚と第一のバンプ電極１０４の径を適切な大きさに調整することにより、第一のバンプ電極１０４表面の凹み量を抑えているため、図１に示したようにバンプとバンプ電極との接合箇所にボイドを発生させない、あるいは接合箇所のボイドの大きさを十分に抑えることができるため、接合信頼性を高めることができる。
バンプ２０を介して、第二の半導体装置３０が第一の半導体装置１０と接合されている。第二の半導体装置３０は、シリコン基板等の第二の半導体基板３００、第二の配線電極３０１、第二の保護層３０２、第二のバリア膜３０３、及び第二のバンプ電極３０４を備えている。
第二の半導体基板３００には、それぞれ図示を省略するが半導体素子、素子と電気的に接続されたＣｕ等の導電配線層、及び層間絶縁層が設けられている。第二の半導体基板３００の表面には、Ｃｕ配線層を介して半導体素子と接続された第二の配線電極３０１が形成されている。第二の配線電極３０１は、たとえばＮｉ、Ａｕ、Ｃｕ、Ａｌなどの導電材である。
第二の配線層３０１上には、絶縁性の第二の保護層３０２が形成されている。第二の保護層３０２は、たとえば、シリコン酸化膜、シリコン窒化膜、およびポリイミド等のいずれか単層またはそれらの複数層で構成される。第一の保護層１０２と同様、第二の保護層３０２の膜厚を５μｍ以上にすることで半導体基板上の素子構造を効果的に保護することができる。第二の保護層３０２には、第二の配線層３０１上部に開口部が形成されている。
第二の保護層３０２の開口部の底面並びに側面、及び第二の保護層３０２の開口部近傍の上部には、第二のバリア膜３０３が形成されている。第二のバリア膜３０３は、第一バリア膜１０３と同様の材料および構造を採用できる。また第二のバリア膜３０３は必ずしも形成しなくともよい。
第二のバンプ電極３０４が、第二のバリア膜３０３上で、第二の保護層３０２の開口部内に埋められる。第二のバンプ電極３０４は、第一のバンプ電極１０４と同様の材料または構造であり、その膜厚は、第一のバンプ電極１０４と同様、３μｍ以下とすることにより半導体装置全体を小型化することができる。
第二のバンプ電極３０４上にはバンプ２０が形成されており、バンプ２０を介して半導体装置２０と半導体装置１０は電気的および物理的に接続されている。
続いて、本実施形態に係る半導体装置の製造方法について、図２及び図３を用いて説明する。図２および図３は本実施形態の半導体装置の製造方法を示す工程断面図である。
まず、図２（ａ）に示すように、第一の半導体装置１０の第一の半導体基板１００を用意する。第一の半導体基板１００には、図示を省略するが、半導体素子、素子と電気的に接続されたＣｕ等の導電配線層、及び層間絶縁層が設けられている。第一の半導体基板１００の表面に、配線層を介して半導体素子と電気的に接続する第一の配線電極１０１を形成する。さらに第一の半導体基板１００の表面に、第一の配線電極１０１を覆うように、ＣＶＤ法等により膜厚５μｍの第一の保護層１０２を形成する。その後、リソグラフィおよびドライエッチングにより、第一の保護層１０２に開口径５μｍ程度の開口部を設け、第一の配線電極１０１の一部を開口部から露出する。
次に、図２（ｂ）に示すように、スパッタ法等により第一のバリア膜１０３を、第一の保護層１０２の上面および開口部の底面および側面に形成する。その後、フォトレジスト１０５を第一のバリア膜１０３上に形成した後、リソグラフィによりフォトレジスト１０５に開口部を設け、第一のバリア膜１０３の一部を露出させる。
その後、図２（ｃ）に示すように、電気めっき法を用いて、フォトレジスト１０５の開口部内で露出したバリア膜１０３上に第一のバンプ電極１０４を形成することで、第一のバンプ電極１０４が第一の保護層１０２の開口部に埋め込まれる。第一のバンプ電極１０４の材料はＣｕであり、膜厚は３μｍとする。このとき第一の保護層１０２の開口部上方で、第一のバンプ電極１０４の表面に微小な凹部が生じるが、凹み量は抑制されている。第一のバンプ電極１０４を形成した後、フォトレジスト１０５をアッシングにより除去し、さらに露出した第一のバリア膜１０３も除去する。以上、図２（ａ）乃至図２（ｃ）に示したように第一の半導体装置１０を製造する。
次に、図３（ａ）に示すように、第一の半導体装置１０と同様の方法により、第二の半導体装置３０を製造する。第二の半導体基板３００を用意し、第二の配線電極３０１、第二の保護層３０２、第二のバリア膜３０３、フォトレジスト３０５、及び第二のバンプ電極３０４をそれぞれ形成する。
続いて、図３（ｂ）に示すように、電気めっきにより、フォトレジスト３０５の開口部の第二のバンプ電極３０４上にＳｎ合金等のはんだ層２０１を形成する。はんだ層２０１を形成した後、フォトレジスト３０５およびフォトレジスト３０５下方の第二のバリア膜３０３をともに除去する。
次に、図３（ｃ）に示すように、熱処理によりはんだ層２０１を溶融して、第二の半導体装置３０上にバンプ２０を形成する。バンプ２０は、バンプ径が３０μｍ以下のマイクロバンプである。また図示を省略するが、バンプ２０は、第二の半導体基板３００の同一表面側に複数同時に形成され、それぞれのバンプ間距離は６０μｍ以下とする。
最後に、図３（ｄ）に示すように、熱圧着により、第二の半導体装置３０上に形成されたバンプ２０を第一の半導体装置１０の第一のバンプ電極１０４に押し付け、その後冷却することにより第一の半導体装置１０と第一の半導体装置３０をバンプ２０で接合する。第一のバンプ電極１０４表面には凹部が形成されているものの、凹部の凹み量が小さいため、バンプ２０を第一のバンプ電極１０４に圧着する過程で空気がかみ込まれる恐れがなく、ボイドが生じないため接合信頼性を高めることができる。
なお、他のバンプ接合技術として、バンプを第一の半導体装置上にも予め設けておき、第一の半導体装置上のバンプと第二の半導体装置上のバンプを接合する技術も知られている。これに対し、本実施形態の半導体装置の製造方法では、第二の半導体装置上にのみバンプを形成して第一の半導体装置に接合しているため、はんだ使用量を低減することができる。
図４は、本実施形態の半導体装置の構成の変形例を示す図である。図４に示すとおり、本変形例に係る半導体装置は、図１で示した半導体装置の第二の半導体装置３０上にバンプ４０を介してさらに第三の半導体装置５０を積層した構成を有する。
第二の半導体装置３０は、第二の半導体基板３００内に基板貫通方向に伸びる導電性のビア３０６が形成されている。ビア３０６はＣｕなどの導体材料で構成され、第一の半導体装置１０側の端部で第二の配線電極３０１と電気的に接続されている。またビア３０６は、反対側の端部においても第二の配線電極３０７と電気的に接続されている。
第二の配線電極３０７上には、第一の半導体装置１０における第一の保護層１０２、第一のバリア膜１０３、及び第一のバンプ電極１０４と同様の構成、材料、サイズ、配置で、第二の保護層３０８、第二のバリア膜３０９、及び第二のバンプ電極３１０が設けられている。ここで、第二のバンプ電極３１０表面の凹み量は、第一のバンプ電極１０４表面の凹み量と同様、十分に抑えられている。
第二のバンプ電極３１０上には導電性バンプ４０が接合され、さらにバンプ４０上には第三の半導体装置５０が接合されている。第三の半導体装置５０の構成は、第二の半導体装置３０の構成、材料、サイズ、配置と同様であり、シリコン基板等の第三の半導体基板５００、第三の配線電極５０１、第三の保護層５０２、第三のバリア膜５０３、及び第三のバンプ電極５０４を備えている。バンプ４０は、第二のバンプ電極３１０と第三のバンプ電極５０４間を接合して、第二の半導体装置３０と第三の半導体装置５０との電気的接続を確立する。
以上説明した本変形例に係る半導体装置では、半導体基板の貫通方向に伸びるビアを設けることにより、積層された３以上の半導体装置をコンパクトに保ちつつ各々の電気的接続を図ることができる。また、バンプ接合におけるボイドの発生を抑えられるため、接合信頼性を高めることができる。
以上、本発明の実施形態を説明したが、本実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
１ 半導体装置
１０ 第一の半導体装置
２０、４０ バンプ
３０ 第二の半導体装置
５０ 第三の半導体装置
１００ 第一の半導体基板
１０１ 第一の配線電極
１０２ 第一の保護層
１０３ 第一のバリア膜
１０４ 第一のバンプ電極
３００ 第二の半導体基板
３０１、３０７ 第二の配線電極
３０２、３０８ 第二の保護層
３０３、３０９ 第二のバリア膜
３０４、３１０ 第二のバンプ電極
３０６ ビア
５００ 第三の半導体基板
５０１ 第三の配線電極
５０２ 第三の保護層
５０３ 第三のバリア膜
５０４ 第三のバンプ電極

Claims (5)

  1. 第一の配線電極が表面に設けられた第一の半導体基板と、
    前記半導体基板上に形成され、前記第一の配線電極上に開口部を有する第一の保護層と、
    前記第一の保護層の開口部に形成された第一のバンプ電極と、
    前記第一のバンプ電極に接合されたバンプ径が３０μｍ以下のバンプと、
    を有し、
    前記開口部に形成された前記第一のバンプ電極の底面の径が、前記第一の保護層の膜厚の１．５倍以下であり、
    前記第一のバンプ電極は表面に凹部が形成され、
    前記第一のバンプ電極の上層表面の最上部と最下部との差が１．５μｍ以下であり、
    前記第一の保護層の膜厚は５μｍ以上である
    ことを特徴とする半導体装置。
  2. 前記開口部に形成された前記第一のバンプ電極の底面の径が、前記第一の保護層の膜厚以下であることを特徴とする請求項１記載の半導体装置。
  3. 前記第一のバンプ電極は前記第一の保護層上にも形成され、前記第一の保護層上の前記第一のバンプ電極の膜厚は３μｍ以下であることを特徴とする請求項１または２記載の半導体装置。
  4. 前記バンプと、前記第一の半導体基板の同一表面側に設けられた他のバンプとの距離が６０μｍ以下であることを特徴とする請求項１乃至３のいずれか一項記載の半導体装置。
  5. 開口部を有する第一の保護層と前記開口部に形成された第一のバンプ電極とを表面に備えた半導体基板を用意し、
    前記第一のバンプ電極にバンプ径が３０μｍ以下のバンプを接合する半導体装置の製造方法であって、
    前記開口部に形成された前記第一のバンプ電極の底面の径が、前記第一の保護層の膜厚の１．５倍以下であり、
    前記第一のバンプ電極は表面に凹部が形成され、
    前記第一のバンプ電極の上層表面の最上部と最下部との差が１．５μｍ以下であり、
    前記第一の保護層の膜厚は５μｍ以上であることを特徴とする半導体装置の製造方法。
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