TWI587418B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

Info

Publication number
TWI587418B
TWI587418B TW105103350A TW105103350A TWI587418B TW I587418 B TWI587418 B TW I587418B TW 105103350 A TW105103350 A TW 105103350A TW 105103350 A TW105103350 A TW 105103350A TW I587418 B TWI587418 B TW I587418B
Authority
TW
Taiwan
Prior art keywords
electrode
substrate
resist layer
layer
wafer
Prior art date
Application number
TW105103350A
Other languages
English (en)
Other versions
TW201711113A (zh
Inventor
Shinya Watanabe
Original Assignee
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of TW201711113A publication Critical patent/TW201711113A/zh
Application granted granted Critical
Publication of TWI587418B publication Critical patent/TWI587418B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05084—Four-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13084—Four-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H01L2224/16012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/16013—Structure relative to the bonding area, e.g. bond pad the bump connector being larger than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16112—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29012—Shape in top view
    • H01L2224/29013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29012—Shape in top view
    • H01L2224/29014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/053—Oxides composed of metals from groups of the periodic table
    • H01L2924/0544—14th Group
    • H01L2924/05442—SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

半導體裝置及其製造方法 【相關申請案】
本申請案享有以日本專利申請案2015-174753號(申請日：2015年9月4日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
本發明之實施形態係關於一種半導體裝置及其製造方法。
有半導體晶片具備被稱為TSV(Through Silicon Via，矽穿孔)電極之貫通電極之情形。TSV電極包含形成於基板之正面側之正面電極、及形成於基板之背面側之背面電極。於基板之正面側形成有電晶體或多層配線。正面電極介隔多層配線而形成於基板之正面側，背面電極係以於基板之背面側與基板內到達多層配線之方式形成。
於將具備TSV電極之半導體晶片彼此電性連接之情形時，將一個晶片積層於另一晶片上，且將一個晶片之背面電極與另一晶片之正面電極接合。然而，於該情形時，有難以使該等晶片間之距離充分短之問題。
本發明之實施形態提供一種能夠縮短將半導體晶片彼此積層之情形時之半導體晶片間之距離之半導體裝置及其製造方法。
根據一實施形態，半導體裝置具備：基板；第1電極，其設置於上述基板之上表面側；及第2電極，其設置於上述基板之下表面側， 且與上述第1電極電性連接。上述裝置進而具備：第1阻劑層，其以包圍上述第1電極之方式設置於上述基板之上述上表面側，且與上述第1電極隔開；及第2阻劑層，其設置於上述基板之上述下表面側。
1‧‧‧基板
2‧‧‧第1絕緣膜
3‧‧‧層間絕緣膜
4‧‧‧配線部
5‧‧‧正面電極
5a‧‧‧第1電極層
5b‧‧‧第2電極層
5c‧‧‧第3電極層
5d‧‧‧第4電極層
6‧‧‧第2絕緣膜
7‧‧‧背面電極
7a‧‧‧第1電極層
7b‧‧‧第2電極層
7c‧‧‧第3電極層
7d‧‧‧第4電極層
8‧‧‧正面阻劑層
9‧‧‧背面阻劑層
10‧‧‧阻劑層
E‧‧‧凹部
C1‧‧‧半導體晶片
C2‧‧‧半導體晶片
C3‧‧‧半導體晶片
E‧‧‧開口部
F1‧‧‧上表面
F2‧‧‧下表面
F3‧‧‧上表面
H‧‧‧貫通孔
K‧‧‧區域
L1‧‧‧長度
L2‧‧‧長度
R1‧‧‧區域
R2‧‧‧區域
R3‧‧‧區域
S1‧‧‧正面
S2‧‧‧背面
S3‧‧‧側面
T1‧‧‧厚度
T2‧‧‧厚度
T3‧‧‧厚度
V‧‧‧孔隙
α‧‧‧外周
β‧‧‧內周
圖1係表示第1實施形態之半導體裝置之構造之剖視圖。
圖2及圖3係表示第1實施形態之半導體晶片之連接方法之剖視圖。
圖4(a)~圖5(b)係表示第1實施形態之半導體裝置之背面側之構造之俯視圖。
圖6(a)~(c)係表示第1實施形態之半導體裝置之正面側之構造之俯視圖。
圖7係表示第1實施形態之比較例之半導體裝置之構造之剖視圖。
圖8及圖9係表示第1實施形態之比較例之半導體晶片之連接方法之剖視圖。
圖10(a)~圖14(b)係表示第1實施形態之半導體裝置之製造方法之剖視圖。
以下，參照圖式說明本發明之實施形態。
(第1實施形態)
圖1係表示第1實施形態之半導體裝置之構造之剖視圖。圖1表示1個半導體晶片之剖面。
圖1之半導體裝置具備基板1、第1絕緣膜2、層間絕緣膜3、配線部4、正面電極(正面凸塊)5、第2絕緣膜6、背面電極(背面凸塊)7、正面阻劑層8及背面阻劑層9。正面電極5與背面電極7係第1及第2電極之例。正面阻劑層8與背面阻劑層9係第1及第2阻劑層之例。
基板1之例為矽基板等半導體基板。符號S1表示基板1之正面(上表面)。符號S2表示基板1之背面(下表面)。符號S3表示設置於基板1之正面S1與背面S2之間之貫通孔H之側面。圖1表示與基板1之正面S1或背面S2平行且相互垂直之X方向及Y方向、以及與基板1之正面S1及背面S2垂直之Z方向。於本說明書中，將+Z方向視作上方向，將-Z方向視作下方向。本實施形態之-Z方向既可與重力方向一致，亦可不與重力方向一致。基板1之厚度例如為33μm。
第1絕緣膜2形成於基板1之正面S1。第1絕緣膜2係以包圍貫通孔H之方式形成。第1絕緣膜2之例為氧化矽膜或氮化矽膜。
層間絕緣膜3介隔第1絕緣膜2而形成於基板1之正面S1。層間絕緣膜3之例為氧化矽膜或氮化矽膜。
配線部4包含多層配線、及將該等配線彼此連接之插塞。配線部4介隔第1絕緣膜2而形成於基板1之正面S1，且由層間絕緣膜3覆蓋。配線部4之例為各種金屬層。
正面電極5形成於基板1之正面S1側。正面電極5介隔層間絕緣膜3而形成於配線部4上，且電性連接於配線部4。符號F3表示正面電極5之上表面。正面電極5之上表面F3具有於形成正面電極5時所形成之凹部B。符號T3表示層間絕緣膜3之上表面上之正面電極5之厚度。厚度T3例如為3μm。符號α表示正面電極5之外周。
正面電極5依序包含第1電極層5a、第2電極層5b、第3電極層5c及第4電極層5d。第1電極層5a之例為鈦(Ti)層。第2電極層5b之例為銅(Cu)層。第3電極層5c之例為鎳(Ni)層。第4電極層5d之例為金(Au)層。本實施形態之第1及第2電極層5a、5b作為障壁金屬層而發揮功能。
第2絕緣膜6形成於基板1之背面S2與基板1之貫通孔H之側面S3。第2絕緣膜6之例為氧化矽膜或氮化矽膜。
背面電極7形成於基板1之背面S2側。背面電極7介隔第2絕緣膜6而形成於基板1之背面S2側與基板1之貫通孔H內，且電性連接於配線部4。其結果，正面電極5與背面電極7電性連接，而形成TSV電極(貫通電極)。符號V表示於形成背面電極7時所形成之孔隙。
背面電極7依序包含第1電極層7a、第2電極層7b、第3電極層7c及第4電極層7d。第1電極層7a之例為鈦(Ti)層。第2電極層7b之例為銅(Cu)層。第3電極層7c之例為鎳(Ni)層。第4電極層7d之例為Sn-Cu(錫-銅)合金層。本實施形態之第1及第2電極層7a、7b作為障壁金屬層而發揮功能。本實施形態之第4電極層7d係用以將正面電極5與背面電極7接合之焊料層(鍍敷層)。
正面阻劑層8係以包圍正面電極5之方式形成於基板1之正面S1側，且與正面電極5隔開。正面阻劑層8具有包圍正面電極5之內周α之外周β。正面阻劑層8之例為用於抑制半導體晶片之積層損壞之酚系樹脂。正面阻劑層8與正面電極5同樣地，介隔層間絕緣膜3而形成於基板1之正面S1側。符號F1表示正面阻劑層8之上表面。符號T1表示正面阻劑層8之厚度。厚度T1例如為5μm。
於本實施形態中，將正面電極5之厚度T3設定為薄於正面阻劑層8之厚度T1。因此，正面電極5之上表面F3之高度低於正面阻劑層8之上表面F1之高度。
背面阻劑層9形成於基板1之背面S2側，且與背面電極7隔開。背面阻劑層9之例為具有接著功能及感光性之酚醛系樹脂。背面阻劑層9與背面電極7同樣地，介隔第2絕緣膜6而形成於基板1之背面S2側。符號F2表示背面阻劑層9之下表面。符號T2表示背面阻劑層9之厚度。
於本實施形態中，將正面阻劑層8自正面電極5附近去除，使正面阻劑層8與正面電極5隔開。符號K表示已去除正面阻劑層8之區域。因此，於本實施形態中，可使正面電極5之上表面F3之高度低於 正面阻劑層8之上表面F1之高度。藉此，亦能夠使背面阻劑層9之厚度T2變薄。由此，根據本實施形態，於將具有圖1之構造之半導體晶片彼此積層時，能夠一方面藉由正面阻劑層8抑制半導體晶片之積層損壞，一方面縮短半導體晶片間之距離。
圖2與圖3係表示第1實施形態之半導體晶片之連接方法之剖視圖。
圖2與圖3表示具有圖1之構造之半導體晶片C1~C3。其中，圖2表示連接前之半導體晶片C1~C3，圖3表示連接後之半導體晶片C1~C3。
於將半導體晶片C1、C2電性連接時，半導體晶片C2積層於半導體晶片C1上(圖3)。此時，以半導體晶片C2之背面電極7與半導體晶片C1之正面電極5相接，且半導體晶片C2之背面阻劑層9與半導體晶片C1之正面阻劑層8相接之方式，將半導體晶片C2積層於半導體晶片C1上。
繼而，藉由第4電極層7d(焊料層)將半導體晶片C2之背面電極7與半導體晶片C1之正面電極5接合。又，藉由背面阻劑層9之接著功能將半導體晶片C2之背面阻劑層9與半導體晶片C1之正面阻劑層8接著。如此，將半導體晶片C1、C2電性連接。於該情形時，半導體晶片C1為第1晶片之例，半導體晶片C2為第2晶片之例。
同樣地，於將半導體晶片C2、C3電性連接時，將半導體晶片C3積層於半導體晶片C2上(圖3)。於該情形時，半導體晶片C2為第1晶片之例，半導體晶片C3為第2晶片之例。
相鄰之半導體晶片間之距離取決於各晶片之正面阻劑層8與背面阻劑層9之合計厚度T1+T2。若各晶片之正面電極5之厚度T3變厚，則該合計厚度T1+T2必須隨之變厚。然而，根據本實施形態，由於可使各晶片之正面電極5之厚度T3變薄，故可使該合計厚度T1+T2變薄。藉此，能夠縮短相鄰之半導體晶片間之距離。
於本實施形態中，藉由將半導體晶片C1、C2電性連接且將半導體晶片C2、C3電性連接，而可製作具備半導體晶片C1~C3之半導體裝置(半導體模組)。再者，形成半導體模組之半導體晶片之個數亦可為3個以外之數量。根據本實施形態，藉由縮短相鄰之半導體晶片間之距離，能夠使半導體模組之封裝之厚度變薄，或使形成半導體模組之半導體晶片之個數增加。
再者，較理想為，各晶片之正面電極5係以凹部B變小且變淺之方式形成。原因在於，若凹部B大且深，則於接合後之正面電極5與背面電極7之間形成間隙之可能性提高。
圖4與圖5係表示第1實施形態之半導體裝置之背面S2側之構造之俯視圖。
圖4(a)表示圖1之半導體晶片之基板1之背面S2。符號L1表示半導體晶片之X方向之長度。長度L1例如為12mm。符號L2表示半導體晶片之Y方向之長度。長度L2例如為15mm。
圖4(b)係圖4(a)之區域R1之放大圖。圖4(b)表示形成於基板1之背面S2側之複數個背面電極7與複數個背面阻劑層9。
圖5(a)與圖5(b)係圖4(b)之區域R2、R3之放大圖。如圖5(a)與圖5(b)所示，本實施形態之各背面電極7與各背面阻劑層9具有圓形之平面形狀。各背面電極7之直徑例如為20μm。各背面阻劑層9之直徑例如為40~160μm。
圖6係表示第1實施形態之半導體裝置之正面S1側之構造之俯視圖。
圖6(a)表示圖1之半導體晶片之正面S1側之構造之一例。圖6(a)表示形成於基板1之正面S1側之複數個正面電極5、及包圍該等正面電極5之正面阻劑層8。該等正面電極5之外周α與正面阻劑層8之內周β具有圓形之平面形狀。
符號D1表示各正面電極5之外周α之直徑。符號D2表示正面阻劑層8之各內周β之直徑。於本實施形態中，將直徑D2設定為大於直徑D1，其結果，各正面電極5與正面阻劑層8隔開。直徑D1例如為20μm。直徑D2例如為25μm。直徑D為第1直徑之例，直徑D2為第2直徑之例。
圖6(b)表示圖1之半導體晶片之正面S1側之構造之另一例。如圖6(b)所示，正面阻劑層8之各內周β之平面形狀亦可為圓形以外之形狀。
圖6(c)表示圖1之半導體晶片之正面S1側之構造之另一例。於圖6(a)與圖6(b)中，正面阻劑層8之1個內周β僅包圍1個正面電極5。另一方面，於圖6(c)中，正面阻劑層8之1個內周β包圍複數個正面電極5。如此，1個內周β內之正面電極5之個數亦可為任意。
[第1實施形態之比較例之半導體裝置]
圖7係表示第1實施形態之比較例之半導體裝置之構造之剖視圖。
本比較例之正面電極5介隔正面阻劑層8而形成於配線部4上。因此，正面電極5之厚度T3厚於正面阻劑層8之厚度T1，正面電極5之上表面F3之高度高於正面阻劑層8之上表面F1之高度。由此，於本比較例中，背面阻劑層9之厚度T2亦必須變厚。
圖8與圖9係表示第1實施形態之比較例之半導體晶片之連接方法之剖視圖。
圖8與圖9表示具有圖7之構造之半導體晶片C1~C3。其中，圖8表示連接前之半導體晶片C1~C3，圖9表示連接後之半導體晶片C1~C3。
於將半導體晶片C1、C2電性連接時，將半導體晶片C2積層於半導體晶片C1上(圖9)。又，於將半導體晶片C2、C3電性連接時，將半導 體晶片C3積層於半導體晶片C2上(圖9)。
相鄰之半導體晶片間之距離取決於各晶片之正面阻劑層8與背面阻劑層9之合計厚度T1+T2。若各晶片之正面電極5之厚度T3變厚，則該合計厚度T1+T2必須隨之變厚。如上所述，由於本比較例中各晶片之正面電極5之厚度T3較厚，故不易使該合計厚度T1+T2變薄。由此，相鄰之半導體晶片間之距離會變長。
另一方面，根據本實施形態，由於可使各晶片之正面電極5之厚度T3變薄，故可使合計厚度T1+T2變薄。藉此，能夠縮短相鄰之半導體晶片間之距離。
[第1實施形態之半導體裝置之製造方法]
圖10~圖14係表示第1實施形態之半導體裝置之製造方法之剖視圖。
首先，於基板1之正面S1形成第1絕緣膜2、層間絕緣膜3及配線部4之後，於層間絕緣膜3形成到達配線部4之上表面之開口部E(圖10(a))。
繼而，於配線部4上形成正面電極5(圖10(b))。正面電極5例如係藉由在層間絕緣膜3及配線部4上依序形成第1~第4電極層5a~5d，並利用蝕刻對第1~第4電極層5a~5d進行加工而形成。此時，會於正面電極5之上表面F3形成凹部B。
繼而，於層間絕緣膜3及正面電極5上形成正面阻劑層8(圖11(a))。正面阻劑層8係以覆蓋正面電極5之上表面F3之方式形成。其結果，正面電極5之上表面F3之高度低於正面阻劑層8之上表面F1之高度。
繼而，藉由光微影法及蝕刻而去除正面電極5附近之正面阻劑層8(圖11(b))。其結果，正面阻劑層8被加工成包圍正面電極5且與正面電極5隔開之形狀。正面電極5之外周α或正面阻劑層8之內周β之俯視 形狀例如為圓形。
繼而，切削基板1之背面S2，而使基板1薄膜化(圖12(a))。
繼而，藉由光微影法及蝕刻而於基板1之背面S2形成貫通孔H(圖12(b))。基板1之背面S2之貫通孔H之直徑例如為10μm。基板1之正面S1之貫通孔H之直徑例如為8μm。
繼而，於基板1之背面S2、貫通孔H之側面S3及貫通孔H之底面形成第2絕緣膜6(圖13(a))。進而，藉由蝕刻而自貫通孔H之底面去除第2絕緣膜6(圖13(a))。進而，於基板1之背面S2、貫通孔H之側面S3及貫通孔H之底面，介隔第2絕緣膜6而依序形成第1及第2電極層7a、7b(圖13(a))。
繼而，藉由光微影法及蝕刻而於基板1之背面S2側形成阻劑層10(圖13(b))。
繼而，將阻劑層10用作遮罩，於基板1之背面S2及基板1之貫通孔H內形成第3電極層7c(圖14(a))。此時，會於第3電極層7c內形成孔隙V。進而，於去除阻劑層10之後，將第3電極層7c用作遮罩，藉由蝕刻對第1及第2電極層7a、7b進行加工(圖14(a))。
繼而，藉由光微影法及蝕刻而於基板1之背面S2側形成背面阻劑層9(圖14(b))。進而，於第3電極層7c之下表面形成第4電極層7d(圖14(b))。其結果，於基板1之背面S2側及基板1之貫通孔H內形成背面電極7。背面電極7係以電性連接於配線部4之方式形成。藉此，背面電極7經由配線部4而電性連接於正面電極5，從而形成包含正面電極5及背面電極7之TSV電極。
以此方式製造圖1之半導體晶片。之後，使用具有圖1之構造之複數個半導體晶片而製造圖3之半導體模組。
如上所述，本實施形態之正面阻劑層8係以包圍正面電極5且與正面電極5隔開之方式形成於基板1之正面S1側。由此，根據本實施形 態，於將具有圖1之構造之半導體晶片彼此積層之情形時，能夠縮短半導體晶片間之距離。
以上，對若干實施形態進行了說明，但該等實施形態僅作為示例而提出，並非意圖限定發明之範圍。本說明書中所說明之新穎之裝置及方法能夠以其他各種形態加以實施。又，可於不脫離發明之主旨之範圍內，對本說明書中所說明之裝置及方法之方式進行各種省略、置換、變更。意圖使隨附之申請專利範圍及與其均等之範圍包含發明之範圍或主旨中所包含之此種形態或變化例。
1‧‧‧基板
2‧‧‧第1絕緣膜
3‧‧‧層間絕緣膜
4‧‧‧配線部
5‧‧‧正面電極
5a‧‧‧第1電極層
5b‧‧‧第2電極層
5c‧‧‧第3電極層
5d‧‧‧第4電極層
6‧‧‧第2絕緣膜
7‧‧‧背面電極
7a‧‧‧第1電極層
7b‧‧‧第2電極層
7c‧‧‧第3電極層
7d‧‧‧第4電極層
8‧‧‧正面阻劑層
9‧‧‧背面阻劑層
B‧‧‧凹部
F1‧‧‧上表面
F2‧‧‧下表面
F3‧‧‧上表面
H‧‧‧貫通孔
K‧‧‧區域
S1‧‧‧正面
S2‧‧‧背面
S3‧‧‧側面
T1‧‧‧厚度
T2‧‧‧厚度
T3‧‧‧厚度
V‧‧‧孔隙
α‧‧‧外周
β‧‧‧內周

Claims (8)

  1. 一種半導體裝置，其具備：基板；第1電極，其設置於上述基板之上表面側；第2電極，其設置於上述基板之下表面側，且與上述第1電極電性連接；第1阻劑層，其以包圍上述第1電極之方式設置於上述基板之上述上表面側，且與上述第1電極隔開；及第2阻劑層，其設置於上述基板之上述下表面側。
  2. 如請求項1之半導體裝置，其中上述第1電極之上表面之高度低於上述第1阻劑層之上表面之高度。
  3. 如請求項1或2之半導體裝置，其中上述第1阻劑層具有包圍上述第1電極之外周之內周，上述第1電極之上述外周具有第1直徑，上述第1阻劑層之上述內周具有大於上述第1直徑之第2直徑。
  4. 如請求項1或2之半導體裝置，其中上述第2電極設置於上述基板之上述下表面側及上述基板內。
  5. 一種半導體裝置，其具備：第1晶片；及第2晶片，其設置於上述第1晶片上；且上述第1及第2晶片各自具備：基板；第1電極，其設置於上述基板之上表面側；第2電極，其設置於上述基板之下表面側，且與上述第1電極電性連接； 第1阻劑層，其以包圍上述第1電極之方式設置於上述基板之上述上表面側，且與上述第1電極隔開；及第2阻劑層，其設置於上述基板之上述下表面側；且上述第2晶片係以上述第2晶片之上述第2電極與上述第1晶片之上述第1電極相接之方式，設置於上述第1晶片上。
  6. 如請求項5之半導體裝置，其中上述第2晶片係以上述第2晶片之上述第2阻劑層與上述第1晶片之上述第1阻劑層相接之方式，設置於上述第1晶片上。
  7. 一種半導體裝置之製造方法，其包含：於基板之上表面側形成第1電極；於上述基板之上述上表面側，形成包圍上述第1電極且與上述第1電極隔開之第1阻劑層；於上述基板之下表面側形成與上述第1電極電性連接之第2電極；及於上述基板之上述下表面側形成第2阻劑層。
  8. 如請求項7之半導體裝置之製造方法，其進而包含在上述基板之上述下表面形成孔，上述第2電極形成於上述基板之上述下表面側及上述基板之上述孔內。
TW105103350A 2015-09-04 2016-02-02 半導體裝置及其製造方法 TWI587418B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015174753A JP2017050497A (ja) 2015-09-04 2015-09-04 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
TW201711113A TW201711113A (zh) 2017-03-16
TWI587418B true TWI587418B (zh) 2017-06-11

Family

ID=58189660

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105103350A TWI587418B (zh) 2015-09-04 2016-02-02 半導體裝置及其製造方法

Country Status (4)

Country Link
US (1) US9922957B2 (zh)
JP (1) JP2017050497A (zh)
CN (1) CN106505060A (zh)
TW (1) TWI587418B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6509635B2 (ja) * 2015-05-29 2019-05-08 東芝メモリ株式会社 半導体装置、及び、半導体装置の製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120276733A1 (en) * 2011-04-27 2012-11-01 Elpida Memory, Inc. Method for manufacturing semiconductor device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003078108A (ja) 2001-08-31 2003-03-14 Hitachi Chem Co Ltd 半導体パッケージ用基板、これを用いた半導体パッケージとその積層体、およびこれらの製造方法
JP2003234432A (ja) 2002-02-08 2003-08-22 Ibiden Co Ltd 半導体チップ実装回路基板および多層化回路基板
JP2005150299A (ja) * 2003-11-13 2005-06-09 Seiko Epson Corp 半導体チップ、半導体装置及び半導体装置の製造方法、回路基板及び電子機器
JP5114041B2 (ja) * 2006-01-13 2013-01-09 日本シイエムケイ株式会社 半導体素子内蔵プリント配線板及びその製造方法
JP2011054805A (ja) * 2009-09-02 2011-03-17 Toshiba Corp 半導体装置、及び半導体装置の製造方法
JP2011228419A (ja) 2010-04-19 2011-11-10 Renesas Electronics Corp 半導体集積回路装置および半導体集積回路装置の製造方法
JP2012069903A (ja) * 2010-08-27 2012-04-05 Elpida Memory Inc 半導体装置及びその製造方法
JP5802515B2 (ja) * 2011-10-19 2015-10-28 株式会社東芝 半導体装置及びその製造方法
KR101916225B1 (ko) * 2012-04-09 2018-11-07 삼성전자 주식회사 Ｔｓｖ를 구비한 반도체 칩 및 그 반도체 칩 제조방법
US9275967B2 (en) * 2014-01-06 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120276733A1 (en) * 2011-04-27 2012-11-01 Elpida Memory, Inc. Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JP2017050497A (ja) 2017-03-09
TW201711113A (zh) 2017-03-16
US20170069600A1 (en) 2017-03-09
CN106505060A (zh) 2017-03-15
US9922957B2 (en) 2018-03-20

Similar Documents

Publication Publication Date Title
JP4937842B2 (ja) 半導体装置およびその製造方法
JP6034095B2 (ja) 半導体装置およびその製造方法
CN106206505B (zh) 半导体装置以及半导体装置的制造方法
JP6437246B2 (ja) 半導体装置およびその製造方法
US9881851B2 (en) Semiconductor device and method for producing semiconductor device
JP6680705B2 (ja) 半導体装置及びその製造方法
JP6277693B2 (ja) 半導体装置
JPWO2012107971A1 (ja) 半導体装置
US8349736B2 (en) Semiconductor device manufacturing method and semiconductor device
JP6301763B2 (ja) 半導体装置、および半導体装置の製造方法
TWI544555B (zh) 半導體封裝結構及其製造方法
TWI587418B (zh) 半導體裝置及其製造方法
US10163775B2 (en) Electronic device
JP6263859B2 (ja) 貫通電極基板の製造方法、貫通電極基板、および半導体装置
JP2017212370A (ja) 多層配線構造、半導体装置及びファンアウトタイプウエハーレベルパッケージ
JP6435562B2 (ja) 半導体装置および半導体装置の製造方法
JP2014132691A (ja) 半導体装置及びその製造方法
JP5891211B2 (ja) 半導体装置
JP6159125B2 (ja) 半導体装置および半導体装置の製造方法
JP2009130312A (ja) 半導体装置
JP2019083353A (ja) 半導体装置および半導体装置の製造方法
JP6074984B2 (ja) 半導体装置
JP2014222742A (ja) 半導体装置
JP2012134526A (ja) 半導体装置
JP2011119460A (ja) 半導体装置およびその製造方法