CN106206505B - 半导体装置以及半导体装置的制造方法 - Google Patents

半导体装置以及半导体装置的制造方法 Download PDF

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CN106206505B
CN106206505B CN201510854664.9A CN201510854664A CN106206505B CN 106206505 B CN106206505 B CN 106206505B CN 201510854664 A CN201510854664 A CN 201510854664A CN 106206505 B CN106206505 B CN 106206505B
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substrate
electrode
nickel electrode
wiring
semiconductor device
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CN106206505A (zh
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小木曾浩二
村上和博
右田达夫
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Kioxia Corp
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Toshiba Memory Corp
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Abstract

本发明的实施方式提供一种能够谋求厚度方向上的小型化的半导体装置以及半导体装置的制造方法。实施方式的半导体装置具备第1基板、铝垫、第1镍电极、第2基板、第2镍电极以及连接层。第1基板的内部具有配线。铝垫设置在第1基板的表层内，并与配线连接。第1镍电极是一部分埋设在第1基板中并与铝垫连接，并且顶面从第1基板的表面突出。第2基板积层于第1基板。第2镍电极是一部分埋设在第2基板中，并且顶面从第2基板的第1基板侧的表面突出。连接层由含锡的合金形成，将第1镍电极及第2镍电极之间连接。

Description

半导体装置以及半导体装置的制造方法
相关申请案
本申请案享有以日本专利申请2015-110601号(申请日：2015年5月29日)为基础申请案的优先权。本申请案通过参照该基础申请案而包含基础申请案的全部内容。
技术领域
本实施方式涉及一种半导体装置以及半导体装置的制造方法。
背景技术
以往有通过将设有半导体元件或集成电路的基板彼此积层连接而减少安装面积的半导体装置。此种半导体装置与将多个基板平置安装的情况相比能够实现长度方向及宽度方向上的小型化，但有关厚度方向上的小型化，尚有改善的余地。
发明内容
本发明的实施方式提供一种能够谋求厚度方向上的小型化的半导体装置以及半导体装置的制造方法。
实施方式的半导体装置具备第1基板、铝垫、第1镍电极、第2基板、第2镍电极以及连接层。第1基板的内部具有配线。铝垫设置在所述第1基板的表层内，并与所述配线连接。第1镍电极是一部分埋设在所述第1基板中并与所述铝垫连接，并且顶面从所述第1基板的表面突出。第2基板积层于所述第1基板。第2镍电极是一部分埋设在所述第2基板中，并且顶面从所述第2基板的所述第1基板侧的表面突出。连接层由含锡的合金形成，将所述第1镍电极及所述第2镍电极之间连接。
附图说明
图1是表示实施方式的半导体装置的示意性的截面的说明图。
图2(a)～(c)是表示实施方式的半导体装置的制造步骤的说明图。
图3(a)～(c)是表示实施方式的半导体装置的制造步骤的说明图。
图4(a)～(c)是表示实施方式的半导体装置的制造步骤的说明图。
图5是表示实施方式的半导体装置的制造步骤的说明图。
图6(a)及(b)是表示实施方式的半导体装置的制造步骤的说明图。
图7是表示实施方式的半导体装置的制造步骤的说明图。
具体实施方式
以下，参照附图，详细地说明实施方式的半导体装置以及半导体装置的制造方法。另外，本发明并不受该实施方式限定。图1是表示实施方式的半导体装置1的示意性的截面的说明图。
如图1所示，实施方式的半导体装置1具有如下构造：通过将设有半导体元件或集成电路的第1基板10与第2基板11积层连接，而能够减少安装面积。
此处，将基板积层而制造的通常的半导体装置中，在各基板的相对向一侧的表面上设置例如使用铜形成的柱(pillar)状的电极(以下记为“柱形电极”)，对向的柱形电极彼此使用焊料连接。
但是，如果直接使用焊料将铜制的柱形电极彼此连接，那么焊料会向柱形电极内扩散，而导致连接特性变差。因此，通常在柱形电极与焊料之间设置防止焊料扩散的障壁层。
然而，在此种构成中，由于在基板间依次积层柱形电极、障壁层、焊料层、障壁层以及柱形电极，因此被积层的基板的间隔变宽，而导致半导体装置的厚度增加。因此，半导体装置1具备使用能够抑制焊料扩散的Ni(镍)形成的柱形电极以代替铜制的柱形电极，由此能够实现厚度方向上的小型化。
具体来说，半导体装置1的第1基板10具备半导体层8、设置在半导体层8的下表面的保护膜80、依次积层在半导体层8上的第1绝缘层30、第2绝缘层4以及钝化膜5。
保护膜80例如使用SiN(氮化硅)形成。半导体层8例如使用Si(硅)形成，且在内部设置贯通半导体层8的正面及背面的贯通电极81。贯通电极81例如使用Cu(铜)或Ni(镍)形成。
而且，在贯通电极81与半导体层8的界面设置防止金属(例如Cu)从贯通电极81向半导体层8扩散的障壁金属膜82。障壁金属膜82例如使用Ti(钛)形成。另外，此处虽未图示，但在半导体层8的内部设置半导体元件或集成电路等。而且，此处虽未图示，但在保护膜80与半导体层8之间、以及障壁金属膜82与半导体层8之间设置例如使用SiO2(氧化硅)的绝缘膜。
第1绝缘层30例如使用SiO2形成，且在内部设置多层配线3。多层配线3包含与贯通电极81的上表面连接的第1配线31、与第1配线31的上表面连接的第2配线32以及与第2配线32的上表面连接的第3配线33。
第1配线31例如使用W(钨)形成。第2配线32及第3配线33例如使用Cu形成。该第2配线32及第3配线33被障壁金属膜34覆盖。障壁金属膜34例如使用Ti形成。
第2绝缘层4例如使用SiO2形成，且在内部设置与第3配线33的上表面连接的铝垫40。铝垫40被障壁金属膜41覆盖。障壁金属膜41例如使用Ti形成。钝化膜5例如使用SiN或聚酰亚胺形成。
在该第1基板10的上表面设置使用Ni(镍)形成的柱状的第1Ni电极6，该第1Ni电极6是一部分埋设在钝化膜5中并与铝垫40连接，且顶面从钝化膜5的表面突出。
在第1Ni电极6与钝化膜5的界面设置障壁金属膜60。障壁金属膜60例如使用Ti形成。而且，第1Ni电极6在与障壁金属膜60接触的部分具备含Cu的Cu扩散区域61。Cu扩散区域61是通过将在形成第1Ni电极6的步骤中被用作籽晶的Cu向第1Ni电极6扩散而形成。
而且，在第1基板10的下表面侧设置使用Ni(镍)形成的柱状的第2Ni电极9。具体来说，第2Ni电极9为如下形状：一部分埋设在保护膜80中，并且顶面从保护膜80的表面(此处为下表面)突出。
在该第2Ni电极9与保护膜80的界面设置障壁金属膜90。障壁金属膜90例如使用Ti形成。而且，第2Ni电极9在与障壁金属膜90接触的部分具备含Cu的Cu扩散区域91。Cu扩散区域91是通过将在形成第2Ni电极9的步骤被用作籽晶的Cu向第2Ni电极9扩散而形成。
而且，在第2Ni电极9的顶面(此处为下表面)设置由含Sn(锡)的合金形成的连接层7。该连接层7例如使用焊料而形成。而且，连接层7在与第2Ni电极9接触的部分具备含Au(金)的Au扩散区域71。
Au扩散区域71是通过在制造步骤的途中将形成在第2Ni电极9的顶面的下述Au膜104(参照图4(c))的Au向连接层7扩散而形成。在将第1基板10积层于未图示的其他基板的情况下，该连接层7与其他基板表面上的连接端子连接。而且，在相邻设置的第2Ni电极9之间设置支撑部72。支撑部72例如使用具感光性的粘接性树脂形成。
另一方面，第2基板11的上表面以及背面侧的连接部的构成与第1基板10相同。此处，形成在第2基板11内部的半导体元件及集成电路的构成与第1基板10可相同，也可不同。因此，图1中，选择性地图示第2基板11中从半导体层8起下侧的部分。
半导体装置1中，该第2基板11积层于第1基板10上。由此，半导体装置1成为如下构造：在第1基板10的第1Ni电极6的正上方积层第2基板11的连接层7，在连接层7的正上方积层第2基板11的第2Ni电极9，在第2基板11的第2Ni电极9上积层第2基板11。
而且，在半导体装置1中，第2基板11的支撑部72的一个端面(此处为上表面)抵接于第2基板11的保护膜80的下表面，另一端面(此处为下表面)抵接于第1基板10的钝化膜5的上表面。
如上所述，半导体装置1具备设置多层配线3的第1基板10、设置在第1基板10的表层内并与多层配线3连接的铝垫40、以及一部分埋设在第1基板10中并与铝垫40连接的第1Ni电极6。第1Ni电极6的顶面从第1基板10的表面突出。
进而，半导体装置1具备积层于第1基板10的第2基板11、一部分埋设在第2基板11中且顶面从第2基板11的第1基板10侧表面突出的第2Ni电极9、以及将第1Ni电极6及第2Ni电极9之间连接的焊料的连接层7。
这样一来，在半导体装置1中，第1基板10与第2基板11是通过第1Ni电极6、焊料的连接层7以及第2Ni电极9这三种构成要素的积层体而连接。因此，与将具备普通的Cu的柱形电极的基板积层的基板间是通过柱形电极、障壁层、焊料层、障壁层以及柱形电极这五种构成要素的积层体而连接的半导体装置相比，半导体装置1能够实现厚度方向上的小型化。
半导体装置1的第1Ni电极6在与障壁金属膜60接触的部分具备含Cu的Cu扩散区域61。该第1Ni电极6能够使用普通的Cu作为籽晶而形成。因此，根据本实施方式，可以在不大幅度变更现有的通常的制造步骤的情况下，制造能够实现厚度方向上的小型化的半导体装置1。
而且，半导体装置1的连接层7在与第1Ni电极6接触的部位以及与第2Ni电极9接触的部分具备含Au的Au扩散区域71。由此，半导体装置1能够降低连接层7与第1Ni电极6及第2Ni电极9之间的连接电阻。
而且，半导体装置1具备支撑部72，该支撑部72的一个端面抵接于第1基板10的表面，另一端面抵接于第2基板11的第1基板10侧的表面，并且使用树脂形成。在将第2基板11积层于第1基板10的情况下，该支撑部72能够防止第1基板10与第2基板11的间隔过度变窄。
因此，根据半导体装置1，能够防止在对第1基板10积层第2基板11时，连接层7的焊料被过度挤压而下垂，附着于第1基板10的钝化膜5而产生电流泄漏。
另外，如果在第1Ni电极6顶面距钝化膜5表面的高度为1μm～10μm、支撑部72的高度(厚度)为17μm～25μm的情况下，支撑部72的占有面积为第1基板10表面的面积的10％～50％，那么能够防止焊料下垂。
接下来，参照图2～图7，对实施方式的半导体装置1的制造方法进行说明。图2～图7是表示实施方式的半导体装置1的制造步骤的说明图。以下，通过对图2～图7所示的构成要素中与图1所示的构成要素相同的构成要素标注与图1所示的符号相同的符号，而省略该相同部分的详细说明。
而且，第1基板10制造步骤与第2基板11的制造步骤除了在形成于半导体层8的半导体元件及集成电路的形成步骤的方面不同以外，为相同的步骤。因此，此处对第1基板10的制造步骤进行说明，省略有关第2基板11的制造步骤的说明。
而且，第1基板10的制造步骤中，在半导体层8上形成第1绝缘层30及多层配线3的步骤与通常的半导体装置的制造步骤相同，因此，此处省略该步骤的说明。
在制造半导体装置1的情况下，准备如图2(a)所示那样在半导体层8上形成着第1绝缘层30及多层配线3的第1基板10。之后，如图2(b)所示，例如通过利用CVD(ChemicalVapor Deposition，化学气相沉积)在第1绝缘层30上积层SiO2而形成第2绝缘层4。
接着，例如利用RIE(Reactive Ion Etching，反应离子蚀刻法)从第2绝缘层4选择性地去除形成铝垫40的部分的SiO2，之后使用Ti覆盖第2绝缘层4的表面，由此形成障壁金属膜41。
之后，例如通过溅镀在第2绝缘层4上积层Al(铝)后，例如利用RIE将铝图案化。这样一来，如图2(b)所示，在第2绝缘层4上形成铝垫40。
接着，如图2(c)所示，通过在形成着铝垫40的第2绝缘层4上积层SiN或聚酰亚胺，而形成钝化膜5。另外，也可以为钝化膜5与铝垫40之间隔着SiO2而形成。
之后，如图3(a)所示，在钝化膜5上涂布光阻剂100，利用光刻法选择性地去除第1Ni电极6(参照图1)的形成位置上的光阻剂100。
然后，通过进行将剩余的光阻剂100作为掩模的蚀刻，而在钝化膜5的第1Ni电极6的形成位置形成从钝化膜5的表面到达至被障壁金属膜41覆盖的铝垫40的表面为止的开口101。
接着，如图3(b)所示，在去除光阻剂100后，使用Ti覆盖钝化膜5的上表面、开口101的内周面及底面，由此形成障壁金属膜60。进而，通过使用Cu覆盖障壁金属膜60的表面而形成籽晶膜61a。
接着，如图3(c)所示，在籽晶膜61a的表面涂布光阻剂102之后，选择性地去除第1Ni电极6(图1参照)的形成位置上的光阻剂102，由此使被籽晶膜61a覆盖的开口101露出。
之后，如图4(a)所示，通过在去除光阻剂102而露出的部分的籽晶膜61a上积层Ni，而形成第1Ni电极6。Ni的积层是通过使用籽晶膜61a作为电极膜的电解电镀而进行。另外，在第1Ni电极6与籽晶膜61a接触的部分，之后会有Ni从第1Ni电极6向籽晶膜61a扩散、Cu从籽晶膜61a向第1Ni电极6扩散的情况。
由此，已与第1Ni电极6接触部分的籽晶膜61a成为Cu与Ni的合金而成为第1Ni电极6的一部分，在第1Ni电极6的与障壁金属膜60接触的部分形成Cu扩散区域61。
结果在障壁金属膜60与第1Ni电极6之间不存在完全为Cu的区域。这样一来形成第1Ni电极6，该第1Ni电极6的一部分埋设在形成着障壁金属膜60的开口101中并与铝垫40连接，并且顶面从钝化膜5的表面突出。
之后，在第1Ni电极6的上表面形成Au膜103后，如图4(b)所示，去除光阻剂102。然后，通过进行将上表面形成着Au膜103的第1Ni电极6用作掩模的RIE，而从钝化膜5的上表面去除无用部分的籽晶膜61a及障壁金属膜60。
接着，在半导体层8的内部形成贯通电极81。此处，例如在半导体层8的下表面形成保护膜80，并形成从半导体层8的下表面到达至第1配线31的下表面为止的TSV(ThroughSilicon Via，硅穿孔)，利用障壁金属膜82覆盖TSV的内周面之后，在TSV的内部埋入Cu，由此形成贯通电极81。
之后，如图4(c)所示，对保护膜80进行与已参照图3及图4进行说明的步骤相同的步骤，并形成障壁金属膜90、以及形成在与障壁金属膜90接触的部分具备Cu扩散区域91的第2Ni电极9。
由此，形成柱状的第2Ni电极9，该第2Ni电极9是一部分埋设在保护膜80中，并且顶面从保护膜80的表面(此处为下表面)突出。然后，在第2Ni电极9的顶面(此处为下表面)形成Au膜104。
接着，如图5所示，在第1基板10的下表面涂布具有感光性的粘接性树脂105。之后，进行曝光，通过显影去除被照射光的部分的粘接性树脂105。由此，形成图6(a)所示的支撑部72。然后，通过在Au膜104的下表面形成焊料层，而如图6(b)所示那样形成连接层7。
另外，在连接层7与Au膜104接触的部分，之后会有焊料从连接层7向Au膜104扩散、Au从Au膜104向连接层7扩散的情况。由此，与连接层7接触部分的Au膜104成为Au与焊料的合金而成为连接层7的一部分，在连接层7的与第2Ni电极9接触的部分形成Au扩散区域71，从而完成第1基板10。
最后，如图7所示，在已完成的第1基板10上配置已完成的第2基板11，并进行第1基板10的第1Ni电极6与所对应的第2基板11的连接层7的定位，之后在第1基板10上积层第2基板11。由此，完成图1所示的半导体装置1。
如上所述，实施方式的半导体装置中，第1基板与第2基板是通过第1基板侧的第1Ni电极、焊料的连接层以及第2基板侧的第2Ni电极这三种构成要素的积层体而连接。
由此，与被积层的基板间是通过柱形电极、障壁层、焊料层、障壁层以及柱形电极这五种构成要素的积层体而连接的通常的半导体装置相比，实施方式的半导体装置能够实现厚度方向上的小型化。
已对本发明的若干实施方式进行了说明，但这些实施方式是作为示例而提出的，并非意图限定发明的范围。这些新颖的实施方式能以其他各种方式实施，且能够在不脱离发明主旨的范围内进行各种省略、置换、变更。这些实施方式及其变化包含在发明的范围或主旨内，并且包含在权利要求书所记载的发明及其均等的范围内。
[符号的说明]
1 半导体装置
3 多层配线
4 第2绝缘层
5 钝化膜
6 第1Ni电极
7 连接层
8 半导体层
9 第2Ni电极
10 第1基板
11 第2基板
30 第1绝缘层
31 第1配线
32 第2配线
33 第3配线
34 障壁金属膜
40 铝垫
41 障壁金属膜
60 障壁金属膜
61 Cu扩散区域
61a 籽晶膜
71 Au扩散区域
72 支撑部
80 保护膜
81 贯通电极
82 障壁金属膜
90 障壁金属膜
91 Cu扩散区域
100 光阻剂
101 开口
102 光阻剂
103 Au膜
104 Au膜
105 粘接性树脂

Claims (6)

1.一种半导体装置，其特征在于具备：
第1基板，具备第1半导体层，且内部具有使用铜和钨的配线；
第1贯通电极，一端与所述配线连接，且贯通所述第1半导体层；
铝垫，设置在所述第1基板的表层内，与所述配线连接；
钝化膜，设置在所述第1基板的所述表层侧，具有使所述铝垫的一部分露出的开口；
第1障壁金属膜，覆盖所述钝化膜的上表面、所述开口的内周面及底面；
第1镍电极，一部分埋设在所述钝化膜的开口内、并经由所述第1障壁金属膜与所述铝垫连接，顶面从所述第1基板的表面突出；
第2基板，具备第2半导体层，并积层在所述第1基板上；
第2贯通电极，贯通所述第2半导体层并到达所述第1基板侧的表面；
氮化硅膜，设置在所述第1基板侧的所述第2半导体层的表面，具有使所述第2贯通电极的一端露出的开口；
第2镍电极，一部分埋设在所述氮化硅膜的开口内，并且顶面从所述第2基板的所述第1基板侧的表面突出；以及
连接层，由含锡的合金形成，在与所述第1基板的所述第1镍电极接触的部位以及与所述第2基板的所述第2镍电极接触的部分具备含Au的Au扩散区域，将所述第1镍电极与所述第2镍电极之间直接地连接；并且
所述第1镍电极设置在所述铝垫的正上方；
所述第1贯通电极经由所述配线与所述铝垫电连接；
所述第2贯通电极与所述第2镍电极连接。
2.根据权利要求1所述的半导体装置，其特征在于：
所述第1障壁金属膜由钛形成，并且
所述第1镍电极是：
与所述第1障壁金属膜接触的部位包含铜；
还具备第2障壁金属膜，所述第2障壁金属膜由钛形成，设置在所述第2镍电极与所述氮化硅膜及所述第2贯通电极的界面；
所述第2镍电极是：
与所述第2障壁金属膜接触的部位包含铜；
还具备第3障壁金属膜，所述第3障壁金属膜由钛形成，分别设置在所述第1半导体层与所述第1贯通电极的界面、以及所述第2半导体层与所述第2贯通电极的界面；
还具备绝缘膜，分别设置在所述第1半导体层与所述第3障壁金属膜的境界、以及所述第2半导体层与所述第3障壁金属膜的境界。
3.根据权利要求1或2所述的半导体装置，其特征在于：
所述配线包含使用钨的钨配线与使用铜的铜配线，所述第1贯通电极经由所述钨配线与所述铜配线电连接，所述钨配线经由所述铜配线与所述铝垫电连接。
4.根据权利要求1或2所述的半导体装置，其特征在于：
具备支撑部，该支撑部由树脂形成，一个端面抵接于所述第1基板的表面，另一端面抵接于所述第2基板的所述第1基板侧的表面。
5.一种半导体装置的制造方法，其特征在于包含如下步骤：
在具备第1半导体层、且内部具有配线的第1基板的表层内形成与所述配线连接的铝垫；
在所述第1基板的所述表层侧，形成覆盖所述铝垫的表面的钝化膜；
形成从所述钝化膜的表面到达至所述铝垫的表面为止的开口；
在所述开口的内周面及底面，由钛形成障壁金属膜；
形成第1镍电极，该第1镍电极的一部分埋设在形成着所述障壁金属膜的所述开口内并与所述铝垫连接，并且顶面从所述第1基板的表面突出；
在所述第1镍电极的上表面形成第1Au膜；
形成第1贯通电极，所述第1贯通电极的一端与所述配线连接，且贯通所述第1半导体层；
形成覆盖具备第2半导体层的第2基板的所述第1基板侧的所述第2半导体层的表面的氮化硅膜；
在所述氮化硅膜的表面形成开口；
形成第2贯通电极，所述第2贯通电极贯通所述第2半导体层并到达所述第1基板侧的表面；
形成第2镍电极，该第2镍电极的一部分埋设在所述氮化硅膜的开口内，并且顶面从所述第2基板的表面突出；
在所述第2镍电极的顶面形成第2Au膜，在所述第2Au膜的下表面利用含锡的合金形成连接层，在所述连接层的与所述第2镍电极接触的部分形成第1Au扩散区域；以及
在所述第1基板上积层所述第2基板，在所述连接层的与所述第1镍电极接触的部位形成第2Au扩散区域，使所述第1镍电极与所述第2镍电极经由所述连接层直接地连接。
6.根据权利要求5所述的半导体装置的制造方法，其特征在于还包含如下步骤：
形成支撑部，该支撑部由树脂形成，一个端面抵接于所述第2基板的所述第1基板侧的表面；且
使所述第1镍电极与所述第2镍电极经由所述连接层直接连接的步骤包含将所述支撑部的另一端面抵接于所述第1基板的表面。
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