TWI621220B - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

Info

Publication number
TWI621220B
TWI621220B TW104138995A TW104138995A TWI621220B TW I621220 B TWI621220 B TW I621220B TW 104138995 A TW104138995 A TW 104138995A TW 104138995 A TW104138995 A TW 104138995A TW I621220 B TWI621220 B TW I621220B
Authority
TW
Taiwan
Prior art keywords
substrate
nickel electrode
electrode
semiconductor device
layer
Prior art date
Application number
TW104138995A
Other languages
English (en)
Other versions
TW201642398A (zh
Inventor
Koji Ogiso
Kazuhiro Murakami
Tatsuo Migita
Original Assignee
Toshiba Memory Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Memory Corp filed Critical Toshiba Memory Corp
Publication of TW201642398A publication Critical patent/TW201642398A/zh
Application granted granted Critical
Publication of TWI621220B publication Critical patent/TWI621220B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03614—Physical or chemical etching by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10135—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H01L2224/16058—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81139—Guiding structures on the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本發明之實施形態提供一種能夠謀求厚度方向上之小型化之半導體裝置及半導體裝置之製造方法。
實施形態之半導體裝置具備第1基板、鋁墊、第1鎳電極、第2基板、第2鎳電極及連接層。第1基板係於內部具有配線。鋁墊設置於第1基板之表層內，並與配線連接。第1鎳電極係一部分埋設於第1基板中並與鋁墊連接，並且頂面自第1基板之表面突出。第2基板積層於第1基板。第2鎳電極係一部分埋設於第2基板中，並且頂面自第2基板之第1基板側之表面突出。連接層由含錫之合金形成，且將第1鎳電極及第2鎳電極之間連接。

Description

半導體裝置及半導體裝置之製造方法 [相關申請案]
本申請案享有以日本專利申請2015-110601號(申請日：2015年5月29日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
本實施形態係關於一種半導體裝置及半導體裝置之製造方法。
先前有藉由將設有半導體元件或積體電路之基板彼此積層連接而減少安裝面積之半導體裝置。此種半導體裝置與將複數個基板平置安裝之情形相比能夠實現長度方向及寬度方向上之小型化，但有關厚度方向上之小型化，尚有改善之餘地。
本發明之實施形態提供一種能夠謀求厚度方向上之小型化之半導體裝置及半導體裝置之製造方法。
實施形態之半導體裝置具備第1基板、鋁墊、第1鎳電極、第2基板、第2鎳電極及連接層。第1基板係於內部具有配線。鋁墊設置於上述第1基板之表層內，並與上述配線連接。第1鎳電極係一部分埋設於上述第1基板中並與上述鋁墊連接，並且頂面自上述第1基板之表面突出。第2基板積層於上述第1基板。第2鎳電極係一部分埋設於上述第2基板中，並且頂面自上述第2基板之上述第1基板側之表面突出。連接層由含錫之合金形成，且將上述第1鎳電極及上述第2鎳電極之間連 接。
1‧‧‧半導體裝置
3‧‧‧多層配線
4‧‧‧第2絕緣層
5‧‧‧鈍化膜
6‧‧‧第1Ni電極
7‧‧‧連接層
8‧‧‧半導體層
9‧‧‧第2Ni電極
10‧‧‧第1基板
11‧‧‧第2基板
30‧‧‧第1絕緣層
31‧‧‧第1配線
32‧‧‧第2配線
33‧‧‧第3配線
34‧‧‧障壁金屬膜
40‧‧‧鋁墊
41‧‧‧障壁金屬膜
60‧‧‧障壁金屬膜
61‧‧‧Cu擴散區域
61a‧‧‧籽晶膜
71‧‧‧Au擴散區域
72‧‧‧支持部
80‧‧‧保護膜
81‧‧‧貫通電極
82‧‧‧障壁金屬膜
90‧‧‧障壁金屬膜
91‧‧‧Cu擴散區域
100‧‧‧阻劑
101‧‧‧開口
102‧‧‧阻劑
103‧‧‧Au膜
104‧‧‧Au膜
105‧‧‧接著性樹脂
圖1係表示實施形態之半導體裝置之模式性之剖面之說明圖。
圖2(a)~(c)係表示實施形態之半導體裝置之製造步驟之說明圖。
圖3(a)~(c)係表示實施形態之半導體裝置之製造步驟之說明圖。
圖4(a)~(c)係表示實施形態之半導體裝置之製造步驟之說明圖。
圖5係表示實施形態之半導體裝置之製造步驟之說明圖。
圖6(a)及(b)係表示實施形態之半導體裝置之製造步驟之說明圖。
圖7係表示實施形態之半導體裝置之製造步驟之說明圖。
以下，參照隨附圖式，詳細地說明實施形態之半導體裝置及半導體裝置之製造方法。再者，本發明並不受該實施形態限定。圖1係表示實施形態之半導體裝置1之模式性之剖面之說明圖。
如圖1所示，實施形態之半導體裝置1具有如下構造：藉由將設有半導體元件或積體電路之第1基板10與第2基板11積層連接，而能夠減少安裝面積。
此處，將基板積層而製造之通常之半導體裝置中，於各基板之相對向一側之表面上設置例如使用銅形成之柱(pillar)狀之電極(以下記為「柱形電極」)，對向之柱形電極彼此使用焊料連接。
但是，若直接使用焊料將銅製之柱形電極彼此連接，則焊料會向柱形電極內擴散，而導致連接特性變差。因此，通常於柱形電極與焊料之間設置防止焊料擴散之障壁層。
然而，於該構成中，由於在基板間依次積層柱形電極、障壁層、焊料層、障壁層及柱形電極，因此被積層之基板之間隔變寬，而導致半導體裝置之厚度增加。因此，半導體裝置1具備使用能夠抑制焊料擴散之Ni(鎳)形成之柱形電極以代替銅製之柱形電極，由此能夠 實現厚度方向上之小型化。
具體而言，半導體裝置1之第1基板10具備半導體層8、設置於半導體層8之下表面之保護膜80、依次積層於半導體層8上之第1絕緣層30、第2絕緣層4及鈍化膜5。
保護膜80例如使用SiN(氮化矽)形成。半導體層8例如使用Si(矽)形成，且於內部設置貫通半導體層8之正面及背面之貫通電極81。貫通電極81例如使用Cu(銅)或Ni(鎳)形成。
又，於貫通電極81與半導體層8之界面設置防止金屬(例如Cu)自貫通電極81向半導體層8擴散之障壁金屬膜82。障壁金屬膜82例如使用Ti(鈦)形成。再者，此處雖未圖示，但於半導體層8之內部設置半導體元件或積體電路等。又，此處雖未圖示，但於保護膜80與半導體層8之間、及障壁金屬膜82與半導體層8之間設置例如使用SiO2(氧化矽)之絕緣膜。
第1絕緣層30例如使用SiO2形成，且於內部設置多層配線3。多層配線3包含與貫通電極81之上表面連接之第1配線31、與第1配線31之上表面連接之第2配線32及與第2配線32之上表面連接之第3配線33。
第1配線31例如使用W(鎢)形成。第2配線32及第3配線33例如使用Cu形成。該第2配線32及第3配線33被障壁金屬膜34被覆。障壁金屬膜34例如使用Ti形成。
第2絕緣層4例如使用SiO2形成，且於內部設置與第3配線33之上表面連接之鋁墊40。鋁墊40被障壁金屬膜41被覆。障壁金屬膜41例如使用Ti形成。鈍化膜5例如使用SiN或聚醯亞胺形成。
於該第1基板10之上表面設置使用Ni(鎳)形成之柱狀之第1Ni電極6，該第1Ni電極6係一部分埋設於鈍化膜5中並與鋁墊40連接，且頂面自鈍化膜5之表面突出。
於第1Ni電極6與鈍化膜5之界面設置障壁金屬膜60。障壁金屬膜 60例如使用Ti形成。又，第1Ni電極6於與障壁金屬膜60接觸之部分具備含Cu之Cu擴散區域61。Cu擴散區域61係藉由將於形成第1Ni電極6之步驟中被用作籽晶之Cu向第1Ni電極6擴散而形成。
又，於第1基板10之下表面側設置使用Ni(鎳)形成之柱狀之第2Ni電極9。具體而言，第2Ni電極9為如下形狀：一部分埋設於保護膜80中，並且頂面自保護膜80之表面(此處為下表面)突出。
於該第2Ni電極9與保護膜80之界面設置障壁金屬膜90。障壁金屬膜90例如使用Ti形成。又，第2Ni電極9於與障壁金屬膜90接觸之部分具備含Cu之Cu擴散區域91。Cu擴散區域91係藉由將於形成第2Ni電極9之步驟被用作籽晶之Cu向第2Ni電極9擴散而形成。
又，於第2Ni電極9之頂面(此處為下表面)設置由含Sn(錫)之合金形成之連接層7。該連接層7例如使用焊料而形成。又，連接層7於與第2Ni電極9接觸之部分具備含Au(金)之Au擴散區域71。
Au擴散區域71係藉由在製造步驟之途中將形成於第2Ni電極9之頂面之下述Au膜104(參照圖4(c))之Au向連接層7擴散而形成。於將第1基板10積層於未圖示之其他基板之情形時，該連接層7與其他基板表面上之連接端子連接。又，於相鄰設置之第2Ni電極9之間設置支持部72。支持部72例如使用具感光性之接著性樹脂形成。
另一方面，第2基板11之上表面及背面側之連接部之構成與第1基板10相同。此處，形成於第2基板11內部之半導體元件及積體電路之構成與第1基板10可相同，亦可不同。因此，圖1中，選擇性地圖示第2基板11中自半導體層8起下側之部分。
半導體裝置1中，該第2基板11積層於第1基板10上。藉此，半導體裝置1成為如下構造：於第1基板10之第1Ni電極6之正上方積層第2基板11之連接層7，於連接層7之正上方積層第2基板11之第2Ni電極9，於第2基板11之第2Ni電極9上積層第2基板11。
又，於半導體裝置1中，第2基板11之支持部72之一端面(此處為上表面)抵接於第2基板11之保護膜80之下表面，另一端面(此處為下表面)抵接於第1基板10之鈍化膜5之上表面。
如上所述，半導體裝置1具備設置多層配線3之第1基板10、設置於第1基板10之表層內並與多層配線3連接之鋁墊40、及一部分埋設於第1基板10中並與鋁墊40連接之第1Ni電極6。第1Ni電極6之頂面自第1基板10之表面突出。
進而，半導體裝置1具備積層於第1基板10之第2基板11、一部分埋設於第2基板11中且頂面自第2基板11之第1基板10側表面突出之第2Ni電極9、及將第1Ni電極6及第2Ni電極9之間連接之焊料之連接層7。
如此，於半導體裝置1中，第1基板10與第2基板11係藉由第1Ni電極6、焊料之連接層7及第2Ni電極9之3種構成要素之積層體而連接。 因此，與將具備普通之Cu之柱形電極之基板積層之基板間係藉由柱形電極、障壁層、焊料層、障壁層及柱形電極之5種構成要素之積層體而連接之半導體裝置相比，半導體裝置1能夠實現厚度方向上之小型化。
半導體裝置1之第1Ni電極6於與障壁金屬膜60接觸之部分具備含Cu之Cu擴散區域61。該第1Ni電極6能夠使用普通之Cu作為籽晶而形成。因此，根據本實施形態，可於不大幅度變更現有之通常之製造步驟之情況下，製造能夠實現厚度方向上之小型化之半導體裝置1。
又，半導體裝置1之連接層7於與第1Ni電極6接觸之部位及與第2Ni電極9接觸之部分具備含Au之Au擴散區域71。藉此，半導體裝置1能夠降低連接層7與第1Ni電極6及第2Ni電極9之間之連接電阻。
又，半導體裝置1具備支持部72，該支持部72之一端面抵接於第1基板10之表面，另一端面抵接於第2基板11之第1基板10側之表面， 並且使用樹脂形成。於將第2基板11積層於第1基板10之情形時，該支持部72能夠防止第1基板10與第2基板11之間隔過度變窄。
因此，根據半導體裝置1，能夠防止於對第1基板10積層第2基板11時，連接層7之焊料被過度擠壓而下垂，附著於第1基板10之鈍化膜5而產生電流洩漏。
再者，於第1Ni電極6頂面距鈍化膜5表面之高度為1μm~10μm、支持部72之高度(厚度)為17μm~25μm之情形時，若支持部72之佔有面積為第1基板10表面之面積之10%~50%，則能夠防止焊料下垂。
接下來，參照圖2~圖7，對實施形態之半導體裝置1之製造方法進行說明。圖2~圖7係表示實施形態之半導體裝置1之製造步驟之說明圖。以下，藉由對圖2~圖7所示之構成要素中與圖1所示之構成要素相同之構成要素標註與圖1所示之符號相同之符號，而省略該相同部分之詳細說明。
又，第1基板10製造步驟與第2基板11之製造步驟除了在形成於半導體層8之半導體元件及積體電路之形成步驟之方面不同以外，皆為相同之步驟。因此，此處對第1基板10之製造步驟進行說明，省略有關第2基板11之製造步驟之說明。
又，第1基板10之製造步驟中，於半導體層8上形成第1絕緣層30及多層配線3之步驟與通常之半導體裝置之製造步驟相同，因此，此處省略該步驟之說明。
於製造半導體裝置1之情形時，如圖2(a)所示般，準備於半導體層8上形成有第1絕緣層30及多層配線3之第1基板10。之後，如圖2(b)所示，例如藉由利用CVD(Chemical Vapor Deposition，化學氣相沈積)於第1絕緣層30上積層SiO2而形成第2絕緣層4。
繼而，例如利用RIE(Reactive Ion Etching，反應離子蝕刻法)自第 2絕緣層4選擇性地去除形成鋁墊40之部分之SiO2後，使用Ti被覆第2絕緣層4之表面，藉此形成障壁金屬膜41。
之後，例如藉由濺鍍於第2絕緣層4上積層Al(鋁)後，例如利用RIE將鋁圖案化。如此，如圖2(b)所示，於第2絕緣層4上形成鋁墊40。
繼而，如圖2(c)所示，藉由在形成有鋁墊40之第2絕緣層4上積層SiN或聚醯亞胺，而形成鈍化膜5。再者，亦可於與鋁墊40之間隔著SiO2而形成鈍化膜5。
之後，如圖3(a)所示，於鈍化膜5上塗佈阻劑100，利用光微影法選擇性地去除第1Ni電極6(參照圖1)之形成位置上之阻劑100。
然後，藉由進行將剩餘之阻劑100作為遮罩之蝕刻，而於鈍化膜5之第1Ni電極6之形成位置，形成自鈍化膜5之表面到達至由障壁金屬膜41被覆之鋁墊40之表面之開口101。
繼而，如圖3(b)所示，於去除阻劑100後，使用Ti被覆鈍化膜5之上表面、開口101之內周面及底面，藉此形成障壁金屬膜60。進而，藉由使用Cu被覆障壁金屬膜60之表面，而形成籽晶膜61a。
繼而，如圖3(c)所示，於籽晶膜61a之表面塗佈阻劑102之後，選擇性地去除第1Ni電極6(圖1參照)之形成位置上之阻劑102，藉此使由籽晶膜61a被覆之開口101露出。
之後，如圖4(a)所示，藉由於去除阻劑102而露出之部分之籽晶膜61a上積層Ni，而形成第1Ni電極6。Ni之積層係藉由使用籽晶膜61a作為電極膜之電解電鍍而進行。再者，於第1Ni電極6與籽晶膜61a接觸之部分，之後會有Ni自第1Ni電極6向籽晶膜61a擴散、Cu自籽晶膜61a向第1Ni電極6擴散。
藉此，已與第1Ni電極6接觸部分之籽晶膜61a成為Cu與Ni之合金而成為第1Ni電極6之一部分，於第1Ni電極6之與障壁金屬膜60接觸之 部分形成Cu擴散區域61。
其結果，於障壁金屬膜60與第1Ni電極6之間不存在純粹之Cu之區域。如此形成如下之第1Ni電極6，即該第1Ni電極6之一部分埋設於形成有障壁金屬膜60之開口101並與鋁墊40連接，並且頂面自鈍化膜5之表面突出。
之後，於第1Ni電極6之上表面形成Au膜103後，如圖4(b)所示，去除阻劑102。然後，藉由進行將上表面形成有Au膜103之第1Ni電極6用作遮罩之RIE，而自鈍化膜5之上表面去除無用部分之籽晶膜61a及障壁金屬膜60。
繼而，於半導體層8之內部形成貫通電極81。此處，例如於半導體層8之下表面形成保護膜80，並形成自半導體層8之下表面到達至第1配線31之下表面之TSV(Through Silicon Via，矽穿孔)，利用障壁金屬膜82被覆TSV之內周面之後，於TSV之內部埋入Cu，藉此形成貫通電極81。
之後，如圖4(c)所示，對保護膜80進行與已參照圖3及圖4說明之步驟相同之步驟，並進行障壁金屬膜90之形成、及於與障壁金屬膜90接觸之部分具備Cu擴散區域91之第2Ni電極9之形成。
藉此，形成一部分埋設於保護膜80中且頂面自保護膜80之表面(此處為下表面)突出之柱狀之第2Ni電極9。然後，於第2Ni電極9之頂面(此處為下表面)形成Au膜104。
繼而，如圖5所示，於第1基板10之下表面塗佈具有感光性之接著性樹脂105。之後，進行曝光，藉由顯影去除被照射光之部分之接著性樹脂105。由此，形成圖6(a)所示之支持部72。然後，藉由在Au膜104之下表面形成焊料層，而如圖6(b)所示般形成連接層7。
再者，於連接層7與Au膜104接觸之部分，之後會有焊料自連接層7向Au膜104擴散、Au自Au膜104向連接層7擴散。藉此，與連接層7 接觸部分之Au膜104成為Au與焊料之合金而成為連接層7之一部分，於連接層7之與第2Ni電極9接觸之部分形成Au擴散區域71，從而完成第1基板10。
最後，如圖7所示，於已完成之第1基板10上配置已完成之第2基板11，並進行第1基板10之第1Ni電極6與對應之第2基板11之連接層7之定位，之後於第1基板10上積層第2基板11。藉此，完成圖1所示之半導體裝置1。
如上所述，實施形態之半導體裝置中，第1基板與第2基板係藉由第1基板側之第1Ni電極、焊料之連接層及第2基板側之第2Ni電極之3種構成要素之積層體而連接。
藉此，與被積層之基板間係藉由柱形電極、障壁層、焊料層、障壁層及柱形電極之5種構成要素之積層體而連接之通常之半導體裝置相比，實施形態之半導體裝置能夠實現厚度方向上之小型化。
已對本發明之若干實施形態進行了說明，但該等實施形態係作為示例而提出，並非意圖限定發明之範圍。該等新穎之實施形態能以其他各種方式實施，且可於不脫離發明主旨之範圍內進行各種省略、置換、變更。該等實施形態及其變化包含於發明之範圍或主旨內，並且包含於申請專利範圍所記載之發明及其均等之範圍內。

Claims (6)

  1. 一種半導體裝置，其特徵在於具備：第1基板，其於內部具有配線；鋁墊，其設置於上述第1基板之表層內，與上述配線連接；第1鎳電極，其設置於上述鋁墊之正上方，一部分埋設於上述第1基板並與上述鋁墊連接，且其頂面自上述第1基板之表面突出；第2基板，其積層於上述第1基板；第2鎳電極，其一部分埋設於上述第2基板，且其頂面自上述第2基板之上述第1基板側之表面突出；及連接層，其由含錫之合金形成，且將上述第1鎳電極及上述第2鎳電極之間連接。
  2. 如請求項1之半導體裝置，其具備障壁金屬膜，該障壁金屬膜由鈦形成，設置於上述第1鎳電極、與上述第1基板及上述鋁墊之界面，且上述第1鎳電極係：與上述障壁金屬膜接觸之部位包含銅。
  3. 如請求項1或2之半導體裝置，其中上述連接層係：與上述第1鎳電極接觸之部位及與上述第2鎳電極接觸之部位包含金。
  4. 如請求項1或2之半導體裝置，其具備支持部，該支持部之一端面抵接於上述第1基板之表面，另一端面抵接於上述第2基板之上述第1基板側之表面。
  5. 一種半導體裝置之製造方法，其特徵在於包含如下步驟：於內部具有配線之第1基板之表層內，形成與上述配線連接之 鋁墊；形成自上述第1基板之表面到達上述鋁墊之表面之開口；於上述開口之內周面及底面，由鈦形成障壁金屬膜；形成第1鎳電極，該第1鎳電極之一部分埋設於形成有上述障壁金屬膜之上述開口並與上述鋁墊連接，且頂面自上述第1基板之表面突出；形成第2鎳電極，該第2鎳電極之一部分埋設於積層於上述第1基板之第2基板，且頂面自上述第2基板之表面突出；於上述第1鎳電極之頂面及上述第2鎳電極之頂面之兩者或一者，藉由含錫之合金積層連接層；及於上述第1基板積層上述第2基板，經由上述連接層而將上述第1鎳電極與上述第2鎳電極連接。
  6. 如請求項5之半導體裝置之製造方法，其進而包含形成支持部之步驟，該支持部之另一端面抵接於上述第2基板之上述第1基板側之表面；且將上述第1鎳電極與上述第2鎳電極連接之步驟包含將上述支持部之上述一端面抵接於上述第1基板之表面。
TW104138995A 2015-05-29 2015-11-24 Semiconductor device and method of manufacturing the same TWI621220B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015110601A JP2016225466A (ja) 2015-05-29 2015-05-29 半導体装置および半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW201642398A TW201642398A (zh) 2016-12-01
TWI621220B true TWI621220B (zh) 2018-04-11

Family

ID=57397227

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104138995A TWI621220B (zh) 2015-05-29 2015-11-24 Semiconductor device and method of manufacturing the same

Country Status (4)

Country Link
US (1) US9893036B2 (zh)
JP (1) JP2016225466A (zh)
CN (1) CN106206505B (zh)
TW (1) TWI621220B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10269697B2 (en) 2015-12-28 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
EP3542953A4 (en) 2016-11-18 2020-07-08 Agc Inc. DEVICE FOR MACHINING A CURVED PLATE, AND METHOD FOR MANUFACTURING A CURVED PLATE HAVING A MACHINED EXTERNAL CIRCUMFERENCE
US10818627B2 (en) * 2017-08-29 2020-10-27 Advanced Semiconductor Engineering, Inc. Electronic component including a conductive pillar and method of manufacturing the same
US11127704B2 (en) * 2017-11-28 2021-09-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with bump structure and method of making semiconductor device
US10529693B2 (en) * 2017-11-29 2020-01-07 Advanced Micro Devices, Inc. 3D stacked dies with disparate interconnect footprints
US10727204B2 (en) 2018-05-29 2020-07-28 Advances Micro Devices, Inc. Die stacking for multi-tier 3D integration
US10937755B2 (en) 2018-06-29 2021-03-02 Advanced Micro Devices, Inc. Bond pads for low temperature hybrid bonding
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101989557A (zh) * 2009-07-30 2011-03-23 株式会社东芝 半导体装置的制造方法以及半导体装置
US20140327150A1 (en) * 2012-08-03 2014-11-06 Deok-Young Jung Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
TW201508889A (zh) * 2013-08-21 2015-03-01 Toshiba Kk 半導體裝置及半導體裝置之製造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001077295A (ja) * 1999-09-03 2001-03-23 Sony Corp 半導体装置の製造方法
TWI230989B (en) * 2004-05-05 2005-04-11 Megic Corp Chip bonding method
JP2006294826A (ja) * 2005-04-11 2006-10-26 Matsushita Electric Ind Co Ltd 半導体装置および半導体装置の製造方法
JP2007048919A (ja) * 2005-08-10 2007-02-22 Sony Corp バンプの形成方法
JP4611943B2 (ja) * 2006-07-13 2011-01-12 Ｏｋｉセミコンダクタ株式会社 半導体装置
KR100762354B1 (ko) * 2006-09-11 2007-10-12 주식회사 네패스 플립칩 반도체 패키지 및 그 제조방법
JP2011165862A (ja) * 2010-02-09 2011-08-25 Sony Corp 半導体装置、チップ・オン・チップの実装構造、半導体装置の製造方法及びチップ・オン・チップの実装構造の形成方法
US20110227216A1 (en) * 2010-03-16 2011-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Under-Bump Metallization Structure for Semiconductor Devices
CN102201389A (zh) * 2010-03-23 2011-09-28 卡西欧计算机株式会社 设有锡扩散抑制层的半导体装置及其制造方法
JP2012080043A (ja) * 2010-10-06 2012-04-19 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
KR101607790B1 (ko) * 2012-01-17 2016-03-30 파나소닉 아이피 매니지먼트 가부시키가이샤 반도체 장치 제조 방법 및 반도체 장치
JP2013187259A (ja) * 2012-03-06 2013-09-19 Toshiba Corp 半導体装置および半導体装置の製造方法
JP2014011309A (ja) * 2012-06-29 2014-01-20 Ps4 Luxco S A R L 半導体装置およびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101989557A (zh) * 2009-07-30 2011-03-23 株式会社东芝 半导体装置的制造方法以及半导体装置
US20140327150A1 (en) * 2012-08-03 2014-11-06 Deok-Young Jung Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
TW201508889A (zh) * 2013-08-21 2015-03-01 Toshiba Kk 半導體裝置及半導體裝置之製造方法

Also Published As

Publication number Publication date
JP2016225466A (ja) 2016-12-28
CN106206505A (zh) 2016-12-07
US9893036B2 (en) 2018-02-13
TW201642398A (zh) 2016-12-01
US20160351540A1 (en) 2016-12-01
CN106206505B (zh) 2020-06-09

Similar Documents

Publication Publication Date Title
TWI621220B (zh) Semiconductor device and method of manufacturing the same
JP4611943B2 (ja) 半導体装置
US9576921B2 (en) Semiconductor device and manufacturing method for the same
CN100428414C (zh) 形成低应力多层金属化结构和无铅焊料端电极的方法
TWI555090B (zh) 電子裝置及用於製造其之方法
TWI712140B (zh) 半導體裝置及半導體裝置的製造方法
US9035455B2 (en) Semiconductor device
TWI720233B (zh) 半導體裝置及其製造方法
JP6277693B2 (ja) 半導体装置
US20080099919A1 (en) Semiconductor device including copper interconnect and method for manufacturing the same
JP4506767B2 (ja) 半導体装置の製造方法
JP2008244134A (ja) 半導体装置及びその製造方法
JP5273920B2 (ja) 半導体装置
JP6836615B2 (ja) 半導体装置および半導体装置の製造方法
US11876064B2 (en) Semiconductor structure and manufacturing method thereof
TWI576869B (zh) 被動元件結構及其製作方法
JPH02253628A (ja) 半導体装置の製造方法
JP2013128145A (ja) 半導体装置
TWI587418B (zh) 半導體裝置及其製造方法
JP5273921B2 (ja) 半導体装置およびその製造方法
JP2005085884A (ja) 半導体装置およびその製造方法
KR101671973B1 (ko) 다층 금속 범프 구조체 및 그 제조방법
TWI339416B (en) Method of forming conductive bumps with different diameters
JP4986721B2 (ja) 半導体装置およびその製造方法
JP2019160912A (ja) 半導体装置およびその製造方法