1339416 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種形成尺寸不同之導電凸塊的 方法，特別是提供一種形成尺寸不同之電鍍凸塊的 方法。 【先前技術】 隨著晶圓級封裝技術的改進，於製作封裝上變 得愈來愈普遍使用晶圓級封裝。傳統的晶圓設計，禮春 包含許多相同的晶片單元，因此對應於封裝所需的連接墊‘ 與凸塊的尺寸亦相同。 然而，為了降低製程成本，考慮將不同的晶片設計置 於同一晶圓上時，對應於封裝所需的連接墊與凸塊的尺寸 便有所變化，連接墊與凸塊的尺寸不但相異，亦可能尺寸 差異很大。上述的設計制於傳統封裝製程中可能會面臨. 若干問題。 舉例來說’當於晶圓上以電鍍方式形成導電凸塊時， 由於凸塊的尺寸相異’因此於相同的電錢條件下，相同的 電鑛里於尺寸較大的導電凸塊中所呈現的高度則較低。根 1339416 據上述’晶圓上便彬成高度相異的導電凸塊，當與基板結 合時，晶圓中較低的導電凸塊會受制於較高的導電凸塊， 如此可能產生若干導電凸塊無法形成良好的連接， 成良率的降低，反而無法達到降低成本的目的。 【發明内容】 有鑑於上述背景中’有關晶圓級封骏中 不同尺 寸之導電凸塊的設計所需，於此提供一種不同 電凸塊的形成方法’利用電鍍時溢鍍的方* 丨、，可、 確保不同尺寸的導電凸塊具有相同的凸塊高度。乂 戍方 導電 再者，爲了製作具有相同高度但不同尺冲 電凸塊，於此提供一種不同尺寸導電凸塊的形 法’電鍍溢鍍完後利用蝕刻的方式移除過多的 材料，可以形成高度一致但不同尺寸之導電凸绳1339416 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of forming conductive bumps of different sizes, and more particularly to a method of forming plated bumps of different sizes. [Prior Art] With the improvement of wafer-level packaging technology, wafer-level packaging has become more and more popular in manufacturing packages. In the traditional wafer design, Li Chun contains many of the same wafer units, so the connection pads required for the package are the same as the bumps. However, in order to reduce the cost of the process, when the different wafer designs are placed on the same wafer, the size of the connection pads and bumps required for the package varies, and the size of the connection pads and bumps are not only different. It is also possible that the sizes vary widely. The above design may face several problems in the traditional packaging process. For example, when the conductive bumps are formed by electroplating on the wafer, the bumps are different in size. Therefore, under the same electricity-money conditions, the same electric ore is in the larger-sized conductive bumps. The height of the presentation is lower. Root 1339416 According to the above-mentioned 'wafers are highly different conductive bumps, when combined with the substrate, the lower conductive bumps in the wafer will be subject to higher conductive bumps, which may produce several conductive bumps The block cannot form a good connection, and the yield is reduced, but the cost reduction cannot be achieved. SUMMARY OF THE INVENTION In view of the above-mentioned background, in view of the design requirements of different sizes of conductive bumps in the wafer level seal, a method for forming different electric bumps is provided, which utilizes the plating method during plating. , to ensure that different sizes of conductive bumps have the same bump height. In order to make the conductive bumps of the same height but different scales, the method of providing a different size of conductive bumps is provided. After the plating is overplated, excess material is removed by etching, which can be formed. Highly uniform but different sizes of conductive camons
再者，爲了於晶圓上製作具有相同高度1曰 尺寸之導電凸塊，於此提供—種不同尺寸導電凸 形成方法，電鍍溢鍍完後利用化學機械研磨的 7 1339416 可以形成高度一致但不同尺 移除過多的導電·材料 寸之導電凸塊。 巧，本發明之一實施例 種不同尺寸導電凸塊 尼的心成方法。一晶圓結構上具 有導：連接、構。一遮罩層形成於導電連接結構 上’之後移除部份遮罩層以形成大小相異的一第一 開口與-第—開m部分導電連接結#。電一 一導電層填滿第—pq k 渴口’、第二開口並覆蓋於遮罩層 上。移除部份導電層 恭路出遮罩層，最後移除所 有的遮罩層。 【實施方式】 本么明之實知例用示意圖詳細描述如下，在詳述本發 明之實施例時’表示晶圓表面的部份會放大顯示並說 然不應以此作為有限定的認知。此外，在實際的晶圓表面 與方法中，可以包含此結構中其他必要的部分。 其次，當本發明之實施例圖式中的各元件或結構以單— 元件或結構描述說明時，不應以此作為有限定的認知，即 如下之說明未特別強調數目上的限制時，本發明之精神與 應用範圍可推及多數個元件或結構並存的結構與方法上。 第- A至第-D圖所示為本發明之一實施例進行凸 塊製程的側面示意圖。參照第一 A圖’ 一晶圓1〇上可分 為苐-區域5a與第二區域5b，根據後續所形成的連接導 電凸塊尺寸，例如&塊直徑而言，位於第—㈣以的導 電凸塊將小於位於第二區@ 5b的導電凸塊。此外，於晶參 圓ίο上，第-區域5a與第二區域5b可分別位於連續的， 兩個部分，例如位於晶圓的一半圓表面上，或是第一區域， 5a與第二區域％各包含獨立的次區域且可彼此參雜分. 布’視實際設計所需而定。 於晶圓10上以適當的方式形成若干金屬連接墊l2a /、12b(connecting pad) ’例如鋁接墊或銅接墊，分別分義 布於第區域5a與第二區域5b。之後一絕緣保護層 14(passivationlayer)覆蓋於晶® 10SS上並分別暴露出. 金屬連接I 12a與金屬連接# 12b的若干表面。接著.， t ▲的方法，例如電鑛或減鑛的方式，將導電連接 °構1 6覆蓋於絕緣保護層Μ與暴露出的金屬連接塾12a 與金屬連接墊121)表面上形成一導電表面。於一實施例 中，導電連接結構1 6為一般多層的下凸塊金屬結構 (UBM)例如包含阻障層與潤濕/黏著層，其導電材料視後 續欲形成的錫紹r凸塊或無錯凸塊而定。 之後，一遮罩層18(masklayer)覆蓋於導電連接結構· 上亚以適當的方式移除部分的遮罩層1 8以形成若干開口 2〇a(第一開口）與開口 2〇b(第二開口）分別位於金屬連接智· 12a與金屬連接墊12b的上方。於一實施例中，遮罩層丨8 . 為一感光乾膜以貼附方式覆蓋，利用一般微影與蝕刻方式. 移除。於另一實施例中’遮罩層18亦可為一液態光阻以 旋塗方式覆蓋，但本發明不限於上述。再者，於一實施例、 中遮罩層18的尽度紅圍可從25微米（micr〇n meter)到1 5〇 微米不等，視後續欲形成之導電凸塊的高度而定，但本發 明不限於上述。此外，開口 20a與開口 2〇b則視後續欲形參 成之導電凸塊的直徑而定，開口寬度範圍可從5微米 (micron meter)到1毫米（milnmeter)不等。可以理解的是， 由於後續位於第一區域5a的導電凸塊將小於位於第二區、 域5b的導電凸塊，因此’開口 2〇a的開口寬度小於開口 2〇b 的開口寬度。 1339416 要說明的是’本發明亦適用於遽罩層18形成於絕緣保 護層】4上並形成開口 20a與開口 20b後，導電達接結構16 再利用濺鍍的方式形成於開口 20a與開口 20b中。 參照第一 B圖，一導電層22，例如錫鉛（s〇lder)、銅 或錦寺無錯金屬或合金材料，填滿開口 2〇a與開口 並 後蓋於遮罩層丨8上。於一實施例中，導電層22係以電鑛 的方式進行，即溢鍍（。幫plating)導電層22於晶圓ι〇上。籲 要說明的是，由於開口 2〇a的開口寬度小於開p烏的開 口寬度，因此於相同的電鍍條件與時間下，位於第一區域 Sa的導電層22之溢鍍厚度（即超出導電層22表面的厚度） 會大於位於第二區域5b的導電層22之溢鍍厚度。 之伋’參照第- C圖’溢鍍的導電層22 α半導體製 程令使料移除方式移心《出遮罩層18的表面。於丨 -實施例中，她刻的方式，例如祕刻的方式，移除 多餘（即超出導電工 曰2表面的厚度）的導電層22。相較於 —般半導體製程中使用 、 蝕幻的方式’本實施例中由於遮罩 層18與導電層22奸 2材枓特性’特別是光阻的導電層22的 11 1339416 關係’於選用㈣液或考量㈣選擇比（etch selectivity) 時會較一般半導體製程中更有彈性。再者，本發明中所需 移除的導電層22 m於—般半導體製料所需移除 結構的量。 於另f把例中’利用化學機械研磨的方式(c丨職iea丨 mechanical p〇iishlng，CMp)移除多餘的導電層&於選擇 化學機械研磨參數與條件時，選用機械研磨能力為主的场 數與條件即可移除多餘的導電層22。根據上述，利用形-成過多的導電層22於遮罩層18上後再以蝕刻或化學機 械研磨的方式移除多餘的導電層22，如此可得到直徑尺寸-相異（開口 20a與開口 20b)但高度相同的導電凸塊於單一- 晶圓10上，使得晶圓1〇與其封裝結構的設計上更具有彈 性0 參照第一 D圖，晶圓1 〇上所有的遮罩層丨8以適當的 方式移除後形成若干導電凸塊22a與導電凸塊22b分別位 於金屬連接墊12a與金屬連接墊12b的上方，即分別分 布於第一區域5a與第二區域5b内。之後可再利用回鲜處 理導電凸塊22a與導電凸塊22b，並且以適當方式移除暴 12 露出的導電連接結構16(圖上未示）。根據上述本發明之精 神所得的導電凸塊22a與導電凸塊22b的直徑雖然不同， 但高度可保持相同。 根據上述’本發明之一實施例中提供一種不同尺寸 導電凸塊的形成方法。一晶圓結構上具有一導電連 接結構。一遮罩層形成於導電連接結構上，之後移 除部份遮罩層以形成大小相異的一第一開口與一第丨 一開口暴露出部分導電連接結構。電鍍一導電層填 滿第一開口與第二開口並覆蓋於遮罩層上。利用蝕 刻或化學機械研磨方式移除部份導電層至暴露出遮 罩層’最後移除所有的遮罩層。 以上所述之實施例僅係為說明本發明之技術思想及特 點’其目的在使熟習此項技藝之人士能夠瞭解本發明之、 容並據以實施’當不能以之限定本發明之專利範圍，即大 =依本發明所揭示之精神所作之均等變化或修飾，仍應涵 蓋在本發明之專利範圍内。 D圖所不為本發明之一實施例進行凸 【圖式簡單說明】 第一 A至第一 13 1339416 塊製程中步驟的側面示意圖。 【主要元件符號說明】 5a 第一區域 5b 第二區域 10 晶圓 12a 金屬連接墊 12 b 金屬連接塾 14 絕緣保護層 16 導電連接結構 18 遮罩層 20a，b 開口 22 導電層 22a,b 導電凸塊 14Furthermore, in order to fabricate conductive bumps having the same height of 1 晶圆 on the wafer, a method for forming conductive bumps of different sizes is provided, and 7 1339416 using chemical mechanical polishing after electroplating can be formed to be highly uniform but different. The ruler removes too many conductive bumps of conductive material. In one embodiment of the invention, a method of forming a core of different sizes of conductive bumps. A wafer structure has a guide: connection, structure. A mask layer is formed on the conductive connection structure' after removing a portion of the mask layer to form a first opening and a -m-th portion of the conductive connection junction #. An electrically conductive layer fills the first -pq k thirsty port, the second opening and overlies the mask layer. Remove some of the conductive layer. Walk out the mask layer and finally remove all the mask layers. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The detailed description of the present invention will be described in detail with reference to the accompanying drawings, and in the embodiment of the present invention, the portion of the surface of the wafer is shown enlarged and should not be taken as a limited understanding. In addition, other necessary portions of the structure may be included in the actual wafer surface and method. In the following, when the elements or structures in the drawings of the embodiments of the present invention are described in the form of a single element or a structure, the present invention should not be construed as limited, that is, the following description does not particularly emphasize the limitation of the number. The spirit and scope of the invention can be applied to structures and methods in which a plurality of elements or structures coexist. The first to fourth to D-D are schematic side views showing a bump process according to an embodiment of the present invention. Referring to FIG. 1A', a wafer 1 can be divided into a 苐-region 5a and a second region 5b, which are located at the first (fourth) according to the size of the connected conductive bump formed subsequently, for example, & The conductive bumps will be smaller than the conductive bumps located in the second region @5b. In addition, on the crystallographic circle ίο, the first region 5a and the second region 5b may be respectively located in two consecutive portions, for example, on a semicircular surface of the wafer, or in the first region, 5a and the second region% Each contains separate sub-areas and can be mixed with each other. The cloth 'depends on the actual design needs. A plurality of metal connection pads 12a, 12b (connecting pads), such as aluminum pads or copper pads, are formed on the wafer 10 in a suitable manner, and are respectively distributed in the first region 5a and the second region 5b. A passivation layer 14 is then overlaid on the Crystal® 10SS and exposed, respectively, to several surfaces of the metal connection I 12a and the metal connection # 12b. Then, the method of t ▲, such as electric ore or anti-mining, covers a conductive surface of the insulating protective layer Μ with the exposed metal connection 塾 12a and the metal connection pad 121) to form a conductive surface. . In one embodiment, the conductive connection structure 16 is a general multi-layered lower bump metal structure (UBM) including, for example, a barrier layer and a wet/adhesive layer, the conductive material of which is formed according to the subsequent tin-sl bumps or Depending on the bump. Thereafter, a mask layer 18 is overlaid on the conductive connection structure. The upper portion removes a portion of the mask layer 18 in an appropriate manner to form a plurality of openings 2〇a (first opening) and openings 2〇b (first The two openings are respectively located above the metal connection Wi- 12a and the metal connection pad 12b. In one embodiment, the mask layer 丨8 is covered by a photosensitive dry film in a manner of attachment, using general lithography and etching. In another embodiment, the mask layer 18 may also be covered by a liquid photoresist in a spin coating manner, but the invention is not limited to the above. Moreover, in one embodiment, the full redness of the mask layer 18 may vary from 25 micrometers to 15 micrometers, depending on the height of the conductive bumps to be formed later, but The invention is not limited to the above. In addition, the opening 20a and the opening 2〇b depend on the diameter of the conductive bumps to be subsequently formed, and the opening width may range from 5 micron to 1 millimeter. It can be understood that since the conductive bumps located in the first region 5a will be smaller than the conductive bumps located in the second region and the field 5b, the opening width of the opening 2〇a is smaller than the opening width of the opening 2〇b. 1339416 It is to be noted that, after the invention is also applied to the underlayer 18 formed on the insulating protective layer 4 and forming the opening 20a and the opening 20b, the conductive connecting structure 16 is formed on the opening 20a and the opening 20b by sputtering. in. Referring to Fig. B, a conductive layer 22, such as a tin-lead, copper or jinsi error-free metal or alloy material, fills the opening 2〇a and the opening and is then overlaid on the mask layer 8 . In one embodiment, the conductive layer 22 is performed in the form of an electric ore, that is, the plating layer 22 is deposited on the wafer. It is to be noted that since the opening width of the opening 2〇a is smaller than the opening width of the opening, the thickness of the conductive layer 22 located in the first region Sa is over the conductive layer under the same plating conditions and time. The thickness of the surface 22 will be greater than the thickness of the overlying plating layer 22 located in the second region 5b. Thereafter, the surface of the mask layer 18 is removed by referring to the conductive layer 22 of the -C diagram's overplated conductive layer 22 semiconductor process. In the embodiment - the conductive layer 22 is removed in excess (i.e., beyond the thickness of the surface of the conductive work 2) in a manner such as a secret engraving. Compared with the way of using, ecstasy in the semiconductor process, in this embodiment, the relationship between the mask layer 18 and the conductive layer 22, especially the resistance of the conductive layer 22 of the photoresist, is selected (4). Liquid or consideration (4) etch selectivity is more flexible than the average semiconductor process. Furthermore, the amount of conductive layer 22 m required to be removed in the present invention is the amount of structure required to remove the semiconductor material. In the other example, the method of chemical mechanical polishing (using ie ie ie ie ie ie ie ie ie 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除The excess conductive layer 22 can be removed by the number of fields and conditions. According to the above, the excess conductive layer 22 is removed by etching or chemical mechanical polishing after forming the excessive conductive layer 22 on the mask layer 18, so that the diameter dimension-differentiation can be obtained (the opening 20a and the opening 20b). However, the same height of the conductive bumps on the single-wafer 10 makes the wafer 1〇 and its package structure more flexible. Referring to the first D-picture, all the mask layers 8 on the wafer 1 are After being removed in a proper manner, a plurality of conductive bumps 22a and conductive bumps 22b are respectively disposed above the metal connection pads 12a and the metal connection pads 12b, that is, respectively, in the first region 5a and the second region 5b. The conductive bumps 22a and the conductive bumps 22b may then be processed by the freshening and the conductive connection structures 16 (not shown) exposed by the storms 12 are removed in an appropriate manner. Although the diameters of the conductive bumps 22a and the conductive bumps 22b obtained by the above-described spirit of the present invention are different, the heights can be kept the same. A method of forming conductive bumps of different sizes is provided in accordance with one embodiment of the present invention. A wafer structure has a conductive connection structure. A mask layer is formed on the conductive connection structure, and then a portion of the mask layer is removed to form a first opening having a different size and a first opening to expose a portion of the conductive connection structure. A conductive layer is plated to fill the first opening and the second opening and overlie the mask layer. Part of the conductive layer is removed by etching or chemical mechanical polishing to expose the mask layer. Finally, all of the mask layers are removed. The embodiments described above are merely illustrative of the technical spirit and the characteristics of the present invention. The purpose of the present invention is to enable those skilled in the art to understand the present invention and to implement the invention. Equivalent changes or modifications made in accordance with the spirit of the present invention should still be covered by the scope of the present invention. Figure D is not a convex embodiment of the present invention. [Simplified illustration of the drawings] A side view of the steps in the block process of the first A to the first 13 1339416. [Main component symbol description] 5a First region 5b Second region 10 Wafer 12a Metal connection pad 12 b Metal connection 塾 14 Insulation protection layer 16 Conductive connection structure 18 Mask layer 20a, b Opening 22 Conductive layer 22a, b Conductive convex Block 14