CN102201389A - 设有锡扩散抑制层的半导体装置及其制造方法 - Google Patents

设有锡扩散抑制层的半导体装置及其制造方法 Download PDF

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CN102201389A
CN102201389A CN201110070548XA CN201110070548A CN102201389A CN 102201389 A CN102201389 A CN 102201389A CN 201110070548X A CN201110070548X A CN 201110070548XA CN 201110070548 A CN201110070548 A CN 201110070548A CN 102201389 A CN102201389 A CN 102201389A
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layer
semiconductor device
suppresses
distribution
tin diffusion
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CN201110070548XA
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定别当裕康
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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Priority claimed from JP2010066190A external-priority patent/JP2011199130A/ja
Priority claimed from JP2010070524A external-priority patent/JP2011204894A/ja
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Publication of CN102201389A publication Critical patent/CN102201389A/zh
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Abstract

一种半导体装置，在配线(7)的焊接区上方设有锡扩散抑制层(12)，在该锡扩散抑制层(12)上方设有焊球(13)。从而，即使该半导体装置为处理大电流的电源IC等，也能够通过锡扩散抑制层(12)的存在而进一步抑制焊球(13)中的锡向配线(7)扩散。

Description

设有锡扩散抑制层的半导体装置及其制造方法
技术领域
本发明涉及设有锡扩散抑制层的半导体装置及其制造方法。
背景技术
根据WO2003/012863号公报，已知在设于半导体基板上的配线的焊接区(land)上设有焊球。此时，在由铜构成的配线的焊接区上表面，为了降低接触电阻、促进焊料的反应性，而设有由镍等构成的镀膜、且在该镀膜的上表面设有焊球。
另外，虽然在WO2003/012863号公报中没有关于镀膜的形成方法的记载，但是，由于将配线的焊接区以外的部分用涂覆膜(overcoat film)覆盖，在与配线的焊接区相对应部分的、形成于涂覆膜的开口部中的配线的焊接区上表面，形成厚度比涂覆膜厚度薄的镀膜，因此，认为镀膜通过无电解镀而形成。
若焊球中的锡一直扩散到由铜构成的配线的内部，则由于在配线中形成由锡和铜构成的较脆的合金层或产生空隙，从而易于发生断线等情况。因此，若在配线的焊接区上表面形成由镍等构成的镀膜，则镀膜作为锡扩散抑制层而发挥作用。
但是，对于处理大电流的电源IC等的半导体装置来说，由于电迁移现象而使得焊球中的锡向配线内部的扩散速度变得非常快。另一方面，若通过无电解镀而进行镀膜的形成，则由于无电解镀的特性而使得镀膜厚度比较薄，即使厚也不足5μm。并且，在溅射的情况下，则厚度为(0.2～0.5μm)的程度。因此，对于处理大电流的电源IC等的半导体装置来说，即使在配线的焊接区上表面通过无电解镀形成镀膜，也存在锡扩散抑制功能不足的问题。
发明内容
因此，本发明的目的在于，提供一种半导体装置及其制造方法，能够进一步抑制焊球中的锡向其下的金属层及配线扩散，并且能够进一步缓和施加于焊球的应力。
根据本发明的一实施方式，提供一种半导体装置，其特征在于，具有：
半导体基板；
配线，经由绝缘膜而设于所述半导体基板上；
锡扩散抑制层，设于所述配线的上方；和
焊料凸块，设于所述锡扩散抑制层上，
所述锡扩散抑制层的熔点比所述焊料凸块的熔点高。
根据本发明的另一实施方式，提供一种半导体装置，其特征在于，具有：
半导体基板；
配线，经由绝缘膜而设于所述半导体基板上；
锡扩散抑制层，设于所述配线上；
氧化抑制层，设于所述锡扩散抑制层上；和
焊料凸块，搭载于所述氧化抑制层上，
所述氧化抑制层在所述焊料凸块搭载前被覆膜。
根据本发明的另一实施方式，提供一种半导体装置的制造方法，其特征在于，
在形成有配线的具有绝缘膜的半导体基板上的所述配线上，以规定的温度加热导电性膏，形成在所述规定温度下不发生再熔融的锡扩散抑制层，
在所述锡扩散抑制层上形成焊球。
根据本发明的另一实施方式，提供一种半导体装置的制造方法，其特征在于，
在经由半导体基板上的绝缘膜而形成的配线用上部金属层的焊接区上，形成锡扩散抑制层，
在所述锡扩散抑制层上形成抑制该锡扩散抑制层的氧化的氧化抑制层，
在所述氧化抑制层上形成焊料凸块。
附图说明
图1是作为本发明的第1实施方式的半导体装置的平面图。
图2是大致沿图1的II-II线的部分的剖视图。
图3是图1及图2所示的半导体装置的制造方法的一例中、最初准备的结构的剖视图。
图4是继图3的工序的剖视图。
图5是继图4的工序的剖视图。
图6是继图5的工序的剖视图。
图7是继图6的工序的剖视图。
图8是继图7的工序的剖视图。
图9是继图8的工序的剖视图。
图10是继图9的工序的剖视图。
图11是继图10的工序的剖视图。
图12是继图11的工序的剖视图。
图13是作为本发明的第2实施方式的半导体装置的平面图。
图14是大致沿图13的X IV-X IV线的部分的剖视图。
图15是图13及图14所示的半导体装置的制造方法的一例中、最初准备结构的剖视图。
图16是继图15的工序的剖视图。
图17是继图16的工序的剖视图。
图18是继图17的工序的剖视图。
图19是继图18的工序的剖视图。
图20是继图19的工序的剖视图。
图21是继图20的工序的剖视图。
图22是继图21的工序的剖视图。
图23是继图22的工序的剖视图。
图24是作为本发明的第3实施方式的半导体装置的剖视图。
图25是作为本发明的第4实施方式的半导体装置的剖视图。
具体实施方式
(第1实施方式)
图1表示作为本发明第1实施方式的半导体装置的平面图，图2表示大致沿图1的II-II线的部分的剖视图。该半导体装置，一般称为CSP(chipsize package，芯片尺寸封装)，具有平面方形的硅基板(半导体基板)1。在硅基板1的上表面形成有未图示的元件，例如晶体管、二极管、电阻、电容等元件，上述元件构成规定功能的集成电路。在硅基板1的上表面周边部设有多个连接焊盘(connection pad)2，该连接焊盘2与上述集成电路的各元件连接，由铝类金属等构成。
在除硅基板1的周边部及连接焊盘2的中央部以外的硅基板1的上表面，设有由氧化硅等构成的钝化膜(绝缘膜)3，经由设于钝化膜3的开口部4使连接焊盘2的中央部露出。在钝化膜3的上表面设有由聚酰亚胺类树脂等构成的保护膜(绝缘膜5)。在与钝化膜3的开口部4对应部分的保护膜5处设有开口部6。
在保护膜5的上表面设有多个配线7。配线7为基底金属层8与上部金属层9组成的2层结构，该基底金属层8由设于保护膜5的上表面的铜等构成，该上部金属层9由设于基底金属层8的上表面的铜构成。配线7的一端部经由钝化膜3及保护膜5的开口部4、6连接于连接焊盘2。这里，如图1所示，配线7由连接于连接焊盘2的端部7a、平面圆形的焊接区7b、以及在两者间的引线部7c构成。并且，配线7的焊接区7b以矩阵状配置于保护膜5的上表面。
在硅基板1的周边部上表面及包含配线7的保护膜5的上表面，在配线7的焊接区7b以外的部分设有涂覆膜10，该涂覆膜10由聚酰亚胺类树脂、阻焊剂(solder resist)等构成。该状态下，在与配线7的焊接区7b对应的部分的涂覆膜10处，设有平面圆形的开口部11。
在涂覆膜10的开口部11内的配线7的焊接区7b上表面处，以平面圆形而设有圆顶(dome)状的锡扩散抑制层12。锡扩散抑制层12由下述融点上升型的焊料形成，该融点上升型焊料在后述的回流时，在180℃～280℃的加热温度下熔融并固化，之后，在同样的180℃～280℃的加热温度下不发生再熔融(remelted)，具体来说，由高铜含量的非共晶成分的锡铜类无铅焊料构成。
在锡扩散抑制层12的上表面设有焊球(焊料凸块)13。焊球13由下述非融点上升型的焊料形成，该非融点上升型焊料在后述的回流时，在180℃～280℃的加热温度下熔融并固化，之后，在同样的180℃～280℃的加热温度下再熔融，具体来说，由共晶成分的锡银类无铅焊料构成。
接着，对该半导体装置的制造方法的一例进行说明。首先，如图3所示进行准备，在晶片状态的硅基板(下面，称为半导体晶片21)的上表面形成由铝类金属等构成的多个连接焊盘2、由氧化硅等构成的钝化膜3及由聚酰亚胺类树脂等构成的保护膜5，并经由钝化膜3及保护膜5的开口部4、6使连接焊盘2的中央部露出。
此时，半导体晶片21的厚度比图2所示的基板1的厚度更厚。另外，在图3中，符号22所示的区域为切割道。之后，将与切割道22及其两侧对应的部分的钝化膜3及保护膜5去除。
接着，如图4所示，在包括经由钝化膜3及保护膜5的开口部4、6而露出的连接焊盘2的上表面的、保护膜5的上表面，以及与切割道22及其两侧对应的部分的半导体晶片21的上表面，形成基底金属层8。此时，基底金属层8可以仅是通过无电解镀形成的铜层，也可以仅是通过溅射形成的铜层，还可以是在通过溅射形成的钛等薄膜层上通过溅射形成有铜层的金属层。
接着，在基底金属层8的上表面，图案形成由正(positive)型的液状抗蚀剂构成的阻镀剂膜23。此时，在与上部金属层9形成区域相对应的部分的阻镀剂膜23处形成有开口部24。接着，若进行将基底金属层8作为镀电流通路的铜电解镀，则在阻镀剂膜23的开口部24内的基底金属层8的上表面形成上部金属层9。
接着，剥离阻镀剂膜23，然后，若将上部金属层9作为掩模来对除了该上部金属层9下以外的区域的基底金属层8进行刻蚀并去除，则如图5所示，仅在上部金属层9下残留基底金属层8。该状态下，通过上部金属层9与其下残留的基底金属层8，形成2层结构的配线7。
接着，如图6所示，在切割道22及其两侧的半导体晶片21的上表面及包括配线7的保护膜5的上表面，通过旋涂(spin coat)法、印刷法等，形成由聚酰亚胺类树脂、阻焊剂等构成的涂覆膜10。接着，在与配线7的焊接区7b相对应的部分的涂覆膜10处，通过照射激光束的激光加工或光刻法形成平面圆形的开口部11。
接着，如图7所示，在涂覆膜10上配置焊料膏(solder paste)印刷掩模25。此时，在与涂覆膜10的开口部11相对应的部分的焊料膏印刷掩模25处形成开口部26。接着，通过使涂刷器(squeegee)27在焊料膏印刷掩模25上移动的丝网印刷法，在焊料膏印刷掩模25及涂覆膜10的开口部26、11内的配线7的焊接区7b上表面处印刷焊料膏12a，形成焊料膏层12b。
此时，焊料膏12a通过下述融点上升型的焊料形成，该融点上升型焊料在后述的回流时，在180℃～280℃的加热温度下熔融并固化，之后，在同样的180℃～280℃的加热温度下不发生再熔融，具体来说，由含铜率高的非共晶成分的锡铜类无铅焊料构成，更具体来说，由使粒径15μm左右的锡粒子及铜粒子分散到焊剂中且为膏状的焊料膏构成。
接着，如图8所示，若以加热温度180℃～280℃进行回流，则在涂覆膜10的开口部11内的配线7的焊接区7b上表面处，以平面圆形形状而形成圆顶状的锡扩散抑制层12。此时，焊料膏层12b中的焊剂蒸发，且仅焊料膏层12b中的锡粒子熔融，熔点高的铜粒子未熔融。接着，铜粒子与熔融后的锡反应，生成铜锡合金(Cu6Sn5)。结果，锡扩散抑制层12变为铜锡合金、锡及铜混合存在的结构，之后，即便以加热温度180℃～280℃进行加热也不发生再熔融。
这里，作为一例，配线7的厚度为5μm左右。配线7上的涂覆膜10的厚度为5μm～10μm。锡扩散抑制层12的最大高度可远远高于由无电解镀形成的不足5μm左右的镀膜的厚度而达到50μm左右。
接着，如图9所示，通过丝网印刷法将焊剂28印刷到锡扩散抑制层12上及其周围的涂覆膜10上，并在其上搭载焊球13a。此时，焊球13a通过下述非融点上升型的焊料形成，该非融点上升型焊料在后述的回流时，在180℃～280℃的加热温度下熔融并固化，之后，在相同的180℃～280℃的加热温度下发生再熔融，具体来说，由共晶成分的锡银类无铅焊料形成。接着，若以加热温度180℃～280℃进行回流，则焊剂28蒸发且焊球13a熔融后固化，从而如图10所示，在锡扩散抑制层12上形成焊球13。
在这种情况下，锡扩散抑制层12在用于焊球13形成的回流时的、180℃～280℃的加热温度下不发生再熔融，维持圆顶形状的状态的原样。并且，焊球13也可以如下方式形成，即，首先在锡扩散抑制层12上通过丝网印刷法印刷焊料膏，接着通过以加热温度180℃～280℃进行回流。
接着，如图11所示，对半导体晶片21的下表面侧进行适当地研磨，使半导体晶片21的厚度变薄。接着，如图12所示，若沿着切割道切断涂覆膜10及半导体晶片21，则得到多个如图1及图2所示的半导体装置。
在如此得到的半导体装置中，由于在配线7的焊接区7b上形成锡扩散抑制层12，在该锡扩散抑制层12上形成焊球13，因此，即使该半导体装置为处理大电流的电源IC等，也由于锡扩散抑制层12的存在从而能够进一步抑制焊球13中的锡向其下的配线7的扩散。
并且，在该半导体装置中，圆顶状的锡扩散抑制层12的最大高度可远远高于由无电解镀形成的不足5μm左右的镀膜的厚度，，而达到例如50μm左右。结果，与锡扩散抑制层12呈圆顶状相结合，该最大高度能够相对变高，因此焊球13受到的应力能够在锡扩散抑制层12的高度方向上分散，焊球受到的应力进一步缓和。
另外，在上述半导体装置的制造方法中，在形成圆顶状的锡扩散抑制层12时，在配线7的焊接区7b上通过丝网印刷法印刷焊料膏12a并进行回流，因此，与采用阻镀剂膜的通过电解镀形成的情况相比，能够降低工序成本。
另外，在上述实施方式中，对通过熔点上升型的焊料膏形成锡扩散抑制层12的情况进行了说明，但不限于此。作为锡扩散抑制层12的材料，只要是在形成时的加热温度下不发生再熔融的金属膏即可，例如，可以通过丝网印刷法对在由热硬化性树脂等构成的膏中分散铜粒子而成的铜膏进行印刷，并以150℃左右的加热温度进行烧制，从而形成锡扩散抑制层12。并且，在上述实施方式中，对在配线7的焊接区7b上直接形成锡扩散抑制层12的情况进行了说明，但不限于此。例如，如图13所示，可以在配线7的焊接区7b上形成柱状电极(铜层)15，并在柱状电极15上形成锡扩散抑制层12。
(第二实施方式)
图14表示作为本发明的第2实施方式的半导体装置的平面图，图15表示大致沿图14的X IV-X IV线的部分的剖视图。该半导体装置一般称为CSP(chip size package)，具有平面方形的硅基板(半导体基板)1。在硅基板1的上表面形成有未图示但构成规定功能的集成电路的元件，例如，晶体管、二极管、电阻、电容等元件。在硅基板1的上表面的周边部设有，与上述集成电路的各元件连接的、由铝类金属等构成的多个连接焊盘2。
在去除硅基板1的周边部及连接焊盘2的中央部以外的硅基板1的上表面，设有由氧化硅等构成的钝化膜(绝缘膜)3，经由设于钝化膜3的开口部4使连接焊盘2的中央部露出。在钝化膜3的上表面设有由聚酰亚胺类树脂等构成的保护膜(绝缘膜)5。在与钝化膜3的开口部4相对应的部分的保护膜5处设有开口部6。
在保护膜5的上表面设有多个配线7。配线7形成为由基底金属层8与上部金属层9所构成的2层结构，该基底金属层8设置于保护膜5的上表面的铜等构成，该上部金属层9由设置于基底金属层8的上表面的铜构成。配线7的一端部经由钝化膜3及保护膜5的开口部4、6而连接于连接焊盘2。
这里，如图14所示，配线7由连接于连接焊盘2的端部7a、成为后述柱状电极(铜层)15的底座的平面圆形的焊接区7b、以及在两者间的引线部7c组成。并且，配线7的焊接区7b以矩阵状配置于保护膜5的上表面。
在配线7的焊接区7b上表面依次设有，平面圆形的由铜构成的柱状电极15、由镍构成的锡扩散抑制层12及由焊料构成的氧化抑制层16。在硅基板1的周边部上表面及包括配线7的保护膜5的上表面、柱状电极15、锡扩散抑制层12及氧化抑制层16的周围，设有包含二氧化硅填充物的由环氧类树脂构成的密封膜17。这里，氧化抑制层16设置为，其上表面与密封膜17的上表面共面或低于密封膜17的上表面1～2μm。在氧化抑制层16的上表面设有焊球13。
接着，对该半导体装置的制造方法的一例进行说明。首先，如图3所示进行准备，在晶片状态的硅基板(下面，称为半导体晶片21)的上表面形成由铝类金属等构成的多个连接焊盘2、由氧化硅等构成的钝化膜3及由聚酰亚胺类树脂等构成的保护膜5，并经由钝化膜3及保护膜5的开口部4、6使连接焊盘2的中央部露出。
此时，半导体晶片21的厚度比图15所示的硅基板1的厚度更厚。另外，在图16中，由符号22所示的区域为切割道。之后，将与切割道22及其两侧对应的部分的钝化膜3及保护膜5去除。
接着，如图17所示，在包括经由钝化膜3及保护膜5的开口部4、6而露出的连接焊盘2的上表面的、保护膜5的上表面，以及与切割道22及其两侧对应的部分的半导体晶片21的上表面，形成基底金属层8。此时，基底金属层8可以仅是通过无电解镀形成的铜层，也可以仅是通过溅射形成的铜层，还可以是在通过溅射形成的钛等薄膜层上通过溅射形成铜层的金属层。
接着，在基底金属层8的上表面，图案形成由正型的液状抗蚀剂构成的阻镀剂膜23。此时，在与上部金属层9形成区域相对应的部分的阻镀剂膜23处形成有开口部24。接着，若进行将基底金属层8作为镀电流通路的铜电解镀，则在阻镀剂膜23的开口部24内的基底金属层8的上表面，形成上部金属层9。接着，剥离阻镀剂膜23。
接着，如图18所示，在包含上部金属层9的基底金属层8的上表面，图案形成由负型的干膜抗蚀剂构成的阻镀剂膜29。此时，在与上部金属层9的焊接区7b(柱状电极15等形成区域)相对应的部分的阻镀剂膜29处形成有开口部26。接着，若对基底金属层8作为镀电流通路的铜、镍及焊料以该顺序连续地进行电解镀，则在阻镀剂膜29的开口部26内的上部金属层9的焊接区7b上表面处，依次形成柱状电极(铜层)15、锡扩散抑制层12及氧化抑制层16。
柱状电极15用于在印刷配线板(未图示)上对图14所示的半导体装置进行了安装的状态下缓和应力，其高度例如为100μm。锡扩散抑制层12由镍构成，用于抑制向由铜构成的柱状电极15的锡的扩散，其厚度比通过无电解镀形成的情况厚，例如为5～10μm。氧化抑制层16由焊料构成，用于防止锡扩散抑制层12的氧化，其厚度为例如10μm以上。在这种情况下，由于通过后工序对氧化抑制层16的上表面侧进行研磨，因此氧化抑制层16的厚度一定程度上比图14所示的氧化抑制层16的厚度更厚。这里，若取代氧化抑制层16而形成金层，则采用比较高价的金并在后工序中对其上面侧进行研磨，从而成本变高，但像本发明这样，若形成由价格比较低廉的焊料所构成的氧化抑制层16，则能够降低成本。
接着，剥离阻镀剂膜29，之后，若将上部金属层9作为掩模而对除了该上部金属层9下以外的区域的基底金属层8进行刻蚀并去除，则如图19所示，只有上部金属层9下残留有基底金属层8。在该状态下，通过上部金属层9及其下残留的基底金属层8形成2层结构的配线7。
接着，如图20所示，在切割道22及其两侧的半导体晶片21的上表面、以及包括配线7及氧化抑制层16的保护膜5的上表面，通过压模(compression mold)法、印刷法等形成含有二氧化硅填充物的由环氧类树脂构成的密封膜17，并使其厚度比氧化抑制层16的高度稍厚。因此，在该状态下，氧化抑制层16的上表面由密封膜17覆盖。
接着，对密封膜17及氧化抑制层16的上表面侧进行适当地研磨，如图21所示，使氧化抑制层16的上表面露出，并且使包含该露出的氧化抑制层16的上表面的密封膜17的上表面平坦化。这里，在上部金属层9的焊接区7b上表面仅形成了由铜构成的柱状电极15的情况下，由于会对柱状电极15的上表面侧进行研磨，因此若在柱状电极15的周围的密封膜17的上表面附着有铜的研磨碎屑，则需要通过光刻蚀(light etching)等对该附着的研磨碎屑进行去除的工序。对此，通过研磨氧化抑制层16的上表面侧，即使在氧化抑制层16的周围的密封膜17的上表面附着了焊料的研磨碎屑，也可如后所述而不需要去除该附着的研磨碎屑。
接着，如图22所示，在氧化抑制层16的上表面形成焊球13。作为焊球13的形成方法，首先，在氧化抑制层16的上表面涂布焊料膏或搭载焊球。接着通过进行回流，在氧化抑制层16的上表面形成焊球13。在该情况下，即使在氧化抑制层16的周围的密封膜17的上表面附着有焊料的研磨碎屑，由于该附着的研磨碎屑在进行回流时熔融而与焊球13或氧化抑制层16成为一体，因此如上所述，不需要去除附着的研磨碎屑。
接着，如图23所示，对半导体晶片21的下表面侧进行适当地研磨而使半导体晶片21的厚度变薄。接着，如图24所示，若沿着切割道22对密封膜17及半导体晶片21进行切断，则得到多个图13及图15所示的半导体装置。
在如此得到的半导体装置中，由于通过电解镀形成用于抑制包含氧化抑制层16的焊球13中的锡向柱状电极15扩散的锡扩散抑制层12，因此与通过无电解镀而形成的情况相比，可使锡扩散抑制层12的厚度变厚。结果，即使该半导体装置为处理大电流的电源IC等，也能够进一步抑制包含氧化抑制层16的焊球13中的锡向柱状电极15扩散。
(第3实施方式)
图25表示作为本发明的第2实施方式的半导体装置的剖视图。在该半导体装置中，与图15所示的半导体装置的不同点在于，柱状电极(铜层)15的高度降低为例如几μm的程度。在该情况下，可以在最初通过旋涂法等、利用聚酰亚胺类树脂等而使密封膜(涂覆膜)17覆盖氧化抑制层16的上表面。因此，该情况下，也对密封膜17及氧化抑制层16的上表面侧进行适当地研磨从而使氧化抑制层16的上表面露出。
(第4实施方式)
图26表示作为本发明的第3实施方式的半导体装置的剖视图。在该半导体装置中，与图15所示的半导体装置的不同点在于，省略了柱状电极15。该情况下，锡扩散抑制层12的作用在于，抑制包含氧化抑制层16的焊球13中的锡向由铜构成的配线7的扩散。并且，该情况下，也可以在最初通过旋涂法等、利用聚酰亚胺类树脂等而使密封膜(涂覆膜)17覆盖氧化抑制层16的上表面。因此，该情况下，也对密封膜17及氧化抑制层16的上表面侧进行适当地研磨从而使氧化抑制层16的上表面露出。

Claims (30)

1.一种半导体装置，其特征在于，具备：
半导体基板，具有连接焊盘；
配线，连接于所述连接焊盘；
锡扩散抑制层，含有焊料，设置于所述配线的上方；和
焊料凸块，设置于所述锡扩散抑制层上，
所述锡扩散抑制层的熔点比所述焊料凸块的熔点高。
2.根据权利要求1所述的半导体装置，其特征在于，
所述配线设置于绝缘膜上，
所述半导体装置具备涂覆膜，该涂覆膜设置于所述配线上及所述绝缘膜上，并在与所述配线的焊接区相对应的部分具有开口部。
3.根据权利要求1所述的半导体装置，其特征在于，
所述锡扩散抑制层以180℃～280℃进行加热而形成，并且在180℃～280℃不发生再熔融。
4.根据权利要求1所述的半导体装置，其特征在于，
所述锡扩散抑制层为熔点上升型的焊料。
5.根据权利要求4所述的半导体装置，其特征在于，
所述熔点上升型的焊料包含非共晶成分的锡铜类无铅焊料。
6.根据权利要求1所述的半导体装置，其特征在于，
所述锡扩散抑制层包含在热硬化性树脂中分散有铜粒子的层。
7.根据权利要求1所述的半导体装置，其特征在于，
所述焊料凸块包含非熔点上升型的焊料。
8.根据权利要求7所述的半导体装置，其特征在于，
所述非熔点上升型的焊料包含共晶成分的锡银类无铅焊料。
9.根据权利要求1所述的半导体装置，其特征在于，
在所述配线的焊接区上的所述锡扩散抑制层下设有铜层。
10.一种半导体装置，其特征在于，具备：
半导体基板，具有连接焊盘；
配线，连接于所述连接焊盘；
锡扩散抑制层，设置于所述配线的上方；
氧化抑制层，设置于所述锡扩散抑制层上；和
焊料凸块，搭载于所覆盖的所述氧化抑制层上，
所述氧化抑制层在搭载所述焊料凸块前被覆膜。
11.根据权利要求10所述的半导体装置，其特征在于，
在所述配线的焊接区的上方的所述锡扩散抑制层下设有铜层。
12.根据权利要求10所述的半导体装置，其特征在于，
所述配线设置于绝缘膜上，
在所述锡扩散抑制层及所述氧化抑制层的周围的所述绝缘膜上设有密封膜。
13.根据权利要求10所述的半导体装置，其特征在于，
所述锡扩散抑制层的厚度为5μm～10μm。
14.根据权利要求10所述的半导体装置，其特征在于，
所述锡扩散抑制层含有镍，所述氧化抑制层含有焊料。
15.一种半导体装置的制造方法，其特征在于，包含如下步骤：
在形成有配线的半导体基板的所述配线的上方，以规定的温度进行加热，形成在所述规定温度下不发生再熔融的锡扩散抑制层；
在所述锡扩散抑制层上形成焊料凸块。
16.根据权利要求15所述的半导体装置的制造方法，其特征在于，
所述配线形成于绝缘膜上，
在所述配线上及所述绝缘膜上，形成在与所述配线的焊接区相对应的部分具有开口部的涂覆膜。
17.根据权利要求15所述的半导体装置的制造方法，其特征在于，
所述规定的温度为180℃～280℃。
18.根据权利要求15所述的半导体装置的制造方法，其特征在于，
所述锡扩散抑制层通过印刷金属膏来形成金属膏层、并对金属膏层进行加热而形成。
19.根据权利要求18所述的半导体装置的制造方法，其特征在于，
所述金属膏包含熔点上升型的焊料膏。
20.根据权利要求19所述的半导体装置的制造方法，其特征在于，
所述熔点上升型的焊料膏包含非共晶成分的锡铜类无铅焊料膏。
21.根据权利要求15所述的半导体装置的制造方法，其特征在于，
所述金属膏包含铜膏。
22.根据权利要求20所述的半导体装置的制造方法，其特征在于，
所述铜膏包含在热硬化性树脂中分散有铜粒子的膏。
23.根据权利要求15所述的半导体装置的制造方法，其特征在于，
所述焊料凸块通过非熔点上升型的焊料膏而形成。
24.根据权利要求23所述的半导体装置的制造方法，其特征在于，
所述非熔点上升型的焊料膏包含共晶成分的锡银类无铅焊料膏。
25.一种半导体装置的制造方法，其特征在于，包含如下步骤：
在半导体基板的上方形成的配线用上部金属层的焊接区的上方，形成锡扩散抑制层；
在所述锡扩散抑制层上形成抑制该锡扩散抑制层的氧化的氧化抑制层；和
在所述氧化抑制层上形成焊料凸块。
26.根据权利要求25所述的半导体装置的制造方法，其特征在于，
在所述半导体基板上形成绝缘膜，在所述绝缘膜上形成基底金属层，
在所述基底金属层上通过电解镀形成所述配线用上部金属层，
在所述配线用上部金属层的所述焊接区的上方，通过电解镀而按顺序连续地形成所述锡扩散抑制层及所述氧化抑制层，
在所述氧化抑制层上形成所述焊料凸块。
27.根据权利要求25所述的半导体装置的制造方法，其特征在于，
在所述配线用上部金属层的所述焊接区的上方的所述锡扩散抑制层下，形成铜层。
28.根据权利要求25所述的半导体装置的制造方法，其特征在于，
在所述锡扩散抑制层及所述氧化抑制层的周围的所述配线上及所述绝缘膜上，形成密封膜。
29.根据权利要求25所述的半导体装置的制造方法，其特征在于，
所述锡扩散抑制层含有镍，所述氧化抑制层含有焊料。
30.根据权利要求28所述的半导体装置的制造方法，其特征在于，
形成所述密封膜的工序为如下工序：以覆盖所述氧化抑制层的上表面的方式形成所述密封膜，并研磨所述密封膜及所述氧化抑制层的上表面侧而使所述氧化抑制层的上表面露出。
CN201110070548XA 2010-03-23 2011-03-23 设有锡扩散抑制层的半导体装置及其制造方法 Pending CN102201389A (zh)

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