JP5299458B2 - 半導体装置および半導体装置ユニット - Google Patents
半導体装置および半導体装置ユニット Download PDFInfo
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- JP5299458B2 JP5299458B2 JP2011064513A JP2011064513A JP5299458B2 JP 5299458 B2 JP5299458 B2 JP 5299458B2 JP 2011064513 A JP2011064513 A JP 2011064513A JP 2011064513 A JP2011064513 A JP 2011064513A JP 5299458 B2 JP5299458 B2 JP 5299458B2
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- semiconductor device
- layer
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Description
図12(a)に示すように、Si基板200の片面に、電極パッド202が形成されている。また、Si基板200および電極パッド202の周縁部を覆うように、窒化ケイ素(Si3N4)からなる保護膜204が形成されており、保護膜204から露出している電極パッド202表面および保護膜204の開口周縁部にかけてアンダーバリアメタル(UBM)からなる金属層206が形成されている。そして、金属層206にはバンプ208が接合されている。
すなわち、金属層の表面にフラックスを塗布した後、当該塗布面に、バンプ材料として、例えば、Sn−Ag系鉛フリー半田材からなるはんだボールを載せ、リフローによりはんだボールの一部を溶融することによりなされる。
本発明の目的は、上記した課題に鑑み、金属層からバンプが大きくはみ出すことを可能な限り防止できる構成を備えた半導体装置を提供することにある。また、そのような半導体装置を有する半導体装置ユニットを提供することにある。
<第1実施形態>
図1(a)は第1実施形態に係る半導体装置10の斜視図であり、図1(b)は同平面図である。半導体装置10はCSPタイプの半導体パッケージである。
図2に示すように、基板12の主表面には、不図示の層間絶縁膜を介して、電極パッド20が形成されている。電極パッド20は、例えば、アルミニウム(Al)からなる。なお、前記層間絶縁膜(不図示)は、基板12の片側主表面全面に形成されている。
ダイシング前のウェハー1012(工程A)の片面に保護膜14(図1)となる窒化ケイ素膜1014を形成する。窒化ケイ素膜1014は、CMP(Chemical and Mechanical Polishing)を用いて平坦化される(工程B)。
そして、熱リン酸(H3PO4)などの薬液を用いたウェットエッチング法により、窒化ケイ素膜1014の一部をエッチングして、貫通孔16を形成する(工程D)。このとき、エッチングは等方的に進行するため、サイドエッチング効果により貫通孔16の内壁22は、貫通孔16の外側に向って傾いた斜面22に形成される。斜面22の電極パッド20に対する傾斜角αの大きさは、例えば、開口径の異なる複数のマスク材を順次適用すること等によって調整することができる。
<第2実施形態>
図5に、第2実施形態に係る半導体装置のバンプを含む位置で切断した一部断面図を示す。図5(a)は、第2実施形態の第1実施例に係る半導体装置26を、図5(b)は第2実施例に係る半導体装置28を、図5(c)は第3実施例に係る半導体装置30をそれぞれ示している。
<第3実施形態>
図6に、第3実施形態に係る半導体装置のバンプを含む位置で切断した一部断面図を示す。図6(a)は、第3実施形態の第1実施例に係る半導体装置42を、図6(b)は第2実施例に係る半導体装置44を、図6(c)は第3実施例に係る半導体装置48を、図6(d)は第4実施例に係る半導体装置47をそれぞれ示している。
<第4実施形態>
図7に、第4実施形態に係る半導体装置のバンプを含む位置で切断した一部断面図を示す。図7(a)は、第4実施形態の第1実施例に係る半導体装置54を、図7(b)は第2実施例に係る半導体装置56を、図7(c)は第3実施例に係る半導体装置58をそれぞれ示している。
第4実施形態の第1〜第3実施例に係る半導体装置54,56,58は、第2実施形態の第1〜第3実施例に係る半導体装置26,28,30とは、保護膜の構成が異なる以外は基本的に同じである。よって、図7において図5と同様の構成部分には同じ符号を付してその説明については省略し、異なる部分を中心に説明する。
保護膜60に開設された貫通孔66の内壁は、第1層62部分と第2層64部分とでその傾斜角を異にしており、第1層62部分よりも第2層64部分の傾斜角の方が大きく(傾斜が急に)なっている。
ここで、このような2層構造の保護膜60を有する半導体装置の製造方法について、半導体装置58(図7(c))を例にとり説明する。
次に、バンプ材料が設けられた基板12を熱処理して、バンプ材料を溶融することによりバンプ材料を金属層24と接合する。上記プロセスにおいて、金属層24の上に印刷したフラックスは、バンプ材料の保持及び再溶解(リフロー)時における酸化膜の除去といった2つの機能を主に有する。このため、フラックスは、ロジン系又は水溶性フラックス等を用いることができ、特にハロゲンフリータイプのロジン系フラックスを用いることが好ましい。
<第5実施形態>
図8に、第5実施形態に係る半導体装置のバンプを含む位置で切断した一部断面図を示す。図8(a)は、第5実施形態の第1実施例に係る半導体装置68を、図8(b)は第2実施例に係る半導体装置70を、図8(c)は第3実施例に係る半導体装置72をそれぞれ示している。
<第6実施形態>
図9に、第6実施形態に係る半導体装置のバンプを含む位置で切断した一部断面図を示す。図9(a)は、第6実施形態の第1実施例に係る半導体装置80を、図9(b)は第2実施例に係る半導体装置82を、図9(c)は第3実施例に係る半導体装置84をそれぞれ示している。
<第7実施形態>
図10は、第3実施形態(図6)で用いるバンプ18の形状の変形例を示している。図10(a)、図10(b)、図10(c)に符号「88」で指し示すのは、リフロー後のバンプの形状である。なお、バンプ形状以外の構成は、第3実施形態の第1〜第3実施例42,44,46と同様の構成である。よって、図10において図6と同様の構成部分については、同じ符号を付し、その説明については省略する。
<第8実施形態>
図11は、半導体装置28(図5(b))が実装基板90に実装されてなる半導体装置ユニット92の一部断面図である。図11は、バンプ18の存する位置で切断した図である。
12 基板
14,32,38,48,60,72 保護膜
16,34,50,66 貫通孔
18 バンプ
20 電極パッド
22,36,52 内壁(斜面)
24,40,86 金属層
62 第1層
64,76 第2層
Claims (5)
- 基板と、
前記基板上に形成された複数の電極パッドと、
各電極パッドに対応して開設された貫通孔を有し、電極パッドの周縁部および前記基板を覆うように形成された保護膜と、
を備え、
前記貫通孔の内壁は、当該貫通孔の外側に向って傾いた斜面に形成されており、
前記電極パッドの、前記貫通孔を介して前記保護膜から露出された露出面および前記貫通孔の前記斜面の中程にかけて金属層が形成されていて、
当該金属層にバンプが接合されており、
前記保護膜は、前記基板側から第1層、第2層の順に積層された2層構造を有し、
前記金属層の周縁が前記第1層の厚み方向中程に在ることを特徴とする半導体装置。 - 前記第2層に対応する前記斜面部分の前記電極パッドに対する傾斜角が、前記第1層に対応する同傾斜角よりも大きいことを特徴とする請求項1に記載の半導体装置。
- 前記第1層の貫通孔部分の径よりも前記第2層の貫通孔部分の径の方が大きく、前記斜面が階段状に形成されていることを特徴とする請求項2に記載の半導体装置。
- 前記複数の電極パッドは、マトリックス状に配列されていることを特徴とする請求項1〜3のいずれか1項に記載の半導体装置。
- 実装基板に、請求項1〜4のいずれか1項に記載の半導体装置が実装された半導体装置ユニット。
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JP2006012952A (ja) | 2004-06-23 | 2006-01-12 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
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JP5194471B2 (ja) | 2007-02-06 | 2013-05-08 | パナソニック株式会社 | 半導体装置 |
JP2009064812A (ja) | 2007-09-04 | 2009-03-26 | Panasonic Corp | 半導体装置の電極構造およびその関連技術 |
US8309864B2 (en) | 2008-01-31 | 2012-11-13 | Sanyo Electric Co., Ltd. | Device mounting board and manufacturing method therefor, and semiconductor module |
US7868453B2 (en) * | 2008-02-15 | 2011-01-11 | International Business Machines Corporation | Solder interconnect pads with current spreading layers |
JP2011044496A (ja) * | 2009-08-19 | 2011-03-03 | Panasonic Corp | 半導体デバイス及びそれを用いた半導体装置 |
US8354750B2 (en) * | 2010-02-01 | 2013-01-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress buffer structures in a mounting structure of a semiconductor device |
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2011
- 2011-02-25 US US13/034,930 patent/US8492896B2/en not_active Expired - Fee Related
- 2011-03-04 CN CN2011100530536A patent/CN102254876A/zh active Pending
- 2011-03-23 JP JP2011064513A patent/JP5299458B2/ja not_active Expired - Fee Related
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JP2012009822A (ja) | 2012-01-12 |
US8492896B2 (en) | 2013-07-23 |
US20110285008A1 (en) | 2011-11-24 |
CN102254876A (zh) | 2011-11-23 |
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