JP5404513B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP5404513B2 JP5404513B2 JP2010096232A JP2010096232A JP5404513B2 JP 5404513 B2 JP5404513 B2 JP 5404513B2 JP 2010096232 A JP2010096232 A JP 2010096232A JP 2010096232 A JP2010096232 A JP 2010096232A JP 5404513 B2 JP5404513 B2 JP 5404513B2
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- Japan
- Prior art keywords
- solder
- substrate
- semiconductor
- conductive paste
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Description
図2〜図6は、実施の形態に係る半導体装置の製造方法を示す工程図である。
Claims (1)
- 電極パッドが上面に設けられた配線基板を用意する工程と、
前記電極パッドを被覆するように、前記配線基板の上面全体にはんだと絶縁樹脂とが混練された導電性ペーストを塗布する工程と、
前記電極パッドに対応する外部電極端子が設けられた半導体チップをフェイスダウンした状態で、前記外部電極端子に対応して設けられた、はんだバンプを介して前記導電性ペーストの上に搭載する工程と、
前記はんだが溶融する温度で加熱を行い、前記電極パッドと前記はんだバンプとを前記導電性ペーストに含まれるはんだで接合する工程と、
を備え、
前記導電性ペーストに含まれる絶縁樹脂で、前記電極パッドと前記はんだバンプとを接合するはんだを被覆させ、
前記配線基板を用意する工程は、
少なくとも1層の層間絶縁膜によって相互に接続された多層配線層を金属基板の上の所定領域に構築する工程と、
前記所定領域を挟んで対向する辺部分に前記金属基板が残るように前記金属基板を選択的に除去して、一対のスティフナーを形成するとともに、一対のスティフナーで挟まれた部分において前記多層配線層と電気的に接続された電極パッドを露出させる工程と、
を含むことを特徴とする半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010096232A JP5404513B2 (ja) | 2010-04-19 | 2010-04-19 | 半導体装置の製造方法 |
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Application Number | Priority Date | Filing Date | Title |
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JP2010096232A JP5404513B2 (ja) | 2010-04-19 | 2010-04-19 | 半導体装置の製造方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006222053A Division JP2008047710A (ja) | 2006-08-16 | 2006-08-16 | 半導体基板、半導体装置およびこれらの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010161419A JP2010161419A (ja) | 2010-07-22 |
JP5404513B2 true JP5404513B2 (ja) | 2014-02-05 |
Family
ID=42578292
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2010096232A Active JP5404513B2 (ja) | 2010-04-19 | 2010-04-19 | 半導体装置の製造方法 |
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JP (1) | JP5404513B2 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5587804B2 (ja) * | 2011-01-21 | 2014-09-10 | 日本特殊陶業株式会社 | 電子部品実装用配線基板の製造方法、電子部品実装用配線基板、及び電子部品付き配線基板の製造方法 |
JP2012164965A (ja) | 2011-01-21 | 2012-08-30 | Ngk Spark Plug Co Ltd | 配線基板及びその製造方法 |
KR102134933B1 (ko) | 2012-08-31 | 2020-07-16 | 소니 주식회사 | 배선 기판 및 배선 기판의 제조 방법 |
JP6032070B2 (ja) | 2013-03-13 | 2016-11-24 | ソニー株式会社 | 半導体装置、半導体装置の製造方法 |
WO2016016916A1 (ja) * | 2014-07-29 | 2016-02-04 | パナソニックIpマネジメント株式会社 | 半導体部品とそれを用いた半導体実装品、半導体実装品の製造方法 |
US9925612B2 (en) | 2014-07-29 | 2018-03-27 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor component, semiconductor-mounted product including the component, and method of producing the product |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11320176A (ja) * | 1998-05-18 | 1999-11-24 | Fujitsu Ltd | はんだペースト |
JP2002299378A (ja) * | 2001-03-30 | 2002-10-11 | Lintec Corp | 導電体付接着シート、半導体装置製造方法および半導体装置 |
JP4022139B2 (ja) * | 2002-12-25 | 2007-12-12 | 富士通株式会社 | 電子装置及び電子装置の実装方法及び電子装置の製造方法 |
JP4063240B2 (ja) * | 2004-04-21 | 2008-03-19 | 日本電気株式会社 | 半導体装置搭載基板とその製造方法、並びに半導体パッケージ |
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2010
- 2010-04-19 JP JP2010096232A patent/JP5404513B2/ja active Active
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JP2010161419A (ja) | 2010-07-22 |
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