JP2009010260A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2009010260A JP2009010260A JP2007171914A JP2007171914A JP2009010260A JP 2009010260 A JP2009010260 A JP 2009010260A JP 2007171914 A JP2007171914 A JP 2007171914A JP 2007171914 A JP2007171914 A JP 2007171914A JP 2009010260 A JP2009010260 A JP 2009010260A
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- insulating
- opening
- insulating portion
- conductive
- semiconductor device
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
【解決手段】本発明の半導体装置10は、一面に第一絶縁部12が形成された半導体基板11を有する。第一絶縁部12には、第一導電部13を覆う第二絶縁部14が重ねて配される。第二絶縁部14には第二導電部15が重ねて配される。第二絶縁部14には、第二導電部15を覆う第三絶縁部16が配される。互いに隣接する構造体17どうしの間には、第三開口部19が形成されている。この第三開口部19は、第三絶縁部16および第二絶縁部14を貫通し、第一絶縁部12を露呈させる。
【選択図】図1
Description
前記構造体のうち、隣接する位置にある少なくとも一組の構造体間には、前記第二絶縁部および前記第三絶縁部を貫通し、前記第一絶縁部を露呈させる第三開口部が配されてなることを特徴とする。
本発明の請求項2に記載の半導体装置は、請求項1において、前記第三開口部は、互いに隣接する位置にある前記構造体どうしの間の少なくとも一部を分離するように形成されることを特徴とする。
本発明の請求項3に記載の半導体装置は、請求項2において、前記半導体装置を上から見たときに、前記構造体が前記端子を取り巻く独立した島状を成すように前記第三開口部が形成されることを特徴とする。
本発明の請求項4に記載の半導体装置は、請求項1において、隣接する前記構造体どうしは互いに繋がり、かつ前記構造体間に配された前記第三開口部どうしは互いに独立して形成されることを特徴とする。
本発明の請求項5に記載の半導体装置は、一面が第一絶縁部で覆われた半導体基板と、前記半導体基板の一面に配された第一導電部、前記第一絶縁部に重ねて配され、前記第一導電部を露呈させる第一開口部を有する第二絶縁部、前記第二絶縁部に重ねて配され、前記第一開口部で前記第一導電部に電気的に接続される第二導電部、前記第二導電部に重ねて配され、前記第二導電部の一部を露呈させる第二開口部を有する第三絶縁部、及び前記第二開口部に配された端子からなる構造体を、前記半導体基板上に複数個備えた半導体装置であって、
前記構造体のうち、隣接する位置にある少なくとも一組の構造体間には、前記第二絶縁部を貫通し、前記第一絶縁部を露呈させる第三開口部を有し、
第三絶縁部は、隣接する位置にある少なくとも一組の構造体間で連なり、前記第三開口部を覆うことを特徴とする。
Claims (5)
- 一面が第一絶縁部で覆われた半導体基板と、前記半導体基板の一面に配された第一導電部、前記第一絶縁部に重ねて配され、前記第一導電部を露呈させる第一開口部を有する第二絶縁部、前記第二絶縁部に重ねて配され、前記第一開口部で前記第一導電部に電気的に接続される第二導電部、前記第二導電部に重ねて配され、前記第二導電部の一部を露呈させる第二開口部を有する第三絶縁部、及び前記第二開口部に配された端子からなる構造体を、前記半導体基板上に複数個備えた半導体装置であって、
前記構造体のうち、隣接する位置にある少なくとも一組の構造体間には、前記第二絶縁部および前記第三絶縁部を貫通し、前記第一絶縁部を露呈させる第三開口部が配されてなることを特徴とする半導体装置。 - 前記第三開口部は、互いに隣接する位置にある前記構造体どうしの間の少なくとも一部を分離するように形成されることを特徴とする請求項1記載の半導体装置。
- 前記半導体装置を上から見たときに、前記構造体が前記端子を取り巻く独立した島状を成すように前記第三開口部が形成されることを特徴とする請求項2記載の半導体装置。
- 隣接する前記構造体どうしは互いに繋がり、かつ前記構造体間に配された前記第三開口部どうしは互いに独立して形成されることを特徴とする請求項1記載の半導体装置。
- 一面が第一絶縁部で覆われた半導体基板と、前記半導体基板の一面に配された第一導電部、前記第一絶縁部に重ねて配され、前記第一導電部を露呈させる第一開口部を有する第二絶縁部、前記第二絶縁部に重ねて配され、前記第一開口部で前記第一導電部に電気的に接続される第二導電部、前記第二導電部に重ねて配され、前記第二導電部の一部を露呈させる第二開口部を有する第三絶縁部、及び前記第二開口部に配された端子からなる構造体を、前記半導体基板上に複数個備えた半導体装置であって、
前記構造体のうち、隣接する位置にある少なくとも一組の構造体間には、前記第二絶縁部を貫通し、前記第一絶縁部を露呈させる第三開口部を有し、
第三絶縁部は、隣接する位置にある少なくとも一組の構造体間で連なり、前記第三開口部を覆うことを特徴とする半導体装置。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007171914A JP2009010260A (ja) | 2007-06-29 | 2007-06-29 | 半導体装置 |
TW097120912A TWI371811B (en) | 2007-06-29 | 2008-06-05 | Semiconductor device |
CN200810126820XA CN101335249B (zh) | 2007-06-29 | 2008-06-24 | 半导体器件 |
KR1020080060448A KR101014829B1 (ko) | 2007-06-29 | 2008-06-25 | 반도체 장치 |
US12/163,581 US7791187B2 (en) | 2007-06-29 | 2008-06-27 | Semiconductor device |
EP08159244A EP2009691A1 (en) | 2007-06-29 | 2008-06-27 | Semiconductor device |
US12/848,652 US7863719B2 (en) | 2007-06-29 | 2010-08-02 | Wafer level chip scale package |
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JP2007171914A JP2009010260A (ja) | 2007-06-29 | 2007-06-29 | 半導体装置 |
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JP2009010260A5 JP2009010260A5 (ja) | 2010-06-24 |
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US (2) | US7791187B2 (ja) |
EP (1) | EP2009691A1 (ja) |
JP (1) | JP2009010260A (ja) |
KR (1) | KR101014829B1 (ja) |
CN (1) | CN101335249B (ja) |
TW (1) | TWI371811B (ja) |
Cited By (3)
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JP2010278040A (ja) * | 2009-05-26 | 2010-12-09 | Renesas Electronics Corp | 半導体装置の製造方法および半導体装置 |
JP2013543272A (ja) * | 2010-11-01 | 2013-11-28 | 日本テキサス・インスツルメンツ株式会社 | Icデバイスのクラックアレストビア |
JP2022100276A (ja) * | 2020-12-23 | 2022-07-05 | エフェクト フォトニクス ベーハー | 環境保護されたフォトニック集積回路 |
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FR2939566B1 (fr) * | 2008-12-05 | 2011-03-11 | St Microelectronics Sa | Procede de realisation de plots exterieurs d'un dispositif semi-conducteur et dispositif semi-conducteur. |
CN101866905B (zh) * | 2009-04-16 | 2012-05-30 | 日月光半导体制造股份有限公司 | 基板结构及其制造方法 |
EP2330618A1 (en) * | 2009-12-04 | 2011-06-08 | STMicroelectronics (Grenoble 2) SAS | Rebuilt wafer assembly |
CN108075036B (zh) * | 2016-11-18 | 2021-08-13 | 旭化成微电子株式会社 | 霍尔元件以及霍尔元件的制造方法 |
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- 2008-06-27 EP EP08159244A patent/EP2009691A1/en not_active Withdrawn
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JP2004104103A (ja) * | 2002-08-21 | 2004-04-02 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
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JP2022100276A (ja) * | 2020-12-23 | 2022-07-05 | エフェクト フォトニクス ベーハー | 環境保護されたフォトニック集積回路 |
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US20080296762A1 (en) | 2008-12-04 |
CN101335249B (zh) | 2011-04-06 |
KR101014829B1 (ko) | 2011-02-15 |
TW200908177A (en) | 2009-02-16 |
TWI371811B (en) | 2012-09-01 |
EP2009691A1 (en) | 2008-12-31 |
CN101335249A (zh) | 2008-12-31 |
US7863719B2 (en) | 2011-01-04 |
US7791187B2 (en) | 2010-09-07 |
KR20090004557A (ko) | 2009-01-12 |
US20100295175A1 (en) | 2010-11-25 |
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