CN101335249A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN101335249A
CN101335249A CNA200810126820XA CN200810126820A CN101335249A CN 101335249 A CN101335249 A CN 101335249A CN A200810126820X A CNA200810126820X A CN A200810126820XA CN 200810126820 A CN200810126820 A CN 200810126820A CN 101335249 A CN101335249 A CN 101335249A
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mentioned
insulation division
peristome
conductive part
semiconductor substrate
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CNA200810126820XA
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CN101335249B (zh
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宗像浩次
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Fujikura Ltd
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Fujikura Ltd
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

本发明提供一种半导体器件，该半导体器件具有一面形成有第一绝缘部的半导体基板。在第一绝缘部上重叠配置有覆盖第一导电部的第二绝缘部。在第二绝缘部上重叠配置有第二导电部。在第二绝缘部上配置有覆盖第二导电部的第三绝缘部。构造体由第一导电部、第二绝缘部、第二导电部、第三绝缘部以及端子构成。在相互邻接的构造体彼此之间，形成有第三开口部。该第三开口部贯通第三绝缘部及第二绝缘部，使第一绝缘部露出。根据本发明，可提供防止了因绝缘层的伸缩而引起的基板弯曲、及绝缘层与基板脱离，并且，提高了端子间绝缘性的半导体器件。

Description

半导体器件
技术领域
本发明涉及半导体器件，例如涉及在不使用布线基板(interposer)等的晶片级CSP等中使用的半导体器件。
背景技术
在以往的半导体器件中，主流是例如，利用树脂来密封半导体芯片、在该密封后的树脂周围的侧面部配置金属导线的周围配置端子型。但是，在这种封装构造的情况下，封装体的面积比半导体芯片的面积大。因此，近年来，一种被称为CSP(芯片级封装体或芯片尺寸封装体)的封装体构造正在迅速普及。
这种CSP，采用在封装体的平坦表面上平面状配置电极的所谓球栅阵列(BGA)技术，以比以往小的面积在电子电路基板上高密度安装具有相同电极端子数的相同投影面积的半导体芯片。因此，这种CSP其封装面积基本等于半导体芯片的面积，所以能够对电子设备的小型、轻量化做出很大贡献。
这种CSP，是切断形成有电路的硅晶片、并针对切断了的各个半导体芯片个别地实施封装而完成的。另一方面，被称为晶片级CSP的封装体构造，在硅晶片上形成有绝缘层、二次布线层(导电层)、密封层、焊料凸起(端子)等。而且，在最后工序中将晶片切断为规定的芯片尺寸，从而使封装体的面积和半导体芯片的面积基本相等(例如，参照日本特开2004-207368号公报)
在这种构造的CSP中，在硅晶片等基板上，大致在整个区域形成绝缘层和密封层，保证二次布线层(导电层)的绝缘。但是，存在以下问题：这种绝缘层和密封层大多利用树脂等形成，固化时的收缩和发热所引起的伸缩，可能使其与基板之间产生应力，导致基板发生弯曲，或者绝缘层和密封层从基板上脱离。因此，在例如日本特开200-353716号公报所记载的发明中，记载了下述半导体器件：按照每个暴露在外部的端子(凸起)，在绝缘层和密封层上形成槽来进行划分，减小因绝缘层和密封层的伸缩而引起的基板弯曲。
但是，在日本特开2000-353716号公报所记载的半导体器件中，由于仅在绝缘层和密封层上形成了宽度较窄的槽，所以很难完全吸收绝缘层和密封层的伸缩，很难可靠地防止因绝缘层和密封层而引起的基板弯曲。此外，暴露在外部的端子(凸起)之间，由于仅以宽度较窄的槽进行划分，所以在高密度地配置端子时，端子之间也可能发生短路。
发明内容
本发明就是鉴于上述情况而做出的，目的是提供一种防止因绝缘层的伸缩而引起的基板弯曲、和绝缘层与基板脱离，并提高端子之间的绝缘性的半导体器件。
本发明的半导体器件具有半导体基板和构造体，半导体基板的一面被第一绝缘部覆盖，该构造体包括：第一导电部，配置在上述半导体基板的一面上；第二绝缘部，重叠配置在上述第一绝缘部上，具有使上述第一导电部露出的第一开口部；第二导电部，重叠配置在上述第二绝缘部上，通过上述第一开口部与上述第一导电部电连接；第三绝缘部，重叠配置在上述第二导电部上，具有使上述第二导电部的一部分露出的第二开口部；以及端子，配置在上述第二开口部上；在上述半导体基板上配置有多个上述构造体，上述构造体中的位于邻接位置的至少一组构造体之间，配置有第三开口部，该第三开口部贯通上述第二绝缘部和上述第三绝缘部，使上述第一绝缘部露出。
在本发明的半导体器件中，上述第三开口部最好形成为：使位于相互邻接位置的上述构造体之间的至少一部分分离。
在本发明的半导体器件中，上述第三开口部最好以下述方式形成：从上方观察上述半导体器件时，上述构造体呈包围上述端子的独立的岛状。
在本发明的半导体器件中，最好是，邻接的上述构造体彼此相连，并且配置在上述构造体之间的上述第三开口部相互独立地形成。
本发明的半导体器件，具有一面被第一绝缘部覆盖的半导体基板、和设置在上述半导体基板上的多个构造体，上述构造体具有：第一导电部，配置在上述半导体基板的一面上；第二绝缘部，重叠配置在上述第一绝缘部上，具有使上述第一导电部露出的第一开口部；第二导电部，重叠配置在上述第二绝缘部上，通过上述第一开口部与上述第一导电部电连接；第三绝缘部，重叠配置在上述第二导电部上，具有使上述第二导电部的一部分露出的第二开口部；以及端子，配置在上述第二开口部上；上述构造体中的位于邻接位置的至少一组构造体之间，具有第三开口部，该第三开口部贯通上述第二绝缘部，使上述第一绝缘部露出；第三绝缘部绵延在位于邻接位置的至少一组构造体之间，并覆盖上述第三开口部。
根据本发明的半导体器件，可以利用贯通第三绝缘部和第二绝缘部的第三开口部，来吸收由第三绝缘部和第二绝缘部的伸缩引起的应力。例如，在第三绝缘部和第二绝缘部的形成过程中，第三绝缘部和第二绝缘部的形成材料固化时，这种形成材料将发生收缩。特别是，当利用树脂来形成第三绝缘部和第二绝缘部时，固化过程中的收缩更明显。
该第三绝缘部和第二绝缘部收缩时，会在半导体基板与第三绝缘部及第二绝缘部之间产生很大的应力，使得半导体基板弯曲，当应力更大时，第三绝缘部和第二绝缘部还可能从半导体基板上脱离，造成半导体器件本身损坏。
但是，可以利用第三开口部来有效地缓和因第三绝缘部及第二绝缘部与半导体基板之间的伸缩率不同而产生的应力。特别是，这样的第三开口部贯通第三绝缘部和第二绝缘部，并且底部大到露出第一绝缘部的程度。因此，即使在第三绝缘部及第二绝缘部与半导体基板之间产生很大的应力，也能吸收这种大的应力，从而能有效地防止半导体基板弯曲、或者第三绝缘部及第二绝缘部从半导体基板脱离。
此外，通过在高密度排列的端子之间形成第三开口部，还可以防止因电流泄露而引起的端子间短路等电的异常导通。
附图说明
图1A是表示本发明的半导体器件的一个例子的俯视图。
图1B是表示本发明的半导体器件的一个例子的剖面图。
图2A是表示本发明的半导体器件的另一例子的俯视图。
图2B是表示本发明的半导体器件的另一例子的剖面图。
图3是表示本发明的半导体器件的另一例子的俯视图。
图4是表示本发明的半导体器件的另一例子的俯视图。
图5是表示本发明的半导体器件的另一例子的俯视图。
图6A是表示本发明的半导体器件的另一例子的俯视图。
图6B是表示本发明的半导体器件的另一例子的剖面图。
具体实施方式
以下，基于附图对本发明中的半导体器件的一实施方式进行说明。并且本发明并不限定于本实施方式。此外，为了容易了解本发明的特征，对于以下的说明中所使用的附图，有时出于方便而对作为要部的部分进行了放大显示，各构成要素的尺寸比例等不一定和实际相同。
图1A是作为本发明的半导体器件的一个例子的CSP型半导体器件的俯视图。此外，图1B是沿图1A所示的半导体器件的A-A线的剖面图。本发明的半导体器件10，具有一面形成有第一绝缘部(钝化(passivation)膜)12的半导体基板11。在半导体基板11的一部分上，形成有和形成于半导体基板11的集成电路(省略图示)等电连接的电极(以下称为第一导电部)13。此外，在第一绝缘部12上形成有使第一导电部13露出的电极开口部12a。
在第一绝缘部12上重叠配置有第二绝缘部14。该第二绝缘部14上形成有使第一导电部(电极)13的一部分露出的第一开口部14a。在第二绝缘部14上重叠配置有二次布线层(以下称为第二导电部)15。该第二导电部(二次布线层)15，经由第一开口部14a和第一导电部13电连接。
在第二绝缘部14上配置有覆盖第二导电部15的第三绝缘部(密封层)16。在该第三绝缘层16上形成有使第二导电部15的一部分露出的第二开口部16a。而且，在第二导电部15的因第二开口部16a而露出的部分上，配置有和第二导电部15电连接的端子(凸起)18。
在半导体基板11上，配置多个由这些上述第一导电部13、第二绝缘部14、第二导电部15、第二绝缘部16以及端子18构成的构造体17。在本实施方式中，这些构造体17相互连接地形成。
在位于相互邻接的位置上的一组构造体17、17之间，形成有第三开口部19。该第三开口部19贯通第三绝缘部16和第二绝缘部14，使第一绝缘部12露出。
根据这样构成的本发明的半导体器件10，可以利用贯通第三绝缘部16和第二绝缘部14的第三开口部19来减小因第三绝缘部16及第二绝缘部14的伸缩而引起的应力的影响。例如，在第三绝缘部16及第二绝缘部14的形成过程中，第三绝缘部16及第二绝缘部14的形成材料固化时，这种形成材料将发生收缩。特别是当利用树脂来形成第三绝缘部16及第二绝缘部14时，固化过程中的收缩更明显。
该第三绝缘部16及第二绝缘部14收缩时，会在半导体基板11与第三绝缘部16及第二绝缘部14之间产生很大的应力，使得半导体基板11弯曲，或者当应力更大时，还可能导致第三绝缘部16及第二绝缘部14从半导体基板11脱离，从而造成半导体器件10本身损坏。
但是，利用在相互连接的构造体17、17之间形成的第三开口部19，可以有效地缓和因这样的第三绝缘部16及第二绝缘部14与半导体基板11之间的伸缩率不同而产生的应力。特别是，这样的第三开口部19，贯通第三绝缘部16及第二绝缘部14，并且底部大到使第一绝缘部12露出的程度。因此，即使第三绝缘部16及第二绝缘部14与半导体基板11之间产生很大的应力，也难以受到该大应力的影响，能有效地防止半导体基板11弯曲、或者第三绝缘部16及第二绝缘部14从半导体基板11上脱离。
同样，在使用半导体器件10时发生温度变动的情况下，也会在伸缩率比较小的半导体基板11与伸缩率较大的第三绝缘部16及第二绝缘部14之间产生应力。不过，这种因使用环境的温度变动而引起的应力，也可以利用第三开口部19来有效地缓和，并可防止半导体基板11弯曲、或者第三绝缘部16及第二绝缘部14从半导体基板11上剥离。
此外，通过在构造体17、17之间形成第三开口部19，还可以防止因电流泄露而引起的端子18间的短路等电的异常导通。此外，利用第三开口部19，使形成有构成半导体电路的第一导电部13的第一绝缘部12露出，还可以有效地对第一导电部13附近产生的热量进行散热。
半导体基板11例如，最好使用硅晶片等半导体晶片。
此外，第一导电部13由铜、铝等导电材料构成。该第一导电部13的厚度，例如可以在0.3～1.5μm左右。覆盖半导体基板11的第一绝缘部(钝化膜)12例如，只要是在半导体基板11的整个一面上形成了SiN等的膜即可。
第二绝缘部14例如，可以使用聚酰亚胺、环氧树脂、硅树脂等绝缘性树脂。此外，这样的第二绝缘部14例如，可以利用旋涂法、层叠法、印刷法等形成。第二绝缘部14的厚度，例如可以在3～50μm左右。
第二导电部(二次布线层)15例如，由铜、铝、镍、金等导电材料构成。第二导电部15例如，可以利用电解电镀、非电解电镀等方法形成。此外，第二导电部15的厚度，例如可以在3～50μm左右。
第三绝缘部(密封层)16例如，可以使用聚酰亚胺、环氧树脂、硅树脂等绝缘性树脂。该第三绝缘部16例如，可以使用感光性的树脂，利用旋涂法、层叠法等形成。该第三绝缘部16的厚度，例如可以在3～150μm左右。
第三开口部19可以在形成了第三绝缘部16及第二绝缘部14之后，使用形似第三开口部19的抗蚀剂掩模、通过蚀刻来形成，或者，预先去除第三开口部19的轮廓部分来形成第三绝缘部16及第二绝缘部14。
图2A是表示本发明的半导体器件的另一例子的俯视图。此外，图2B是表示沿图2A所示的半导体器件的A-A线的剖面图。在本实施方式的半导体器件20中，第二导电部(二次布线层)25形成为：从配置在半导体基板21的周边附近的第一导电部(电极)23向半导体基板21的中央区域延伸。而且，在该第二导电部25的一端形成有端子(凸起)28。
由第一导电部23、第二绝缘部24、第二导电部25、第三绝缘部26以及端子28构成的构造体27，彼此相互分离地配置在半导体基板21上，在这些构造体27之间，形成有贯通第三绝缘部26及第二绝缘部24并使第一绝缘部(钝化膜)22露出的第三开口部29。该第三开口部29将各个构造体27划分为矩形。即，第三开口部29在构造上使位于相互邻接的位置上的构造体27彼此分离。
在这样的实施方式中，也形成划分各个构造体27并使第一绝缘部22露出的第三开口部29。由此，即使在伸缩率比较小的半导体基板21与伸缩率较大的第三绝缘部26及第二绝缘部24之间，因温度变动等而产生应力，也能利用第三开口部29来有效地缓和应力。因此，可有效地防止半导体基板21弯曲、或者第三绝缘部26及第二绝缘部24从半导体基板21上脱离。
另外，第三开口部也可以以包围端子(凸起)的方式来形成，形成由第一导电部、第二绝缘部、第二导电部、第三绝缘部以及端子构成的构造体。包围端子的第二绝缘部和第三绝缘部，可以是其一部分与邻接的第二绝缘部及第三绝缘部相连的结构(例如，参照图4)、和相互分离的结构(例如参照图3、图5)的任意一种。
由此，通过以残留第二绝缘部及第三绝缘部的方式形成第三开口部，第二绝缘部及第三绝缘部变得不连续，并且，可以抑制由在这些第二绝缘部及第三绝缘部产生的应力所引起的半导体基板弯曲。
作为第三开口部的形状，例如，也可以如图3所示，将由第一导电部、第二绝缘部、第二导电部、第三绝缘部以及端子构成的构造体37划分成岛状，使第一绝缘部(钝化膜)32在更宽的范围内露出，形成提高了缓和应力能力的第三开口部39。通过将构造体37划分成岛状，能将构造体37的面积做得比图2所示的半导体器件的构造体27更小。各个岛状构造体的拐角部分，最好为进行了倒角的形状、曲面形状等。由此，可以将在第二绝缘部及第三绝缘部产生的应力抑制得较小，能进一步提高缓和应力的能力。
并且，这些岛状的构造体37，不必都是形成为独立的，也可以以使构造体之间的至少一部分分离的方式来形成第三开口部39。由此，还可以做成端子之间的间隔仅一部分不同的半导体器件。
此外，也可以例如，如图4所示，由第一导电部、第二绝缘部、第二导电部、第三绝缘部以及端子构成的构造体47彼此连接，配置在这些构造体47之间的第三开口部49呈互不相连的独立的形状。在这种实施方式中，构造体47呈具有曲面的形状。通过将矩形构造体的拐角做成进行了倒角的形状、曲面状，能消除如图2所示的半导体器件的构造体27那样应力容易集中的锐角的拐角，能够防止因应力集中在特定部位而使半导体基板弯曲。
此外，也可以如图5所示，以包围各个端子(凸起)58的方式，将由第一导电部、第二绝缘部、第二导电部、第三绝缘部以及端子构成的构造体57，划分为比图3所示的实施方式更小的岛状。由此，可以加大第三开口部59，能够进一步提高第三开口部59缓和应力的能力。
图6A是作为本发明的半导体器件的另一例子的CSP型半导体器件的俯视图。此外，图6B是沿图6A所示的半导体器件的A-A线的剖面图。本发明的半导体器件60具有一面形成有第一绝缘部(钝化膜)62的半导体基板61。在半导体基板61的一部分上，形成有和形成于半导体基板61的集成电路(省略图示)等电连接的电极(以下称为第一导电部)63。此外，在第一绝缘部62上形成有使第一导电部63露出的电极开口部62a。
在第一绝缘部62上重叠配置有第二绝缘部64。在该第二绝缘部64上形成有使第一导电部(电极)63的一部分露出的第一开口部64a。在第二绝缘部64上重叠配置有二次布线层(以下称为第二导电部)65。该第二导电部(二次布线层)65，通过第一开口部64a与第一导电部63电连接。
在第二绝缘部64上，配置有覆盖第二导电部65的第三绝缘部(密封层)66。在该第三绝缘部66上形成有使第二导电部65的一部分露出的第二开口部66a。而且，在第二导电部65的因第二开口部66a而露出的部分上，配置有和第二导电部65电连接的端子(凸起)68。
在半导体基板61上，配置有多个由这些第一导电部63、第二绝缘部64、第二导电部65、第三绝缘部66以及端子68构成的构造体67。在本实施方式中，这些构造体67相互连接地形成。
在位于相互相邻的位置的一组构造体67、67之间，形成有第三开口部69。该第三开口部69贯通第二绝缘部64，使第一绝缘部62露出。而且，以覆盖该第三开口部69并使位于相互邻接位置的一组构造体67、67之间连接成一串的方式形成有第三绝缘部66。即，第三绝缘部66为扩展到多个构造体67、67的连通层。
通过做成这种结构，可以提高整个半导体器件60的绝缘性，并且，可以利用在上面侧使构造体67、67彼此相连(覆盖)的第三绝缘部66，来提高半导体器件60的强度。
以上，对本发明的优选实施例进行了说明，但是，本发明并不限于这些实施例。在不脱离本发明宗旨的范围内，可以进行结构的添加、省略、置换以及其他变更。本发明不受上述说明所限定，仅由所附权利要求的范围限定。

Claims (5)

1.一种半导体器件，具有半导体基板和构造体，该半导体基板的一面被第一绝缘部覆盖，该构造体包括：第一导电部，配置在上述半导体基板的一面上；第二绝缘部，重叠配置在上述第一绝缘部上，具有使上述第一导电部露出的第一开口部；第二导电部，重叠配置在上述第二绝缘部上，通过上述第一开口部与上述第一导电部电连接；第三绝缘部，重叠配置在上述第二导电部上，具有使上述第二导电部的一部分露出的第二开口部；以及端子，配置在上述第二开口部上；
在上述半导体基板上配置有多个上述构造体；
在上述构造体中的位于邻接位置的至少一组构造体之间，配置有第三开口部，该第三开口部贯通上述第二绝缘部和上述第三绝缘部，并使上述第一绝缘部露出。
2.根据权利所述1的半导体器件，其特征在于，
上述第三开口部形成为：使位于相互邻接位置的上述构造体之间的至少一部分分离。
3.根据权利要求2所述的半导体器件，其特征在于，
上述第三开口部以下述方式形成：从上方观察上述半导体器件时，上述构造体呈包围上述端子的独立的岛状。
4.根据权利要求1所述的半导体器件，其特征在于，
邻接的上述构造体彼此相连，并且配置在上述构造体之间的上述第三开口部相互独立地形成。
5.一种半导体器件，具有一面被第一绝缘部覆盖的半导体基板、和配置在上述半导体基板上的多个构造体；
上述构造体包括：第一导电部，配置在上述半导体基板的一面上；第二绝缘部，重叠配置在上述第一绝缘部上，具有使上述第一导电部露出的第一开口部；第二导电部，重叠配置在上述第二绝缘部部上，通过上述第一开口部与上述第一导电部电连接；第三绝缘部，重叠配置在上述第二导电部上，具有使上述第二导电部的一部分露出的第二开口部；以及端子，配置在上述第二开口部上；
在上述构造体中的位于邻接位置的至少一组构造体之间，配置有第三开口部，该第三开口部贯通上述第二绝缘部，使上述第一绝缘部露出；
第三绝缘部绵延在位于邻接位置的至少一组构造体之间，并覆盖上述第三开口部。
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