CN102104030A - 重构晶片的组装 - Google Patents

重构晶片的组装 Download PDF

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CN102104030A
CN102104030A CN2010105797093A CN201010579709A CN102104030A CN 102104030 A CN102104030 A CN 102104030A CN 2010105797093 A CN2010105797093 A CN 2010105797093A CN 201010579709 A CN201010579709 A CN 201010579709A CN 102104030 A CN102104030 A CN 102104030A
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electronic component
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朱利安·卫图
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STMicroelectronics Grenoble 2 SAS
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Abstract

本发明涉及重构晶片的组装，提供一种电子元件的封装件，其包括：电子元件(1)，其具有电路表面；树脂块(3)，其部分环绕所述电子元件；以及多层互连件(6)，其与所述电路表面接触，其中，所述多层互连件(6)连接到间距小于50μm的接合焊盘，所述树脂块(3)以注塑成型的树脂制成。

Description

重构晶片的组装
技术领域
本发明涉及用于电子元件的封装件，具体地但不排它地涉及半导体元件的封装件。
背景技术
很多元件以球栅阵列封装方式被封装，其中，在半导体的情况下，芯片(die)置于衬底上，衬底提供芯片上的接触点与外界之间的连接。
该衬底具有相关材料的成本以及约为200μm的最小厚度。
人们总是期望减小电子元件的尺寸并降低电子元件的成本。
在以下的描述以及附图中，相同元件由相同的附图标记指示。
图1以截面来表示根据球栅阵列(BGA)封装领域中的最近发展情况的封装件。
在封装好的电子元件1中，芯片2部分地被树脂块3包围。芯片2具有无树脂的有源表面4，并且在有源表面4上是接合焊盘5。多层互连件6包括介电层601、导电孔602以及导电轨道603，多层互连件6附连到有源表面3。典型地，钝化层604用于保护导电轨道603。
多层互连件6提供了接合焊盘5与锡球11之间的连接。锡球11可以由任何其它合适的连接(例如锡膏接合焊盘)所替代。为清楚起见，仅示出一层导电轨道603和导电孔602，但可以使用多层。
图1的封装件不再使用衬底，因而节省了相关成本。由于所述多层互连件远薄于等效衬底，因此封装高度减小。
期望提供一种用于制造这种封装的工艺流程，该封装相对于传统封装而言不会通过增加其它材料或处理步骤的成本而使得从材料成本的获益减少。还期望获得至少与传统封装同样多的引脚数量。
发明内容
在此描述的实施例通过提供一种电子元件封装件来解决这种需求，该电子元件封装件包括：电子元件，其具有电路表面；树脂块，其部分环绕所述电子元件；以及多层互连件，其与所述电路表面接触。所述多层互连件连接到间距小于50μm的多个接合焊盘，并且所述树脂块由注塑成型树脂制成。
根据实施例，所述多层互连件的厚度不大于30μm。
根据实施例，所述多层互连件是薄膜结构。
根据实施例，所述电子元件是半导体。
根据实施例，所述电子元件封装件具有锡球。
提供一种电子设备，其包括根据实施例的电子元件封装件。
还提供一种制造所述电子元件封装件的工艺，该工艺包括以下步骤：
提供第一多个电子元件，每个电子元件均具有有源表面，并保持在模制后的树脂块中并且置于第一载体上，
通过切割电子元件之间的树脂将多个电子元件分为各个单元，
移除所述第一载体，
将第二多个所述各个单元定位在第二载体上，以及
在第二多个有源表面上形成互连层。
根据实施例，在将多个电子元件分为各个单元的步骤之前，所述工艺还包括步骤：将第一介电层置于有源表面上。
根据实施例，在将多个电子元件分为各个单元的步骤之前，所述工艺还包括步骤：将籽晶层置于所述介电层上。
根据实施例，所述工艺使用第一载体，第一载体是与采用条带模制球栅阵列(strip-molding ball-grid array)封装的设备兼容的格式。
根据实施例，所述工艺使用第二载体，第二载体具有与硅晶片处理设备兼容的晶片的形式。
根据实施例，所述工艺使用第二载体，第二载体具有300mm晶片的形式。
根据实施例，形成互连层的工艺步骤使用薄膜技术。
根据实施例，所述工艺还包括步骤：形成部分覆盖互连层的钝化层。
附图说明
通过参照附图的说明以及不限于附图给出的实施例的以下详细描述，本发明的前述和其它目的、特征、方面和优点将变得清楚，其中：
图1表示电子元件封装件的截面；
图2表示用于制造类似于图1的封装件的组装流程；
图3a和图3b表示根据实施例的组装流程；
图4表示图3a所示的流程中使用的载体的平面图；
图5表示图3b所示的流程中使用的载体的平面图；以及
图6表示包括根据实施例的封装形式的电子元件的设备。
具体实施方式
在以下描述中，已经描述过的特征将不再进一步详细地描述。
图2以截面图的方式表示用于制造图1的封装的可能工艺流程。
在步骤S21中，芯片2通过有源表面4置于下方的载体20上。载体20具有类似于硅晶片的圆形形式，并且尺寸与硅晶片处理设备兼容。
在步骤S22中，通过涂覆液体树脂，然后使液体树脂压缩到载体20上的芯片2组，而形成覆盖所有芯片2的树脂块21。压缩的目的在于，施力于各芯片2之间的液体树脂，并且确保各个芯片2的满意的包封。接着，树脂变硬，并且类似于晶片形状的结构得以产生。
在步骤S23中，移除载体20，并且利用薄膜技术使多层互连件6形成在芯片2的有源表面4上。
如果需要，在此阶段锡球11被附连。多层互连件大约是20μm厚。如果使用更多的金属层，则厚度可以增加到30μm。
在步骤S24，各个组件分为多个单独的电子元件1。
树脂21在其变硬状态下具有与芯片以及载体不同的热膨胀系数。此外，当树脂21变硬时，其体积改变。这有两个结果：芯片2的相对位置以不可预测的方式改变，并且“晶片”势必翘曲。晶片越大，这些结果越严重。
该工艺的后续步骤(即多层互连件的薄膜沉积)具有光刻特性。它们使用暗示多个部件的位置的掩膜，部件已知进行了连接。此外，该工艺需要一定的平坦度。
这意味着，载体需要限制尺寸，进而意味着，批量尺寸减小，并且处理成本因此高于以其它方式的处理成本。
另一后果在于，可以在多层互连件6内形成的最小部件尺寸大于利用诸如薄膜的典型处理以其它方式可能形成的尺寸。重要的是，因为芯片2的各接合焊盘5的间距可能不比各多层互连件6的间距更小。因此，芯片2可能强制性地大于采用其它方式所需的尺寸，这不是期望的，因为芯片面积非常昂贵。
当前的工艺限制适于直径为200mm以及最小接合焊盘间距约为70μm的载体。
图3a以截面图来表示根据实施例的工艺流程的第一部分。
在步骤S31中，芯片2通过其有源表面4置于下方的第一载体30上。第一载体30具有粘接表面，从而将芯片2保持在适当位置。期望的是，粘接剂以更艰难地提供多层互连件6的附连的方式而不会污损有源表面4。还期望的是，稍后可以无困难地移除第一载体30。
在步骤S32中，通过注塑成型形成树脂块31，从而包封芯片2。可以使用对于球栅BGA处理来说常规的注塑成型工艺。介电层32被沉积。对此可能的技术可以是液体沉积的薄膜或旋涂。
介电层32形成多层互连件的第一部分。期望的是，介电层32是与将稍后用于实现多层互连件的薄膜技术兼容的材料。同样方便的是，在该位置沉积对于后续金属层所必须的任何籽晶层(未示出)。
在步骤S34，在各芯片2之间切割树脂块31和介电层32，以产生各个单独的处理单元33。可以使用例如锯切的传统切割技术。
图3b以截面图表示根据实施例的工艺流程的第二部分。
在步骤S35，各个部分被处理的单元33附连到第二载体34，此时，有源表面4和附连至有源表面4的介电层32与第二载体34间隔。第二载体34具有粘接表面，该粘接表面将各个单元33保持在合适的位置，同时允许稍后以满意方式移除这些单元。
介电层32的存在性有助于防止在转移过程期间对各个单独的处理单元33的损坏。
在步骤S36，使用薄膜技术实现多层互连件6。典型地，这将包括：在介电层中形成孔602，形成导电轨道603，以及形成钝化层604。可以添加锡球11(未示出)。如上所述，可以使用更多层的导电孔602、导电轨道603以及多个介电层32。
此后，从第二载体34移除各个完成的组件。
期望的是，以精确的设备来放置各个单元33，从而可以将后续薄膜处理的掩膜步骤以令人满意的程度对齐。放置越精确，由薄膜处理所限定的部件越小。例如，可能实现40μm的连接的接合焊盘的间距。
最小间距从70μm减少到40μm导致任何给定尺寸的芯片2的最大引脚数量的增加。
图4表示适用于参照图3a描述的工艺流程的第一部分的第一载体30的示例的平面图。第一载体30具有矩形形式，有利地与常规BGA处理设备兼容。芯片2置于多个基体40中，一个基体中的芯片数量由芯片2的尺寸确定。树脂块31在每个基体40上被模制。
图5表示适用于参照图3b描述的工艺流程的第二部分的第二载体34的示例的平面图。在第二载体34上，放置各个单独的处理单元33的矩阵50。构造51将称为“重构晶片”。
如果第二载体34具有圆形形状和硅晶片所需的标准尺寸，则有可能从与在用于形成多层互连件的晶片制造中所使用设备的相似的设备中获益。这种设备比传统封装设备更好地适于限定小的部件。
此外，因为重构晶片51是由分离单元构造而成的，而不是在其整个表面上都具有树脂，所以在很大程度上减少了与树脂的热膨胀和体积变化关联的问题。这意味着，重构晶片51很少翘曲，并且芯片位置不具有不可预测性。因此，可以使得重构晶片51变大并且在薄膜处理中限定更小的部件。
因此，批量尺寸增加，减少了工艺成本。实际上，300mm直径的重构晶片被认为是可能的，显著地改进了当今可能的200mm晶片。
图6表示包括印刷电路板60的设备的截面，在根据本发明的封装中多个电子元件1安装在该印刷电路板60上。该设备具有外壳61，该外壳61除了其它作用以外用于保护内部的电子装置。
前述内容仅以示例的方式给出，但绝不意图限制。实际上，流程的其它变型是可能的。例如，可以在与所示位置不同的位置沉积介电层32或籽晶层。而且，可以使用除了薄膜处理之外的技术来制造多层互连件6。
因此，已经描述了本发明的至少一个示意性实施例，对于本领域技术人员来说可以想到各种变更、修改和改进。这些变更、修改和改进意在本发明的精神和范围内。因此，前面的描述仅是作为示例，而非意在进行限制。本发明仅限于所附权利要求及其等同物所限定的内容。

Claims (14)

1.一种电子元件封装件，包括：
电子元件(1)，所述电子元件具有电路表面；
树脂块(3)，所述树脂块部分地包围所述电子元件；以及
多层互连件(6)，所述多层互连件与所述电路表面接触，
其中，所述多层互连件(6)连接到间距小于50μm的多个接合焊盘，并且所述树脂块(3)由注塑成型的树脂制成。
2.根据权利要求1所述的电子元件封装件，其中，所述多层互连件的厚度在20μm与30μm之间。
3.根据权利要求1所述的电子元件封装件，其中，所述多层互连件是薄膜结构。
4.根据权利要求1所述的电子元件封装件，其中，所述电子元件是半导体。
5.根据权利要求1所述的电子元件封装件，具有锡球(11)。
6.一种电子设备，包括根据权利要求1所述的电子元件封装件。
7.一种制造电子元件封装件的工艺，包括以下步骤：
提供第一多个电子元件(2)，每个所述电子元件均具有有源表面，并保持在模制的树脂块(31)中并且置于第一载体(20)上，
通过切割所述电子元件之间的树脂，将多个所述电子元件分为各个单元，
移除所述第一载体，
将第二多个所述各个单元定位在第二载体(30)上，以及
在所述第二多个各个单元的所述有源表面上形成互连层(32)。
8.根据权利要求7所述的工艺，还包括在将多个所述电子元件分为各个单元的步骤之前将第一介电层置于所述有源表面上的步骤。
9.根据权利要求8所述的工艺，还包括在将多个所述电子元件分为各个单元的步骤之前将籽晶层置于所述介电层上的步骤。
10.根据权利要求7所述的工艺，其中，所述第一载体是与用于条带模制球栅阵列封装件的设备兼容的格式。
11.根据权利要求7所述的工艺，其中，所述第二载体具有与硅晶片处理设备兼容的晶片的形式。
12.根据权利要求11所述的工艺，其中，所述第二载体具有300mm晶片的形式。
13.根据权利要求7所述的工艺，其中，形成互连层的步骤使用薄膜技术。
14.根据权利要求7所述的工艺，还包括步骤：形成部分地覆盖所述互连层的钝化层。
CN2010105797093A 2009-12-04 2010-12-06 重构晶片的组装 Pending CN102104030A (zh)

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