CN102169842A - 用于凹陷的半导体基底的技术和配置 - Google Patents

用于凹陷的半导体基底的技术和配置 Download PDF

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Publication number
CN102169842A
CN102169842A CN2011100388085A CN201110038808A CN102169842A CN 102169842 A CN102169842 A CN 102169842A CN 2011100388085 A CN2011100388085 A CN 2011100388085A CN 201110038808 A CN201110038808 A CN 201110038808A CN 102169842 A CN102169842 A CN 102169842A
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China
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semiconductor
based end
nude
redistributing layer
nude films
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Inventor
吴亚伯
陈若文
韩忠群
刘宪明
卫健群
常润滋
吴嘉洛
郑全成
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Marvell World Trade Ltd
Mawier International Trade Co Ltd
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Mawier International Trade Co Ltd
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Publication of CN102169842A publication Critical patent/CN102169842A/zh
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

本发明的实施方式涉及用于凹陷的半导体基底的技术和配置，具体地，提供了一种方法，包括：提供半导体基底，该半导体基底具有(i)第一表面和(ii)与第一表面相反地布置的第二表面；在半导体基底的第一表面上形成电介质膜；在电介质膜上形成再分布层；将一个或多个裸片电耦合到再分布层；在半导体基底上形成模塑料；使半导体基底的第二表面凹陷；形成通过半导体基底的凹陷的第二表面的一个或多个沟道以暴露再分布层；以及在该一个或多个沟道中形成一个或多个封装互连结构，该一个或多个封装互连结构电耦合到再分布层，该一个或多个封装互连结构用以路由该一个或多个裸片的电信号。可以描述和/或要求保护其他实施方式。

Description

用于凹陷的半导体基底的技术和配置
相关申请的交叉引用
本公开要求以下专利申请的优先权：2010年2月3日提交的美国临时专利申请No.61/301,125、2010年3月22日提交的美国临时专利申请No.61/316,282、2010年4月5日提交的美国临时专利申请No.61/321,068以及2010年4月16日提交的美国临时专利申请No.61/325,189，就各方面而言，在此通过引用的方式引入这些申请整个说明书的全部内容，除了可能存在的与本说明书不一致的那些部分。
技术领域
本公开的实施方式涉及集成电路领域，并且更特别地涉及用于封装组件的凹陷(recessed)半导体基底的技术、结构以及配置。
背景技术
在此出于一般地呈现本公开的上下文的目的而提供了背景技术描述。在该背景技术部分中所描述的当前署名的发明人的工作以及本说明书中的并未以其他方式被判定为申请日时的现有技术的各方面，均不表示明确地或隐含地被承认为相对于本公开的现有技术。
诸如晶体管的集成电路器件形成在其大小持续缩减为更小尺寸的裸片或芯片上。裸片的紧缩尺寸对当前用于路由去往或来自半导体裸片的电信号的传统基底制作和/或封装组件技术提出了挑战。例如，层压基底技术不能在基底上产生足够小的特征以对应于互连的更细微的节距，或者形成在裸片上的其他路由信号的特征。
发明内容
在一个实施方式中，本公开提供了一种方法，包括：提供半导体基底，该半导体基底具有(i)第一表面和(ii)与第一表面相反地布置的第二表面；在半导体基底的第一表面上形成电介质膜；在电介质膜上形成再分布层；将一个或多个裸片电耦合到再分布层；在半导体基底上形成模塑料(molding compound)；使半导体基底的第二表面凹陷；形成通过半导体基底的凹陷的第二表面的一个或多个沟道以暴露再分布层；以及在该一个或多个沟道中形成一个或多个封装互连结构，该一个或多个封装互连结构电耦合到再分布层，该一个或多个封装互连结构用以路由该一个或多个裸片的电信号。
在另一实施方式中，本公开提供了一种装置，包括：半导体基底，该半导体基底具有(i)第一表面和(ii)与第一表面相反地布置的第二表面；形成在半导体基底的第一表面上的电介质膜；形成在电介质膜上的再分布层；电耦合到再分布层的一个或多个裸片；形成在半导体基底上的模塑料；形成为通过半导体基底的第二表面的一个或多个沟道；以及布置在该一个或多个沟道中的一个或多个封装互连结构，该一个或多个封装互连结构通过该一个或多个沟道电耦合到再分布层以路由该一个或多个裸片的电信号。
附图说明
通过结合附图的以下详细描述，将很容易理解本公开的实施方式。为便于进行这一描述，类似的参考标号表示类似的结构性元件。这里的实施方式在附图的各图中以示例的方式而不是限制的方式示出。
图1示意性地示出包括凹陷的半导体基底的封装组件。
图2A-图2I示意性地示出在各种工艺操作之后的封装组件。
图3示意性地示出包括凹陷的半导体基底的另一封装组件。
图4是用以制作在此描述的封装组件的方法的处理流程图。
具体实施方式
本公开的实施方式描述了用于具有凹陷区域和相关联的封装组件的半导体基底的技术、结构以及配置。在以下详细描述中，参考了作为其一部分的附图，其中贯穿附图，类似的参考标号表示类似的部分。在不脱离本公开范围的情况下，可以利用其他实施方式，并且可以在结构上和逻辑上进行改变。因此，以下详细描述不应理解为限制性的，并且实施方式的范围由所附权利要求书及其等同形式限定。
本说明书可以使用基于透视的描述，诸如上/下、之上/之下，和/或顶部/底部。这种描述仅用于便于讨论，而并非旨在将在此描述的实施方式的应用限制为任何特定方向。
出于本公开的目的，短语“A/B”意思是A或B。出于本公开的目的，短语“A和/或B”意思是“(A)、(B)或者(A和B)”。出于本公开的目的，短语“A、B以及C中的至少一个”意思是“(A)、(B)、(C)、(A和B)、(A和C)、(B和C)、或者(A、B以及C)”。出于本公开的目的，短语“(A)B”意思是“(B)或(AB)”，也即，A是可选元素。
各种操作以最有助于理解所要求保护的主题的方式被描述为按次序的多个离散操作。然而，描述的顺序不应当理解为暗示这些操作必然是依赖于顺序的。特别地，这些操作可以不以所呈现的顺序执行。所描述的操作可以以与所描述的实施方式不同的顺序来执行。可以执行各种附加的操作和/或所描述的操作在附加实施方式中可以省略。
本说明书使用短语“在一个实施方式中”、“在实施方式中”或者类似的语言，其均可以指代一个或多个相同或不同的实施方式。另外，针对本公开的实施方式而使用的术语“包括”、“包含”、“具有”等是同义的。
图1示意性地示出包括凹陷的半导体基底的封装组件100。封装组件100一般地包括半导体基底102，该半导体基底102是基底或插入物，其实质上包括半导体材料，诸如硅(Si)。也即，半导体基底102的主要材料是半导体材料。半导体材料可以包括晶体和/或非晶类型的材料。在硅的情况下，例如，硅可以包括单晶体和/或多晶硅类型。在其他实施方式中，半导体基底102可以包括其他半导体材料，诸如锗、III-V族材料或者II-VI族材料，其也可以从在此描述的原理受益。
半导体基底102包括第一表面A1和与第一表面A1相反地布置的第二表面A2。第一表面A1和第二表面A2通常指代半导体基底102的相反表面，以便于描述在此描述的各种配置。
根据各种实施方式，第二表面A2的一部分是凹陷的，以提供厚度T，该厚度T便于通过半导体基底102而形成一个或者多个沟道104。在某些实施方式中，半导体基底102是凹陷的，以具有在大约10微米与500微米之间的厚度T。该厚度不限于这一范围，在其他实施方式中可以使用其他更大或者更小的两种厚度。
半导体基底102是使用与一般已知的用以在裸片或芯片上制作集成电路(IC)结构的那些技术类似的技术来制作的。例如，公知的用于在裸片上制作IC器件的图案化工艺，诸如光刻/蚀刻和/或沉积工艺，可以用于形成半导体基底102的特征。通过使用半导体制作技术，半导体基底102可以包括比诸如层压(例如有机)基底之类的其他类型的基底更小的特征。半导体基底102实现了对用于大小持续缩减的裸片的电信号，诸如输入/输出(I/O)和/或电源/接地信号的路由。例如，在某些实施方式中，半导体基底102允许在半导体基底102与一个或多个裸片108之间进行路由的最终线路和细微节距Si到Si互连。
电介质膜105形成在半导体基底的第一表面A1和/或第二表面A2上。电介质膜105可以包括例如二氧化硅(SiO2)、氮化硅(SiN)或者氮氧化硅(Si2N2O)，或者其他合适的电介质材料。电介质膜105一般地提供针对布置在半导体基底上的导电材料的电隔离，以防止半导体基底的半导体材料(例如，硅)与导电材料之间的电流泄漏。
一个或多个再分布层106形成在电介质膜105上，以路由一个或多个裸片108的电信号，该裸片108耦合到半导体基底102。例如一个或多个再分布层106可以提供一个或多个裸片108与布置在一个或多个沟道104中的一个或多个封装互连结构114之间的电路由。
一个或多个再分布层106一般地包括导电材料，诸如金属(例如，铜或铝)。在其他实施方式中，可以使用其他合适的导电材料来形成一个或多个再分布层106。
一个或多个再分布层106可以包括用以路由电信号的各种各样的结构，诸如焊盘、焊区或者迹线。尽管未示出，但可以将包括诸如聚酰亚胺之类的电绝缘材料的钝化层沉积在一个或多个再分布层106上，并且图案化为在钝化层中提供开口以允许一个或多个裸片108到一个或多个再分布层106的电耦合。
一个或多个裸片108耦合到半导体基底102。一个或多个裸片108一般地包括半导体材料，诸如硅。在一个实施方式中，一个或多个裸片108和半导体基底102是使用相同的半导体材料来制作的，以减少与材料的加热/冷却失配(诸如失配的热膨胀系数(CTE))相关联的应力。
一个或多个裸片108可以使用任何合适的配置耦合到半导体基底102。一个或多个裸片108一般地具有活性侧和非活性侧，活性侧包括如下表面，在该表面上形成了用于逻辑和/或存储器的多个集成电路(IC)器件(未示出)，诸如晶体管，并且非活性侧与活性侧相反地布置。一个或多个裸片108的活性侧电耦合到一个或多个再分布层106。
在某些实施方式中，一个或多个裸片108的活性侧使用一个或多个凸点110，以倒装芯片配置耦合到一个或多个再分布层106，正如可以看到的那样。在其他实施方式中，一个或多个裸片108的活性侧使用其他结构，诸如一个或多个键合引线来电耦合到一个或多个再分布层106以提供引线键合配置。
一个或多个凸点110一般地包括导电材料，诸如焊料或其他金属，以路由一个或多个裸片108的电信号。根据各种实施方式，一个或多个凸点110包括铅、金、锡、铜或无铅材料或者其组合。一个或多个凸点110可以具有各种各样的形状(包括球形、圆柱形、矩形或其他形状)，并且能够使用凸点工艺(诸如可控坍塌芯片连接(C4)工艺、柱形凸点成形(stud-bumping)或者其他合适的工艺)来形成。
尽管未示出，但可以在半导体基底102上安装一个或多个其他有源或无源部件。这些部件可以包括电子复合体和集成电路(IC)。这些部件可以包括例如滤波器元件、电阻器、电感器、功率放大器、电容器或者已封装的IC卡。在其他实施方式中，其他有源或无源部件可以耦合到半导体基底102。
模塑料112布置在半导体基底102的第一表面A1上。模塑料112一般地包括电绝缘材料，诸如热固性树脂，其布置以保护一个或多个裸片108不受到潮湿、氧化或者与处理相关联的破碎。在某些实施方式中，模塑料112布置为实质上封住一个或多个裸片108并且实质上充满一个或多个裸片108与半导体基底102之间(例如，一个或多个凸点110之间)的区域，正如可以看到的那样。可以将模塑料112选择为具有与半导体基底102和/或一个或多个裸片108的热膨胀系数(CTE)相同或实质上类似的CTE，以减少与失配的CTE材料相关联的应力。
根据各种实施方式，一个或多个沟道104，又称为通孔，形成为通过半导体基底102的凹陷表面(例如，第二表面A2)。一个或多个沟道104填充有导电材料和/或导热材料(诸如金属)以形成一个或多个封装互连结构114。一个或多个沟道104一般地提供半导体基底102的第一表面A1与第二表面A2之间的电通路和/或热通路。在半导体基底102包括硅的实施方式中，一个或多个沟道104是一个或多个硅贯通孔(through-silicon via，简写为TSV)。在某些实施方式中，一个或多个沟道104是锥形的。在其他实施方式中，一个或多个沟道104可以是直的或者具有其他形状。
一个或多个封装互连结构114，诸如一个或多个焊球或杆，布置在一个或多个沟道104中，以进一步路由一个或多个裸片108的电信号。一个或多个封装互连结构114通过一个或多个沟道104电耦合到一个或多个再分布层106。在图1所示的实施方式中，一个或多个封装互连结构114直接耦合到形成在半导体基底102的第一表面A1上的一个或多个再分布层106。
一个或多个封装互连结构114一般地包括导电材料，诸如金属。一个或多个封装互连结构114可以形成为各种各样的形状(包括球面、平面或者多边形形状)，并且可以定位在各种各样的位置(包括在一行中，或者在含多行的阵列中)。尽管在半导体基底102的周边部分示出了一个或多个封装互连结构114，但在其他实施方式中，一个或多个封装互连结构114可以布置在半导体基底102的中心部分或者靠近该中心部分。
封装组件100可以使用一个或多个封装互连结构114来电耦合到另一电子设备150，以进一步向其他电子设备150路由一个或多个裸片108的电信号。该其他电子设备150可以包括例如印刷电路板(PCB)(例如，主板)、模块或者另一封装组件。
图2A-图2I示意性地示出在各种工艺操作之后的封装组件。参考图2A，示出了在半导体基底102的至少第一表面A1上形成电介质膜105之后的封装组件200。在实施方式中，电介质膜105形成在半导体基底102的第一表面A1和第二表面A2上，正如可以看到的那样。电介质膜105可以通过使用沉积技术(诸如物理气相沉积(PVD)、化学气相沉积(CVD)和/或原子层沉积(ALD))来形成，以沉积电介质材料，诸如二氧化硅(SiO2)、氮化硅(SiN)或者氮氧化硅(Si2N2O)。在其他实施方式中，可以使用其他合适的沉积技术和/或电介质材料。
参考图2B，示出了在布置于第一表面A1上的电介质膜105上形成一个或多个再分布层106之后的封装组件200。一个或多个再分布层106一般地通过在电介质膜105上沉积导电材料而形成。可以对所沉积的导电材料进行图案化和/或蚀刻，以提供路由一个或多个裸片(例如，图2C的一个或多个裸片108)的电信号的路由结构(例如，迹线或焊盘)。可以将多个再分布层堆叠在半导体基底102上，以提供对电信号的期望路由。
参考图2C，示出了在将一个或多个裸片108电耦合到一个或多个再分布层106之后的封装组件200。一个或多个裸片108可以以各种各样的配置(例如，倒装芯片或引线键合配置，或者其组合)耦合到半导体基底102。在倒装芯片配置中，裸片的活性表面使用一个或者多个凸点110耦合到一个或多个再分布层106。在引线键合配置中，裸片的非活性表面使用粘合剂耦合到半导体基底102，裸片的活性表面使用一个或多个键合引线电耦合到一个或多个再分布层106。
在图2C所示的实施方式中，一个或多个凸点110形成在一个或多个裸片108上，并且以倒装芯片配置键合到一个或多个再分布层106。一个或多个凸点110可以使用凸点成形工艺(诸如可控坍塌芯片连接(C4)工艺、柱形凸点成形或者其他合适的工艺)来形成。当该一个或多个裸片108是晶片或单切的(singulated)形式时，一个或多个凸点110可以形成在一个或多个裸片108上。当半导体基底102是晶片或单切的形式时，一个或多个裸片108可以附接到半导体基底102。
参考图2D，示出了在半导体基底102上形成模塑料112之后的封装组件200。模塑料112一般地通过将电绝缘材料沉积为封住一个或多个裸片108而形成。根据各种实施方式，模塑料112通过将固体形式(例如，粉末)的树脂(例如，热固性树脂)沉积到模具中并施加热量和/或压力以熔化该树脂而形成。在其他实施方式中，可以使用其他公知的用于形成模塑料112的技术。
在某些实施方式中，模塑料112可以与底部填充层(例如，图3的底部填充物118)结合使用。例如，底部填充材料可以布置在一个或多个裸片108与半导体基底102之间，以封住一个或多个凸点110，并且模塑料112可以布置为封住一个或多个裸片108和底部填充物。在某些实施方式中，模塑料112可以形成为使得一个或多个裸片108的表面暴露，以便于从一个或多个裸片108散热。
参考图2E，示出了在使半导体基底102的第二表面A2凹陷之后的封装组件200。半导体基底102可以通过研磨工艺或蚀刻工艺被凹陷，以提供所具有的厚度在大约10微米与大约500微米之间的半导体基底102。在其他实施方式中，可以使用其他凹陷技术和厚度。半导体基底102是凹陷的以提供更薄的基底，该更薄的基底便于或使得能够形成完全通过半导体基底102的一个或多个沟道(例如，一个或多个沟道104)。根据各种实施方式，模塑料112用作机械载体以在半导体基底102的第二表面A2正在被凹陷时、和/或在执行结合图2H描述的动作时支撑半导体基底102。
参考图2F，示出了在形成通过半导体基底102的一个或多个沟道104之后的封装组件200。一个或多个沟道104形成为在半导体基底102的第二表面A2中/通过该半导体基底102的第二表面A2，以暴露电介质膜105，正如可以看到的那样。一个或多个沟道104可以通过选择性地移除半导体基底102的半导体材料而形成。例如，可以利用光刻胶膜或硬掩模而将半导体基底的第二表面A2图案化，并且通过湿法蚀刻工艺或干法刻蚀工艺进行蚀刻，以从选定位置移除经图案化的半导体材料。在某些实施方式中，蚀刻工艺是选择性蚀刻，并且电介质膜105用作蚀刻停止层。根据各种实施方式，在形成模塑料112之后形成一个或多个沟道104。
参考图2G，示出了在移除电介质膜105暴露于一个或多个沟道104中的部分，以便暴露一个或多个再分布层106之后的封装组件200。可以使用例如湿法或干法图案化/蚀刻工艺或者激光钻孔工艺来移除电介质膜105的电介质材料。一个或多个再分布层106的导电材料可以用作蚀刻/激光停止材料。
参考图2H，示出了在一个或多个沟道104中形成一个或多个球下金属化(UBM)结构116之后的封装组件200。一个或多个UBM结构116一般地通过使用任何合适的沉积工艺沉积导电材料而形成。一个或多个UBM结构116可以用作一个或多个封装互连结构(例如，图2I的一个或多个封装互连结构114)与半导体基底102的半导体材料之间的缓冲。在某些实施方式中，一个或多个UBM结构116形成在一个或多个沟道104中的一个或多个再分布层106的暴露部分上，以及形成在一个或多个沟道104内的半导体基底102上。在其他实施方式中，根本不形成一个或多个UBM结构116(例如，正如在图1的封装组件100中可以看到的那样)。形成UBM结构116可以提供增加的联结可靠性。不形成UBM结构116可以简化制作工艺和/或减少与制作工艺相关联的成本。
参考图2I，示出了在一个或多个沟道104中形成一个或多个封装互连结构114之后的封装组件200。一个或多个封装互连结构114电耦合到一个或多个再分布层106以路由一个或多个裸片108的电信号。在某些实施方式中，一个或多个封装互连结构114形成在一个或多个UBM结构116上。在其他实施方式中，一个或多个封装互连结构114直接形成在一个或多个再分布层106上。
一个或多个封装互连结构114可以通过各种各样合适的技术(包括例如丝网印刷、电镀和/或焊球放置)而形成。一个或多个封装互连结构114可以以各种各样的方式(包括例如球栅阵列(BGA)配置)来配置。
图3示意性地示出包括凹陷的半导体基底102的另一封装组件300。封装组件300与图2I所示的封装组件200类似，只不过封装组件300进一步包括(i)形成在一个或多个裸片108与半导体基底102之间的底部填充物118，以及(ii)一个或多个裸片108的暴露的背侧表面。
底部填充物118可以例如在形成模塑料112之前形成(例如，如图2C的封装组件200所示)。根据各种实施方式，底部填充物118通过液体分配或者注射工艺而以液体形式沉积。底部填充物118可以包括例如环氧树脂或其他合适的电绝缘材料。底部填充物118一般地增加在一个或多个裸片108与半导体基底102之间的粘合，提供一个或多个凸点110之间的电绝缘，和/或保护一个或多个凸点110不受到潮湿和氧化。在某些实施方式中，底部填充物118结合模塑料112而使用，正如可以看到的那样。
模塑料112可以形成为使得一个或多个裸片108的背侧表面暴露以便于散热。在一个实施方式中，可以使用如下模具来沉积模塑料112，该模具使得模塑料112被形成为使得一个或多个裸片108的背侧表面暴露。在其他实施方式中，模塑料可以沉积为封住一个或多个裸片，并且随后可以使模塑料凹陷以暴露一个或多个裸片108的背侧表面。
图4是用以制作在此描述的封装组件(例如，图2I的封装组件200)的方法400的处理流程图。在步骤402中，方法400包括提供半导体基底(例如，图2A的半导体基底102)。该半导体基底一般地包括第一表面(例如，图2A的第一表面A1)和与第一表面相反地布置的第二表面(例如，图2A的第二表面A2)。
在步骤404中，方法400进一步包括在半导体基底上形成电介质膜(例如，图2A的电介质膜105)。电介质膜可以根据结合图2A而描述的技术来形成。
在步骤406中，方法400进一步包括在半导体基底上形成再分布层(例如，图2B的一个或多个再分布层106)。再分布层可以根据结合图2B而描述的技术来形成。
在步骤408中，方法400进一步包括将一个或多个裸片(例如，图2C的一个或多个裸片108)电耦合到再分布层。该一个或多个裸片可以根据结合图2C而描述的技术来耦合。
在步骤410中，方法400进一步包括在半导体基底上形成模塑料(例如，图2D的模塑料112)。模塑料可以根据结合图2D而描述的技术来形成。
在步骤412中，方法400进一步包括使半导体基底的表面(例如，图2E的第二表面A2)凹陷。该表面可以根据结合图2E而描述的技术被凹陷。
在步骤414中，方法400进一步包括形成通过半导体基底的一个或多个沟道(例如，图2F和图2G的一个或多个沟道104)。该一个或多个沟道可以根据结合图2F和图2G而描述的技术来形成。
在步骤416中，方法400进一步包括在一个或多个沟道中形成一个或多个凸点下金属化(UBM)结构(例如，图2H的一个或多个UBM结构116)。该一个或多个UBM结构可以根据结合图2H而描述的技术来形成。
在步骤418中，方法400进一步包括在一个或多个沟道中形成一个或多个封装互连结构(例如，图2I的一个或多个封装互连结构114)。该一个或多个封装互连结构可以根据结合图2I而描述的技术来形成。
尽管已经在此示出和描述了特定实施方式，但在不脱离本公开范围的情况下，用于实现相同目的的广泛的各种各样的变更和/或等同的实施方式或实现可以代替所示出和描述的实施方式。本公开旨在覆盖在此讨论的实施方式的任何调整或变化。因此，在此描述的实施方式显然旨在仅由权利要求书及其等同形式限定。

Claims (20)

1.一种方法，包括：
提供半导体基底，所述半导体基底具有(i)第一表面和(ii)与所述第一表面相反地布置的第二表面；
在所述半导体基底的所述第一表面上形成电介质膜；
在所述电介质膜上形成再分布层；
将一个或多个裸片电耦合到所述再分布层；
在所述半导体基底上形成模塑料；
使所述半导体基底的所述第二表面凹陷；
形成通过所述半导体基底的凹陷的第二表面的一个或多个沟道以暴露所述再分布层；以及
在所述一个或多个沟道中形成一个或多个封装互连结构，所述一个或多个封装互连结构被电耦合到所述再分布层，所述一个或多个封装互连结构用以路由所述一个或多个裸片的电信号。
2.根据权利要求1的方法，其中所述再分布层通过在所述电介质膜上沉积导电材料而形成。
3.根据权利要求1的方法，其中所述一个或多个裸片以倒装芯片配置耦合到所述再分布层。
4.根据权利要求1的方法，其中所述模塑料通过将电绝缘材料沉积为实质上封住所述一个或多个裸片而形成。
5.根据权利要求1的方法，其中所述半导体基底通过研磨工艺或蚀刻工艺被凹陷。
6.根据权利要求1的方法，其中所述半导体基底是凹陷的，从而使得所述半导体基底所具有的厚度在大约50微米与大约300微米之间。
7.根据权利要求1的方法，其中所述一个或多个沟道是通过如下方式形成的：
选择性地移除所述半导体基底的半导体材料；以及
选择性地移除所述电介质膜的电介质材料。
8.根据权利要求1的方法，进一步包括：
在所述一个或多个沟道中形成一个或多个球下金属化(UBM)结构，所述一个或多个UBM结构被形成在(i)通过形成所述一个或多个沟道而暴露的所述再分布层和(ii)所述一个或多个沟道内的所述半导体基底上，其中所述一个或多个封装互连结构耦合到所述一个或多个UBM结构。
9.根据权利要求1的方法，其中所述一个或多个封装互连结构包括通过(i)丝网印刷、(ii)电镀以及(iii)焊球放置中的至少一个而形成的焊球。
10.根据权利要求1的方法，进一步包括：
在(i)所述一个或多个裸片与(ii)所述半导体基底之间形成底部填充层。
11.根据权利要求1的方法，其中在形成所述模塑料之后形成所述一个或多个沟道；以及
所述模塑料用作机械载体以在所述半导体基底的所述第二表面被凹陷时支撑所述半导体基底。
12.一种装置，包括：
半导体基底，所述半导体基底具有(i)第一表面和(ii)与所述第一表面相反地布置的第二表面；
形成在所述半导体基底的所述第一表面上的电介质膜；
形成在所述电介质膜上的再分布层；
电耦合到所述再分布层的一个或多个裸片；
形成在所述半导体基底上的模塑料；
形成为通过所述半导体基底的所述第二表面的一个或多个沟道；以及
沉积在所述一个或多个沟道中的一个或多个封装互连结构，所述一个或多个封装互连结构通过所述一个或多个沟道电耦合到所述再分布层，以路由所述一个或多个裸片的电信号。
13.根据权利要求12的装置，其中所述一个或多个裸片使用一个或多个凸点以倒装芯片配置耦合到所述再分布层。
14.根据权利要求12的装置，其中所述模塑料实质上封住所述一个或多个裸片。
15.根据权利要求12的装置，其中所述半导体基底的所述第二表面是凹陷的，从而使得所述半导体基底所具有的厚度在大约50微米与大约300微米之间。
16.根据权利要求12的装置，进一步包括：
形成在所述一个或多个沟道中的一个或多个球下金属化(UBM)结构，所述一个或多个UBM结构形成在(i)所述再分布层和(ii)所述一个或多个沟道内的所述半导体基底上，其中所述一个或多个封装互连结构耦合到所述一个或多个UBM结构。
17.根据权利要求12的装置，进一步包括：
形成在(i)所述一个或多个裸片与(ii)所述半导体基底之间的底部填充层。
18.根据权利要求12的装置，其中：
所述一个或多个封装互连结构包括焊球用以路由所述一个或多个裸片的电信号；以及
所述再分布层包括导电材料用以路由所述一个或多个裸片的所述电信号。
19.根据权利要求12的装置，其中：
所述半导体基底包括硅；
所述一个或多个裸片包括硅；以及
所述一个或多个沟道包括一个或多个硅贯通孔。
20.根据权利要求19的装置，其中：
所述模塑料和所述半导体基底具有相同或实质上类似的热膨胀系数(CTE)；以及
所述一个或多个硅贯通孔是锥形的。
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