TWI643305B - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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Publication number
TWI643305B
TWI643305B TW107101440A TW107101440A TWI643305B TW I643305 B TWI643305 B TW I643305B TW 107101440 A TW107101440 A TW 107101440A TW 107101440 A TW107101440 A TW 107101440A TW I643305 B TWI643305 B TW I643305B
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Taiwan
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circuit layer
die
redistribution circuit
redistribution
layer
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TW107101440A
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TW201828436A (zh
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林漢文
徐宏欣
張簡上煜
林南君
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力成科技股份有限公司
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Publication of TW201828436A publication Critical patent/TW201828436A/zh
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Abstract

一種封裝結構，包括第一重佈線路層、第二重佈線路層、晶粒、多個導電柱以及晶粒堆疊結構。第一重佈線路層具有第一表面以及相對於第一表面的第二表面。第二重佈線路層位於第一表面上。晶粒位於第一重佈線路層與第二重佈線路層之間，並且具有主動面以及相對於主動面的後表面。主動面黏著於第一表面，且晶粒電性連接至第一重佈線路層。導電柱位於並電性連接至第一重佈線路層與第二重佈線路層之間。晶粒堆疊結構接合在第二重佈線路層上。

Description

封裝結構及其製造方法
本發明是有關於一種封裝結構，且特別是有關於一種具有晶粒堆疊結構的封裝結構。
為了使電子產品設計實現輕、薄、短、小的特徵，科技不斷進步以試圖開發出體積更小、重量更輕、整合性更高以及在市場上競爭力更高的產品。隨著產品的體積逐漸縮小，封裝結構中的晶粒也需要在各種維度下更加縮小，如：厚度。因此，如何將封裝結構微型化以達成電子產品朝向輕薄、短小的設計趨勢，實為目前研究人員亟欲解決的課題。
本發明提供一種半導體封裝結構及其製造方法，其可以有效地減少封裝結構的整體體積及線路長度。
本發明提供一種封裝結構，其包括第一重佈線路層、第二重佈線路層、晶粒、多個導電柱以及晶粒堆疊結構。第一重佈線路層具有第一表面以及相對於第一表面的第二表面。第二重佈線路層位於第一重佈線路層的第一表面上。晶粒配置於第一重佈線路層與第二重佈線路層之間。晶粒具有主動面以及相對於主動面的後表面，其中主動面黏著於第一重佈線路層的第一表面，且晶粒電性連接至第一重佈線路層。導電柱位於第一重佈線路層與第二重佈線路層之間，且導電柱電性連接至第一重佈線路層與第二重佈線路層。晶粒堆疊結構接合在第二重佈線路層上。
在本發明的一實施例中，封裝結構更包括晶粒黏著層，位於所述晶粒的所述後表面與所述第一重佈線路層之間。
在本發明的一實施例中，晶粒堆疊結構包括多個晶粒。
本發明提供一種封裝結構的製造方法。此方法至少包括以下步驟。提供載體基板。於載體基板上形成第一重佈線路層。第一重佈線路層具有第一表面以及相對於第一表面的第二表面。載體基板黏著於第二表面上。於第一表面上形成多個導電柱。於第一表面上與多個導電柱之間黏著多個晶粒。各個晶粒具有主動面以及相對於主動面的後表面。藉由絕緣密封體包封晶粒與導電柱。於晶粒與絕緣密封體上方形成第二重佈線路層。晶粒藉由主動面接合至第二重佈線路層。將載體基板與第一重佈線路層分離。於第一重佈線路層上接合晶粒堆疊結構。
在本發明的一實施例中，封裝結構的製造方法更包括以下步驟。在藉由絕緣密封體包封多個晶粒與多個導電柱的步驟後，薄化絕緣密封體以暴露出多個導電柱。
在本發明的一實施例中，晶粒堆疊結構藉由打線接合至第一重佈線路層。
在本發明的一實施例中，封裝結構的製造方法更包括以下步驟。於第二重佈線路層上形成多個球墊。
在本發明的一實施例中，封裝結構的製造方法更包括以下步驟。藉由第二絕緣密封體將晶粒堆疊結構包封於第一重佈線路層上。
本發明提供一種封裝結構的製造方法。此方法至少包括以下步驟。提供第一載體基板。於第一載體基板上形成第一重佈線路層。第一重佈線路層具有第一表面以及相對於第一表面的第二表面。第一表面面向第一載體基板。將第一重佈線路層由第一載體基板轉移至第二載體基板。第二載體基板貼附於第一重佈線路層的第二表面。於第一表面上形成多個導電柱。於第一表面上與導電柱之間配置多個晶粒。各個晶粒具有主動面以及相對於主動面的後表面。晶粒的主動面面向第一重佈線路層的第一表面。晶粒電性連接至第一重佈線路層。藉由絕緣密封體包封晶粒與導電柱。於晶粒、導電柱與絕緣密封體上方形成第二重佈線路層。第二重佈線路層貼附於晶粒的後表面。將第二載體基板與第一重佈線路層分離。將晶粒堆疊結構接合至第二重佈線路層。
在本發明的一實施例中，封裝結構的製造方法更包括以下步驟。在藉由第一絕緣密封體包封多個晶粒與多個導電柱的步驟後，薄化絕緣密封體以暴露出多個導電柱。
在本發明的一實施例中，晶粒堆疊結構藉由打線接合至第二重佈線路層。
在本發明的一實施例中，封裝結構的製造方法更包括以下步驟。於第一重佈線路層上形成多個球墊。
在本發明的一實施例中，封裝結構的製造方法更包括以下步驟。藉由第二絕緣密封體將晶粒堆疊結構包封於第二重佈線路層上。
基於上述，晶粒堆疊結構直接位於第二重佈線路層上並與其接觸。此外，晶粒堆疊結構可以藉由第一重佈線路層、第二重佈線路層以及位於第一重佈線路層與第二重佈線路層之間的導電柱電性連接至位於第一重佈線路層與第二重佈線路層之間的晶粒。因此，在晶粒堆疊結構與第二重佈線路層之間沒有進一步配置凸塊結構、間隙或是其他基板。因此，封裝結構的整體厚度可以減小。此外，簡化的封裝結構可以減少製程的時間與材料耗用，進而降低封裝結構的製造成本。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A至圖1M是依據本發明一實施例的封裝結構的製造方法的剖面示意圖。請參照圖1A，提供第一載體基板100。第一載體基板100可以由矽、玻璃、樹脂或其他適宜的材料所構成。其他適宜的基板材料也可以作為第一載體基板100，只要前述的材料能夠在後續的製程中提供承載，且能構承載在後續的製程中形成於其上的封裝結構即可。形成第一黏著層200於第一載體基板100上，以暫時地增強第一載體基板100以及隨後形成於其上的元件之間的黏著。第一黏著層200可以為光熱轉換（light to heat conversion；LTHC）黏著層或是其他適宜的黏著層。
請參照圖1B，在第一載體基板100與第一黏著層200上形成第一重佈線路層300。第一重佈線路層300包括第一介電層330以及多個電性連接至外部電路或元件的第一線路層320。此外，如圖1B所示，第一重佈線路層300具有第一表面300a與相對於第一表面300a的第二表面300b。
請參照圖1C，在第一重佈線路層300的第一表面300a上形成多個導電柱400。導電柱400電性連接至第一重佈線路層300。導電柱400可以由銅、鋁、錫、金、銀或上述之組合所構成。
請參照圖1D，在第一表面300a上配置多個晶粒50。晶粒50可包括應用處理器（application processor；AP）、系統單晶片（system on chip；SoC）、中央處理器（central processing unit；CPU）或是其他半導體晶片。為了將晶粒50附著至重佈線路層300的第一表面300a，可以將晶粒黏著層500設置於晶粒50與第一重佈線路層300的第一表面300a之間。在本實施例中，晶粒黏著層500可由環氧樹脂（epoxy）、銀膠、晶粒黏著膜或其他適宜的黏著材料所構成。各個晶粒50具有主動面50a與相對於主動面50a的後表面50b。如圖所示，第一重佈線路層300藉由晶粒黏著層500貼附至晶粒50的後表面50b。晶粒黏著層500可由例如旋轉塗佈（spin coating）、噴墨打印（inkjet printing）或其他適宜的製造方法形成，為提供一結構支撐以消除晶粒50與第一重佈線路層300之間的機械夾緊（mechanical clamping）需求。如圖1D所示，在主動面50a上形成多個凸塊52與接墊51。在一些未以圖呈現的實施例中，在晶圓被切割為多個晶粒50之前，可以於晶圓上形成晶粒黏著層500。
請參照圖1E，第一絕緣密封體600可以用於包封晶粒50與導電柱400。第一絕緣密封體600可以包括藉由模塑製程（molding process）所形成的模塑化合物（molding compound）。第一絕緣密封體600可以是由例如是環氧樹脂或其他適宜樹脂等絕緣材料所形成。可以藉由薄化製程（thinning process）將第一絕緣密封體600薄化，以暴露出導電柱400與凸塊52而用於後續的製程。在本實施例中，薄化製程可以經由機械研磨，化學機械研磨（chemical mechanical polishing；CMP）、蝕刻或其他適宜的製程來執行。導電柱400的蝕刻製程可以包括非等向性蝕刻（anisotropic etching）或等向性蝕刻（isotropic etching）。
請參照圖1F，在晶粒50、導電柱400與第一絕緣密封體600上方形成第二重佈線路層700。第二重佈線路層700可以包括多個第二介電層730、第二線路層720以及第二球墊710。如圖1F所示，第二重佈線路層700藉由導電柱400電性連接至導電柱400與第一重佈線路層300。此外，晶粒50藉由凸塊52與接墊51電性連接至第二重佈線路層700。且多個第二球墊710可以位於第二重佈線路層700上。
請參照圖1G，第二載體基板800藉由第二黏著層900黏著至第二重佈線路層700。第二黏著層900可藉由層壓製程（lamination process）形成。此外，第一載體基板100可以藉由第一黏著層200而從第一重佈線路層300的第二表面300b分離。
請參照圖1H，由於打線接合機（wire bonding machine）（未繪示）的尺寸限制，可以在打線接合製程（wire bonding process）之前將切割製程（strip sawing process）用於封裝結構。在一些實施例中，切割製程可以在打線接合製程後被用於封裝結構。切割製程的順序是依據製程設備的型態與實際需求進行調整。在切割製程前，可以藉由第二黏著層900使第二載體基板800從第二重佈線路層700剝離。
請參照圖1I與圖1J，於第一重佈線路層300的第二表面300b上形成晶粒堆疊結構70。在本實施例中，晶粒堆疊結構70包括彼此堆疊於其上的至少一底部半導體晶粒與一頂部半導體晶粒。舉例而言，如圖1I與圖1J所示，晶粒堆疊結構70包括第一半導體晶粒71與第二半導體晶粒72。第一半導體晶粒71位於第一重佈線路層300的第二表面300b上。第二半導體晶粒72堆疊在第一半導體晶粒71上。在一些實施例中，晶粒黏著膜（die attach film；DAF）76可位於每一堆疊晶粒71與72的底面上以提升黏著性。第一半導體晶粒71與第二半導體晶粒72例如是記憶晶粒或快閃（flash）晶粒。
如圖所示，第二半導體晶粒72可以覆蓋第一半導體晶粒71的部分上表面，且第二半導體晶粒72暴露出第一半導體晶粒71的其餘部分上表面，其中前述的第一半導體晶粒71的其餘部分上表面具有多個晶粒接合墊73。 第二半導體晶粒72的上表面也有多個晶粒接合墊73。晶粒接合墊73例如是鋁墊、銅墊或其他適合用於打線接合的材料。如圖1I所示，提供多條導線75以電性連接至第一半導體晶粒71的晶粒接合墊73、第二半導體晶粒72的晶粒接合墊73以及第一重佈線路層300的第一接合墊310。整體來說，晶粒堆疊結構70藉由打線接合電性連接至第一重佈線路層300，並進一步地藉由導電柱400與第二重佈線路層700電性連接至晶粒50。
請參照圖1K，可以藉由第二絕緣密封體1000以將設置於第一重佈線路層300的第二表面300b上的晶粒堆疊結構70包封，而形成如圖1K所示的封裝結構10。第二絕緣密封體1000的側邊可以與第一絕緣密封體600的側邊對齊。亦即晶粒50與晶粒堆疊結構70可以皆位於單一封裝件中。整體來說，在晶粒堆疊結構70與晶粒50之間不需要使用額外的基板或形成間隙。晶粒堆疊結構70與晶粒50的封裝結構10的整體厚度可以更加地減小。
請參照圖1L，例如可以藉由植球製程（ball placement process）與回焊製程（reflow process），以在第二球墊710上形成多顆導電球1100。請參照圖1M，在第二球墊710上放置導電球1100之後，對如圖1L所示的封裝結構10進行切單製程（singulation process），以形成如圖1M所示的個別封裝結構10。
圖2A至圖2L是依據本發明另一實施例的封裝結構的製造方法的剖面示意圖。圖2A至圖2L所示的實施例與圖1A至圖1M所示的實施例類似，因此採用相同的標號來表示相同或近似的元件，故於此不加以贅述。圖2A至圖2L所示的實施例與圖1A至圖1M所示的實施例的差異在於：晶粒50的配置方式，其中晶粒50是以覆晶（flip-chip）的方式配置。
請參照圖2A，提供第一載體基板100。此外，於第一載體基板100上形成第一黏著層200。第一重佈線路層300’藉由第一黏著層200貼附於第一載體基板100上。第一重佈線路層300’包括第一表面300a’與相對於第一表面300a’的第二表面300b’。如圖2A所示，第一表面300a’與第一載體基板100接觸。第一重佈線路層300’可包括多個第一介電層330’、第一線路層320’以及設置於第二表面300b’上的第一球墊310’。第一線路層320’電性連接至第一球墊310’。在本實施例中，第一線路層320’可由銅、鎳或上述之組合所構成。
請參照圖2B，將第一重佈線路層300’自第一載體基板100轉移至第二載體基板800。第二載體基板800藉由第二黏著層900貼附於第一重佈線路層300’的第二表面300b’上。
請參照圖2C，在第一表面300a’上形成導電柱400且電性連接至第一重佈線路層300’。請參照圖2D，藉由覆晶接合製程（flip-chip bonding process）以將晶粒50分別設置於第一表面300a’上。在一些實施例中，晶粒50藉由覆晶接合的銅柱電性連接至第一重佈線路層300’。晶粒50具有主動面50a與相對於主動面50a的後表面50b。如圖2D所示，主動面50a面對第一重佈線路層300’的第一表面300a’。
如圖2D所示，多個導電端點350’可以形成於第一重佈線路層300’的第一表面300a’上，並且電性連接至上述的第一線路層320’與第一接合墊310。導電端點350’可以是為了鑲嵌球或是連接接墊的多個凸塊底金屬（under-ball metallurgy；UBM）圖案。此外，凸塊52與接墊51可以形成於晶粒50的主動面50a上，並且接合至導電端點350’。
請參照圖2E，可以藉由第一絕緣密封體600包封晶粒50與導電柱400。可以藉由薄化製程將第一絕緣密封體600薄化，以暴露出導電柱400與晶粒50的後表面50b。在另一未繪示的實施例中，在進行薄化製程之後，第一絕緣密封體600或介電層可以仍然覆蓋晶粒50的後表面50b。薄化製程可以經由機械研磨，化學機械研磨（chemical mechanical polishing；CMP）、蝕刻或其他適宜的製程來執行。導電柱400的蝕刻製程可以包括非等向性蝕刻（anisotropic etching）或等向性蝕刻（isotropic etching）。
請參照圖2F，於晶粒50、導電柱400以及第一絕緣密封體600上方形成第二重佈線路層700’。請參照圖2G，由於打線接合機（未繪示）的尺寸限制，可以將切割製程用於封裝結構。第二重佈線路層700’可以直接與晶粒50的後表面50b接觸。因此，在晶粒50的後表面50b與第二重佈線路層700之間沒有設置額外的黏著層或介電層。因此，整體封裝結構的厚度可以更加地減小。
請參照圖2H，於第二重佈線路層700’上配置晶粒堆疊結構70。如圖2H所示，第二重佈線路層700’可包括多個第二線路層720’與第二介電層730’，第二線路層720’與第二介電層730’交替地形成或堆疊在彼此的上表面上。此外，第二重佈線路層700’可以更包括多個第二接合墊710’，第二接合墊710’設置於第二重佈線路層700’的表面上，以用於後續晶粒堆疊結構70的打線接合製程。晶粒堆疊結構70包括彼此堆疊於其上的至少一底部半導體晶粒與一頂部半導體晶粒。舉例而言，如圖2H所示，晶粒堆疊結構70包括第一半導體晶粒71與堆疊於其上的第二半導體晶粒72。在一些實施例中，晶粒黏著膜76可位於每一堆疊晶粒71與72的底面上以提升黏著性。
請參照圖2I，第二半導體晶粒72覆蓋第一半導體晶粒71的部分上表面，且第二半導體晶粒72暴露出其餘部分上表面，其中前述的其餘部分上表面具有多個晶粒接合墊73。第二半導體晶粒72的上表面也有晶粒接合墊73。晶粒接合墊73例如是鋁墊、銅墊或其他適合用於打線接合的材料。第一半導體晶粒71的晶粒接合墊73與第二半導體晶粒72的晶粒接合墊73藉由多條導線75電性連接至第二重佈線路層700’的第二接合墊710’。因此，晶粒堆疊結構70打線接合至第二重佈線路層700’、導電柱400以及電性連接至晶粒50。
請參照圖2J，可以藉由第二絕緣密封體1000包封第二重佈線路層700’表面上的晶粒堆疊結構70。如上所述，第二絕緣密封體1000的側邊可以與第一絕緣密封體600對齊。亦即晶粒50與晶粒堆疊結構70可以位於單一封裝件中。因此，在晶粒堆疊結構70與第二重佈線路層700’之間沒有額外的間隙或基板。在晶粒堆疊結構70與晶粒50之間的封裝結構的整體厚度與傳導路徑都能夠更加地減少與縮短。
請參照圖2K，例如可以藉由植球製程與回焊製程，以於第一重佈線路層300’的第一球墊310’上形成多個導電球1100。請參照圖2L，在第一球墊310'上放置導電球1100之後，對如圖2K所示的封裝結構10進行切單製程，以形成如圖2L所示的個別封裝結構10。
綜上所述，封裝結構可包括一頂部的重佈線路層、一較低的重佈線路層與設置於兩者之間的晶粒。此外，在晶粒與頂部的重佈線路層上方配置晶粒堆疊結構。晶粒堆疊結構的底面會直接接觸頂部的重佈線路層，且在其之間有多條導線連接。因此，在晶粒堆疊結構的底面與頂部的重佈線路層之間沒有設置額外的間隙或基板。如此一來，晶粒堆疊結構可以藉由位於其與晶粒之間的導線、頂部的重佈線路層、底部的重佈線路層以及導電柱電性連接至晶粒。透過上述的結構，封裝結構可以基於其厚度與導電路徑而進一步地被簡化與微型化。簡化的封裝結構亦可減少製程的時間與材料耗用，進而降低整體製造成本。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10‧‧‧封裝結構
50‧‧‧晶粒
50a‧‧‧主動面
50b‧‧‧後表面
51‧‧‧接墊
52‧‧‧凸塊
70‧‧‧晶粒堆疊結構
71‧‧‧第一半導體晶粒
72‧‧‧第二半導體晶粒
73‧‧‧晶粒接合墊
75‧‧‧導線
76‧‧‧晶粒黏著膜
100‧‧‧第一載體基板
200‧‧‧第一黏著層
300、300’‧‧‧第一重佈線路層
300a、300a’‧‧‧第一表面
300b、300b’‧‧‧第二表面
310‧‧‧第一接合墊
310’‧‧‧第一球墊
320、320’‧‧‧第一線路層
330、330’‧‧‧第一介電層
350’‧‧‧導電端點
400‧‧‧導電柱
500‧‧‧晶粒黏著層
600‧‧‧第一絕緣密封體
700、700’‧‧‧第二重佈線路層
710‧‧‧第二球墊
710’‧‧‧第二接合墊
720、720’‧‧‧第二線路層
730、730’‧‧‧第二介電層
800‧‧‧第二載體基板
900‧‧‧第二黏著層
1000‧‧‧第二絕緣密封體
1100‧‧‧導電球
圖1A至圖1M是依據本發明一實施例的封裝結構的製造方法的剖面示意圖。 圖2A至圖2L是依據本發明另一實施例的封裝結構的製造方法的剖面示意圖。

Claims (2)

  1. 一種封裝結構的製造方法，包括：提供載體基板；於所述載體基板上形成第一重佈線路層，其中所述第一重佈線路層具有第一表面以及相對於所述第一表面的第二表面，且所述載體基板黏著於所述第二表面上；於所述第一表面上形成多個導電柱；於所述第一表面上與所述多個導電柱之間黏著多個晶粒，其中各個所述多個晶粒具有主動面以及相對於所述主動面的後表面；藉由絕緣密封體包封所述多個晶粒與所述多個導電柱；於所述多個晶粒與所述絕緣密封體上方形成第二重佈線路層，其中所述多個晶粒藉由所述主動面接合至所述第二重佈線路層；將所述載體基板與所述第一重佈線路層分離；以及於所述第一重佈線路層上接合晶粒堆疊結構。
  2. 一種封裝結構的製造方法，包括：提供第一載體基板；於所述第一載體基板上形成第一重佈線路層，其中所述第一重佈線路層具有第一表面以及相對於所述第一表面的第二表面，其中所述第一表面面向所述第一載體基板；將所述第一重佈線路層由所述第一載體基板轉移至第二載體基板，其中所述第二載體基板貼附於所述第一重佈線路層的所述第二表面；於所述第一表面上形成多個導電柱；於所述第一表面上與所述多個導電柱之間配置多個晶粒，其中各個所述多個晶粒具有主動面以及相對於所述主動面的後表面，所述多個晶粒的所述主動面面向所述第一重佈線路層的所述第一表面，且所述多個晶粒電性連接至所述第一重佈線路層；藉由絕緣密封體包封所述多個晶粒與所述多個導電柱；於所述多個晶粒、所述多個導電柱與所述絕緣密封體上方形成第二重佈線路層，其中所述第二重佈線路層貼附於所述多個晶粒的所述後表面；將所述第二載體基板與所述第一重佈線路層分離；以及將晶粒堆疊結構接合至所述第二重佈線路層。
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