TW201642358A - 半導體封裝組件及其製造方法 - Google Patents

半導體封裝組件及其製造方法 Download PDF

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TW201642358A
TW201642358A TW105113409A TW105113409A TW201642358A TW 201642358 A TW201642358 A TW 201642358A TW 105113409 A TW105113409 A TW 105113409A TW 105113409 A TW105113409 A TW 105113409A TW 201642358 A TW201642358 A TW 201642358A
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semiconductor package
semiconductor
semiconductor wafer
redistribution layer
layer structure
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TW105113409A
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TWI582858B (zh
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林子閎
彭逸軒
蕭景文
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聯發科技股份有限公司
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Abstract

本發明提供半導體封裝組件，半導體封裝組件包含半導體封裝。半導體封裝包含半導體晶片。重佈層結構設置於半導體晶片之上，且與半導體晶片電性連接。主動或被動元件設置於半導體晶片與重佈層結構之間。模塑料圍繞半導體晶片和主動或被動元件。

Description

半導體封裝組件及其製造方法
本發明係有關於半導體封裝組件(package assembly)，特別有關於具有被動元件的半導體封裝組件及其製造方法。
為了確保電子產品與通訊裝置的小型化與多功能性，期望半導體封裝在尺寸上變小，並且支持多引腳連接、高速操作和具有高功能性。傳統的半導體封裝通常將被動元件設置於印刷電路板(printed circuit board,PCB)上。然而，印刷電路板需要提供額外的區域以將被動元件安裝於其上，因此難以縮減封裝尺寸。
因此，需要創新的半導體封裝組件及其製造方法。
本發明的一些實施例提供一種半導體封裝組件，其包含半導體封裝。半導體封裝包含半導體晶片。重佈層結構設置於半導體晶片之上，且電性連接半導體晶片。主動或被動元件設置於半導體晶片與重佈層結構之間。模塑料圍繞半導體晶片和主動或被動元件。
本發明的另一些實施例提供一種半導體封裝組件，其包含第一半導體封裝。第一半導體封裝包含半導體晶 片。重佈層結構設置於半導體晶片之上，且電性連接半導體晶片。主動或被動元件設置於半導體晶片與重佈層結構之間。半導體封裝組件也包含第二半導體封裝堆疊於第一半導體封裝之上，第一半導體晶片位於主動或被動元件與第二半導體封裝之間。
本發明的一些實施例提供一種半導體封裝組件的製造方法，包含形成半導體封裝。半導體封裝的形成包含在半導體晶片上提供主動或被動元件。形成模塑料圍繞半導體晶片和主動或被動元件。形成重佈層結構於半導體晶片之上，且電性連接半導體晶片。主動或被動元件位於半導體晶片與重佈層結構之間。
本發明半導體封裝組件的尺寸可大幅地縮減。
100、300、320‧‧‧半導體晶片
110、310、330‧‧‧導電墊
120‧‧‧鈍化層
130‧‧‧導孔
140‧‧‧主動元件
150‧‧‧被動元件
160‧‧‧導電結構
170‧‧‧承載基底
180‧‧‧重佈層結構
190‧‧‧第一子介電層
192‧‧‧第二子介電層
200‧‧‧導電線路
210‧‧‧導孔
220‧‧‧模塑料
230‧‧‧重佈層結構
240‧‧‧金屬層間介電層
242‧‧‧第一子介電層
244‧‧‧第二子介電層
246‧‧‧第三子介電層
250‧‧‧第一導電線路
252‧‧‧第二導電線路
260、280‧‧‧導電元件
270‧‧‧開口
290‧‧‧基底
340‧‧‧接合線
350‧‧‧模塑料
P1、P2、P3、P4‧‧‧半導體封裝組件
S‧‧‧子封裝
L‧‧‧切割道
第1A至1D圖係根據本發明一些實施例之半導體封裝組件製造方法之各階段的剖面示意圖。
第2圖係根據本發明一些實施例之疊層封裝(package-on-package,POP)半導體封裝組件的剖面示意圖。
第3圖係根據本發明一些實施例之半導體封裝組件的剖面示意圖。
第4圖係根據本發明一些實施例之半導體封裝組件的剖面示意圖。
以下的揭露內容提供許多不同的實施例或範例以 及圖式，然而，這些僅是用以說明本發明之原理，且並非用以限制本發明之範圍。本發明之範圍係以申請專利範圍決定。附圖的描述僅用於理解本發明，並非用於限制本發明。為了說明的目的，在附圖中的一些元件的尺寸可能會放大且並未依照實際比例來繪製。附圖中的尺寸和相對尺寸可能不對應於本發明實際應用中的真實尺寸。
第1A至1D圖係根據本發明一些實施例之半導體封裝組件製造方法之各階段的剖面示意圖。於第1A至1D圖描述的各階段之前、期間及/或之後，可提供一些額外的操作步驟。所描述的一些階段可依據不同實施例被代替或省略，也可將額外的特徵部件加入半導體封裝組件中。以下描述的一些特徵部件可依據不同實施例被代替或省略。
如第1A圖所示，提供半導體晶片(die)(晶粒(chip))100。在一些實施例中，半導體晶片100為應用處理器(application processor,AP)晶片。在一些其他實施例中，半導體晶片100可為邏輯晶片(logic die)或其他適合的晶片。例如邏輯晶片包含中央處理單元(central processing unit,CPU)、圖像處理單元(graphics processing unit,GPU)、動態隨機存取記憶體(dynamic random access memory,DRAM)控制器或其組合。
半導體晶片100的複數個導電墊(pad)110設置於半導體晶片100之正表面(front surface)之上。在一些實施例中，導電墊110係半導體晶片100之內連線結構中最上金屬層的複數個部分。鈍化層(passivation layer)120設置於半導體晶片 100之正表面之上，鈍化層120部分地覆蓋導電墊110。
如第1A圖所示，導孔/導孔電極(via)130形成於半導體晶片100之上，導孔130係電性上和實體上連接至從鈍化層120露出的一些導電墊110。導孔130可為中介穿孔/中介穿孔電極(through interposer via,TIV)。在一些實施例中，導孔130包含銅、其他適合的導電材料或其組合。在一些實施例中，導孔130係透過電鍍(electroplating)製程或其他適合的製程形成。
如第1A圖所示，在半導體晶片100之上提供主動元件140和被動元件150。主動元件140和被動元件150接合至從鈍化層120露出的一些導電墊110。在一些實施例中，主動元件140為半導體晶片。在一些實施例中，主動元件140和半導體晶片100具有不同功能。主動元件140可為基頻(baseband,BB)晶片或其他適合的主動元件。在一些實施例中，被動元件150為整合被動元件(integrated passive device,IPD)，被動元件150可包含複數個電容、電阻、電感、變容二極體或其他適合的被動元件。
主動元件140、被動元件150和導孔130於半導體晶片100之上並排(side by side)設置。在一些實施例中，從上視方向來看，導孔130圍繞主動元件140和被動元件150。
如第1A圖所示，在一實施例中，導孔130高於主動元件140和被動元件150。在一些實施例中，導孔130之頂表面大致上對齊於主動元件140之頂表面。在一些其他實施例中，導孔130低於主動元件140。在一些實施例中，導孔130不 低於被動元件150。
如第1A圖所示，在一實施例中，一個主動元件140和一個被動元件150接合至半導體晶片100。可於本發明的實施例作許多變化和修改。在另一實施例中，多於一個具有相同或不同功能的主動元件140接合至半導體晶片100。在又一實施例中，多於一個具有相同或不同功能的被動元件150接合至半導體晶片100。在一些實施例中，主動元件140和被動元件150中僅有一個接合至半導體晶片100。在一些其他實施例中，僅有複數個主動元件140或者複數個被動元件150接合至半導體晶片100。
在一些實施例中，主動元件140和被動元件150係透過複數個導電結構160電性上和實體上連接至一些導電墊110。每個導電結構160可包含一層或多層導電層、導電凸塊(bump)、導電柱(pillar)、導電膏/膠(paste/glue)或其他導電結構。在一些實施例中，導電結構160包含焊料、銅其他適合的導電材料或其組合。
在一些實施例中，主動元件140和被動元件150係透過相同的製程(例如回流/回焊製程(reflow process))接合至半導體晶片100。在一些其他實施例中，主動元件140和被動元件150係在不同的步驟中接合至半導體晶片100。
根據本發明的一些實施例，導孔130形成於晶圓(wafer)上，且主動元件140和被動元件150接合至具有導孔130位於其上的晶圓。之後將晶圓切割成複數個半導體晶片100，因此藉由晶圓級(wafer-level)製程形成了複數個子封裝 (subpackage)S，子封裝S包含半導體晶片100、導孔130、主動元件140和被動元件150。在一些實施例中，主動元件140和被動元件150直接電性耦接至半導體晶片100而未經由設置於子封裝S外的外部導電元件。
如第1B圖所示，提供承載基底170。在一些實施例中，承載基底170為晶圓或板材(panel)，承載基底170可包含玻璃或其他適合的支撐材料。
如第1B圖所示，重佈層(redlstribution layer,RDL)結構180形成於承載基底170之上，重佈層結構180可包含一或多個導電線路(conductive traces)設置於金屬層間介電(inter-metal dielectric,IMD)層中。例如，複數個導電線路200設置於金屬層間介電層之第一層級(layer-level)，導電線路200位於金屬層間介電層之第一子介電(sub-dielectric)層190之上且被金屬層間介電層之第二子介電層192覆蓋。重佈層結構180可更進一步包含複數個導電線路(未繪示)設置於金屬層間介電層之其他的層級。
在一些實施例中，金屬層間介電層之第一子介電層190和第二子介電層192可由有機材料(包含聚合基材料)、無機材料(包含氮化矽(SiNx)、氧化矽(SiOx)、石墨烯(graphene))或類似的材料形成。例如，第一子介電層190和第二子介電層192係由聚合基材料形成，其中第一子介電層190的厚度大約12微米和第二子介電層192的厚度大約24微米。
導電線路200的導電墊部分從重佈層結構180的頂部露出，例如導電線路200的導電墊部分從第二子介電層192 之開口露出且連接至後續形成的導電元件。應理解的是，繪示於圖中的重佈層結構180之導電線路和子介電層的數量和配置僅為範例且並不侷限本發明。重佈層結構180係可選擇性的。在一些其他實施例中，並未形成重佈層結構180。
如第1B圖所示，導孔210形成於重佈層結構180之上，導孔210係電性上和實體上連接至導電線路200的導電墊部分。導孔210可為封裝穿孔/封裝穿孔電極(through package via,TPV)。在一些實施例中，導孔210包含銅、其他適合的導電材料或其組合。在一些實施例中，導孔210係透過電鍍製程或其他適合的製程形成。在一些實施例中，導孔210的尺寸和高度大於導孔130的尺寸和高度。
之後，在承載基底170之上提供包含半導體晶片100、導孔130、主動元件140和被動元件150的子封裝S，子封裝S和導孔210於承載基底170之上並排設置。在一些實施例中，從上視方向來看，導孔210圍繞半導體晶片100和導孔130。
在一些實施例中，子封裝S係透過黏著層(adhesive layer)(例如膠(glue)或其他適合的黏著材料)貼附於(attach to)重佈層結構180。重佈層結構180位於半導體晶片100與承載基底170之間。在一些實施例中，半導體晶片100位於主動元件140與重佈層結構180之間，且位於被動元件150與重佈層結構180之間。
如第1B圖所示，模塑料(molding compound)220形成於承載基底170之上。模塑料220圍繞半導體晶片100、導孔 130、主動元件140、被動元件150和導孔210。在一些實施例中，模塑料220覆蓋半導體晶片100、主動元件140、被動元件150和重佈層結構180。
在一些實施例中，模塑料220是由非導電性材料(例如環氧化物(epoxy)、樹脂(resin)、可塑形聚合物(moldable polymer)或其他適合的模塑材料)形成。在一些實施例中，可在大體上為液態時塗佈模塑料220，並經由化學反應固化模塑料220。在一些實施例，模塑料220可為紫外光(ultraviolet,UV)或熱固化聚合物的膠體或具延展性的固體，且可經由紫外光或熱固化製程來固化。模塑料220亦可使用模具固化。
在一些實施例中，沉積的模塑料220覆蓋導孔130和導孔210之頂表面，接著實施研磨(grinding)製程以薄化(thin)沉積的模塑料220，結果薄化的模塑料220露出導孔130和導孔210之頂表面。在一些實施例中，導孔130和導孔210之頂表面係與模塑料220之頂表面共平面。
在一些情況下，導孔130和導孔210之頂表面可能在製程中被氧化。在一些實施例中，在薄化沉積的模塑料220時，研磨且移除導孔130和導孔210氧化之頂表面。因此，可提升半導體封裝組件的可靠度。在薄化沉積的模塑料220時，主動元件140的後表面(back surface)可能被研磨。
如第1C圖所示，重佈層結構230(亦被稱為扇出(fan-out)結構)形成於模塑料220之上。在一些實施例中，重佈層結構230係透過導孔130電性連接至半導體晶片100。導孔130位於半導體晶片100與重佈層結構230之間。在一些實施例 中，重佈層結構230係透過導孔210電性連接重佈層結構180。
在一些實施例中，重佈層結構230可包含一或多個導電線路設置於金屬層間介電層中，例如複數個第一導電線路250設置於金屬層間介電層240之第一層級，且複數個第一導電線路250中至少一個係電性耦接至半導體晶片100。再者，複數個第二導電線路252設置於不同於金屬層間介電層240之第一層級的第二層級。在此情況下，金屬層間介電層240可包含連續堆疊於模塑料220之上的第一子介電層242、第二子介電層244和第三子介電層246。第一導電線路250位於第一子介電層242之上，第二導電線路252位於第二子介電層244之上且被第三子介電層246覆蓋。另外，第一導電線路250藉由第二子介電層244與第二導電線路252分隔。
在一些實施例中，金屬層間介電層240可由有機材料(包含聚合基材料)、無機材料(包含氮化矽、氧化矽、石墨烯)或類似的材料形成。例如第一子介電層242、第二子介電層244和第三子介電層246係由聚合基材料形成，其中第一子介電層242具有厚度大約12微米和第二子介電層244具有厚度大約24微米。在一些實施例中，金屬層間介電層240係高介電常數(high-k，k係介電層的介電常數)介電層，在一些實施例中，金屬層間介電層240可由光敏感材料形成，其包含乾膜光阻(dry film photoresist)或膠膜(taping film)。
第二導電線路252的導電墊部分從重佈層結構230的頂部露出，例如第二導電線路252的導電墊部分由第三子介電層246之開口露出且連接至後續形成的導電元件。應理解的 是，繪示於圖中的重佈層結構230之導電線路和子介電層的數量和配置僅為範例且並不侷限本發明。
如第1C圖所示，多個導電元件260形成於重佈層結構230之上，導電元件260係電性上和實體上連接至第二導電線路252的導電墊部分。在一些實施例中，導電元件260和主動元件140位於重佈層結構230之兩個相反側。類似地，導電元件260和被動元件150位於重佈層結構230之兩個相反側。
在一些實施例中，導電元件260為導電柱、導電凸塊(例如微凸塊)、導電膠(paste)結構或其他適合的導電元件。導電元件260可包含銅、焊料或其他適合的導電材料。
如第1D圖所示，剝離承載基底170。移除承載基底170，以露出重佈層結構180。接著，多個開口270形成於重佈層結構180中，進而從重佈層結構180的底部露出導電線路200的導電墊部分。一些導電元件將形成於開口270中，以於重佈層結構180與後續接合的半導體封裝(例如記憶體封裝或其他適合的半導體封裝)之間提供導電通路(electrical conductive path)。在一些實施例中，開口270藉由雷射鑽孔(laser drilling)製程、蝕刻製程(例如乾蝕刻製程)或其他適合的製程形成。
之後，沿著切割道(scribe line)L切割重佈層結構180、模塑料220和重佈層結構230，以形成多個半導體封裝。之後，經切割的半導體封裝接合至另一個半導體封裝(例如，記憶體封裝或其他適合的半導體封裝)，以形成多個半導體封裝組件P1。換句話說，晶圓級扇出封裝係整合於半導體封裝 組件P1內。
在一些實施例中，半導體封裝組件P1可更進一步形成於基底上，舉例來說，基底為印刷電路版(printed circuit board,PCB)，且可由聚丙烯(polypropylene,PP)形成。導電元件260提供導電通路於半導體封裝組件P1與基底之間。
根據本發明的一些實施例，藉由導孔130、重佈層結構230和導電元件260，在半導體晶片100與裝設於半導體晶片100之正表面上的電子元件之間建構導電通路。再者，藉由導孔130、重佈層結構230和導孔210在半導體晶片100與裝設於半導體晶片100之後表面上的電子元件之間建構導電通路。
如第1D圖所示，每個半導體封裝組件P1包含主動元件140和被動元件150設置於半導體晶片100與重佈層結構230之間。換句話說，主動元件140和被動元件150係縱向地(vertically)堆疊於半導體晶片100之上，且整合於單一半導體封裝內。因此，半導體封裝組件P1的尺寸(特別是側向的尺寸)係大幅地縮減。再者，主動元件140與半導體晶片100之間和被動元件150與半導體晶片100之間的線路迴路(trace loop)變得更短，因此使得半導體封裝組件P1具有更好的信號完整性/電源完整性(signal integrity/power integrity,SI/PI)性能，且減緩電阻電容延遲(resistive-capacitive delay)。
在一些情況下，一或多個被動元件和多個導電元件並排設置於晶片上。被動元件和導電元件藉由表面安裝技術(surface-mount technology,SMT)於不同階段形成於晶片 上。由於被動元件和導電元件設置在相同平面上，因此形成被動元件和導電元件的期間，可能會發生SMT良率的問題(例如，焊錫架橋(solder bridge)等)，且難以對被動元件和導電元件實施SMT再加工/重工(rework)。
如第1D圖所示，被動元件150和導電元件260縱向地堆疊。被動元件150和導電元件260位於不同的平面上，而不是並排地設置於相同的平面上，因此消除了前述的SMT良率問題，也更容易進行SMT再加工。更進一步而言，重佈層結構230上的空間並未被被動元件150佔用。可設置更多的導電元件260於重佈層結構230之上，因此能夠增加半導體封裝組件P1的輸出/輸入(input/output,I/O)的連接數量，進一步提升被動元件150和導電元件260的設計彈性。
相應的，再次參考第1A-1D圖，本申請另提供一種半導體封裝組件的製造方法，包括：形成一第一半導體封裝P1，其中該第一半導體封裝P1的形成包括：在一第一半導體晶片100之上提供一主動或被動元件(140或150)；形成一模塑料220圍繞該第一半導體晶片100和該主動或被動元件；以及形成一第一重佈層結構230於該第一半導體晶片100之上，以電性連接該第一半導體晶片100，其中該主動或被動元件位於該第一半導體晶片100與該第一重佈層結構230之間。
在一實施例中，在提供該主動或被動元件之前，形成一第一導孔130於該第一半導體晶片100之上，其中該第一重佈層結構230透過該第一導孔130與該第一半導體晶片100電性連接。
在一實施例中，在形成該模塑料220之前，將具有該主動或被動元件和該第一導孔130於其上的該第一半導體晶片100接合至一承載基底170。
在一實施例中，在形成該第一重佈層結構230之後，剝離該承載基底170；導電元件260在剝離承載基底後實施，再進行切割，以及切割該第一重佈層結構230、第二重佈層結構180和該模塑料220，以形成該第一半導體封裝P1。
在一實施例中，在接合該第一半導體晶片100之前，形成一第二導孔210於該承載基底170之上，其中該第二導孔210和該第一半導體晶片並排設置。在一實施例中，在形成該第二導孔210之前，形成一第二重佈層結構180於該承載基底170之上，其中該第二重佈層結構180位於該第一半導體晶片100與該承載基底170之間。在一實施例中，在形成該第一重佈層結構230之後，剝離該承載基底170，以露出該第二重佈層結構180；以及堆疊一第二半導體封裝於該第一半導體封裝P1之上，其中該第一半導體晶片100位於該主動或被動元件與該第二半導體封裝之間。在剝離該承載基底170之後，形成一開口270於該第二重佈層結構180中；以及形成一導電元件於該開口中，以電性連接該第一半導體封裝和該第二半導體封裝。
可將各種半導體封裝堆疊於第1D圖所示的半導體封裝之上，以形成半導體封裝組件。第2圖係根據本發明一些實施例之疊層封裝(package-on-package,POP)半導體封裝組件的剖面示意圖。為簡化，第2圖中相同於第1A至1D圖中的部件係使用相同的標號並省略其說明。
如第2圖所示，半導體封裝組件P2包含第1D圖所示之半導體封裝和另一堆疊於其上的半導體封裝。應理解的是，第2圖所示堆疊的半導體封裝之結構僅為範例且並不侷限本發明。
兩個半導體封裝彼此接合且透過導電元件280互相電性連接。在一些實施例中，半導體晶片100位於主動元件140與堆疊的半導體封裝之間，且位於被動元件150與堆疊的半導體封裝之間。主動元件140和被動元件150縱向地重疊半導體晶片100和上方覆蓋的半導體封裝。在一些實施例中，導電元件280為導電柱、導電凸塊(例如微凸塊)、導電膏結構或其他適合的導電元件。導電元件280可包含銅、焊料或其他適合的導電材料。在一些其他實施例中，導電元件280被底膠(underfill)材料圍繞。
如第2圖所示，上方覆蓋的半導體封裝包括基底(base)290、至少一個半導體晶片(例如兩個縱向地堆疊的半導體晶片300及半導體晶片320)、接合線(bonding wire)340、模塑料350。在一些其他實施例中，基底290為印刷電路版，且可由聚丙烯所構成。基底290係透過導電元件280電性連接至重佈層結構180。
半導體晶片300係透過黏著層(例如膠或其他適合的黏著材料)貼附在基底290之上。半導體晶片300係透過其具有的導電墊310和接合線340電性連接至基底290。在一些實施例中，半導體晶片300為記憶體晶片(memory die)或其他適合的半導體晶片。半導體晶片320係透過黏著層(例如膠或其他 適合的黏著材料)貼附在半導體晶片300之上，半導體晶片320係透過其具有的導電墊330和接合線340電性連接至基底290。在一些實施例中，半導體晶片320為記憶體晶片或其他適合的半導體晶片。在一些實施例中，半導體晶片300和半導體晶片320為動態隨機存取記憶體晶片。
在一些實施例中，半導體晶片300或半導體晶片320和主動元件140位於基底290的兩個相反側上，半導體晶片300或半導體晶片320和被動元件150位於基底290的兩個相反側上。
如第2圖所示，模塑料350覆蓋基底290，且圍繞半導體晶片300和半導體晶片320。接合線340埋置/嵌入(embedded)於模塑料350中。在一些實施例中，模塑料350可由非導電性材料形成，例如環氧樹脂、樹脂、可塑形聚合物或其他適合的模塑材料。在一些實施例中，可在大體上為液態時塗佈模塑料350，並經由化學反應固化模塑料350。在一些實施例，模塑料350可為紫外光或熱固化聚合物的膠體或具延展性的固體，且可經由紫外光或熱固化製程來固化。模塑料350亦可使用模具固化。
可於本發明的實施例作許多變更和修正。第3和4圖係根據本發明一些實施例之半導體封裝組件的剖面示意圖。為簡化，第3和4圖中相同於第1A至1D圖中的部件係使用相同的標號並省略其說明。
請參照第3圖，其繪示出半導體封裝組件P3。半導體封裝組件P3與第1D圖所示的半導體封裝組件P1相似。半 導體封裝組件P1與P3之間主要的不同處在於半導體封裝組件P1包含一個子封裝S，而半導體封裝組件P3包含兩個子封裝S。在一些實施例中，兩個半導體晶片100並排設置，半導體封裝組件P3可包含多於兩個子封裝S。
在一些實施例中，導孔210位於兩個子封裝S之間。在一些實施例中，導孔210與兩個半導體晶片100並排設置。在一些實施例中，導孔210位於一或兩個半導體晶片100的周圍區域。在一些其他實施例中，並沒有導孔210位於兩個子封裝S之間，一部分的模塑料220夾設於兩個半導體晶片100之間。
請參照第4圖，其繪示出半導體封裝組件P4。半導體封裝組件P4與第1D圖所示的半導體封裝組件P1相似。半導體封裝組件P1與P4之間主要的不同處在於半導體封裝組件P4沒有包含第1D圖所示的重佈層結構180和導孔210。再者，半導體封裝組件P1包含一個子封裝S，而半導體封裝組件P4包含兩個子封裝S。在一些實施例中，兩個半導體晶片100並排設置。在一些實施例中，半導體封裝組件P4可包含一個子封裝S或多於兩個子封裝S。
在一些實施例中，一部分的模塑料220夾設於兩個半導體晶片100之間。在一些實施例中，模塑料220更延伸於半導體晶片100之後表面上且覆蓋半導體晶片100。
根據本發明一些實施例的半導體封裝組件及其製造方法提供各種優點，半導體封裝組件包含一或多個主動或被動元件直接縱向地堆疊於半導體晶片之上。因此，半導體 封裝組件的尺寸顯著地縮減。再者，由於縮短了線路迴路，因此使得半導體封裝組件信號完整性/電源完整性(SI/PI)的效能更好。此外，本發明的一些實施例也提供半導體封裝組件改善製造良率和更多輸出/輸入(I/O)連接之優點。本發明的一些實施例更提供半導體封裝組件具有更好的整合/集成(integration)彈性，例如裝置插入和熱解決方案。
雖然本發明的實施例及其優點已揭露如上，但應理解的是，本發明並未侷限於揭露之實施例。任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可做些許更動與潤飾，因此本發明的保護範圍當以權利要求所界定為准。凡依本發明權利要求所做的均等變化與修飾，皆應屬本發明的涵蓋範圍。
100‧‧‧半導體晶片
110‧‧‧導電墊
120‧‧‧鈍化層
130‧‧‧導孔
140‧‧‧主動元件
150‧‧‧被動元件
160‧‧‧導電結構
180‧‧‧重佈層結構
190‧‧‧第一子介電層
192‧‧‧第二子介電層
200‧‧‧導電線路
210‧‧‧導孔
220‧‧‧模塑料
230‧‧‧重佈層結構
240‧‧‧金屬層間介電層
242‧‧‧第一子介電層
244‧‧‧第二子介電層
246‧‧‧第三子介電層
250‧‧‧第一導電線路
252‧‧‧第二導電線路
260‧‧‧導電元件
270‧‧‧開口
P1‧‧‧半導體封裝組件
S‧‧‧子封裝
L‧‧‧切割道

Claims (30)

  1. 一種半導體封裝組件，包括：一第一半導體封裝，包括：一第一半導體晶片；一第一重佈層結構，設置於該第一半導體晶片之上，且與該第一半導體晶片電性連接；一主動或被動元件，設置於該第一半導體晶片與該第一重佈層結構之間；以及一模塑料，圍繞該第一半導體晶片和該主動或被動元件。
  2. 如申請專利範圍第1項所述之半導體封裝組件，其中一個以上的該主動或被動元件設置於該第一半導體晶片與該第一重佈層結構之間。
  3. 如申請專利範圍第1項所述之半導體封裝組件，其中該第一重佈層結構透過一第一導孔與該第一半導體晶片電性連接，且其中該第一導孔設置於該第一半導體晶片與該第一重佈層結構之間，且被該模塑料圍繞。
  4. 如申請專利範圍第1項所述之半導體封裝組件，其中該第一半導體封裝更包括一第二重佈層結構，且該第一半導體晶片位於該主動或被動元件與該第二重佈層結構之間。
  5. 如申請專利範圍第4項所述之半導體封裝組件，其中該模塑料覆蓋該第二重佈層結構。
  6. 如申請專利範圍第4項所述之半導體封裝組件，其中該第二重佈層結構透過一第二導孔與該第一重佈層結構電性連接，且其中該第二導孔被該模塑料圍繞。
  7. 如申請專利範圍第6項所述之半導體封裝組件，其中該第二導孔位於該第一半導體晶片之一周圍區域。
  8. 如申請專利範圍第1項所述之半導體封裝組件，其中該第一半導體封裝更包括一導電元件與該第一重佈層結構耦接，其中該導電元件和該主動或被動元件位於該第一重佈層結構之兩個相反側。
  9. 如申請專利範圍第1項所述之半導體封裝組件，更包括一第二半導體封裝堆疊於該第一半導體封裝之上，其中該第一半導體晶片位於該主動或被動元件與該第二半導體封裝之間。
  10. 如申請專利範圍第9項所述之半導體封裝組件，其中該第二半導體封裝是一記憶體封裝。
  11. 如申請專利範圍第1項所述之半導體封裝組件，其中該第一半導體封裝更包括被該模塑料圍繞的一第二半導體晶片，且該第一半導體晶片和該第二半導體晶片並排放置。
  12. 如申請專利範圍第11項所述之半導體封裝組件，其中該第一半導體封裝更包括另一主動或被動元件被該模塑料圍繞且設置於該第二半導體晶片與該第一重佈層結構之間。
  13. 如申請專利範圍第11項所述之半導體封裝組件，其中該第一半導體封裝更包括被該模塑料圍繞的一導孔，且其中該導孔、該第一半導體晶片和該第二半導體晶片並排放置。
  14. 如申請專利範圍第13項所述之半導體封裝組件，其中該導孔設置於該第一半導體晶片與該第二半導體晶片之間。
  15. 一種半導體封裝組件，包括： 一第一半導體封裝，包括：一第一半導體晶片；一第一重佈層結構，設置於該第一半導體晶片之上，且與該第一半導體晶片電性連接；以及一主動或被動元件，設置於該第一半導體晶片與該第一重佈層結構之間；以及一第二半導體封裝，堆疊於該第一半導體封裝之上，其中該第一半導體晶片位於該主動或被動元件與該第二半導體封裝之間。
  16. 如申請專利範圍第15項所述之半導體封裝組件，其中該第二半導體封裝包括一第二半導體晶片設置於一基底之上，且該第二半導體晶片和該主動或被動元件位於該基底之兩個相反側。
  17. 如申請專利範圍第16項所述之半導體封裝組件，其中該主動或被動元件縱向地重疊該第一半導體晶片和該第二半導體晶片。
  18. 如申請專利範圍第15項所述之半導體封裝組件，其中該第一半導體封裝更包括：一模塑料，圍繞該第一半導體晶片和該主動或被動元件；以及一第一導孔，被該模塑料所圍繞，其中該第一半導體晶片位於該第一導孔與該第二半導體封裝之間。
  19. 如申請專利範圍第18項所述之半導體封裝組件，其中該第一半導體封裝更包括一第二導孔，該第二導孔被該模塑料 圍繞且位於該第一重佈層結構與該第二半導體封裝之間。
  20. 如申請專利範圍第19項所述之半導體封裝組件，其中該第二導孔之一尺寸大於該第一導孔之一尺寸。
  21. 一種半導體封裝組件的製造方法，包括：形成一第一半導體封裝，其中該第一半導體封裝的形成包括：在一第一半導體晶片之上提供一主動或被動元件；形成一模塑料圍繞該第一半導體晶片和該主動或被動元件；以及形成一第一重佈層結構於該第一半導體晶片之上，以電性連接該第一半導體晶片，其中該主動或被動元件位於該第一半導體晶片與該第一重佈層結構之間。
  22. 如申請專利範圍第21項所述之半導體封裝組件的製造方法，更包括在提供該主動或被動元件之前，形成一第一導孔於該第一半導體晶片之上，其中該第一重佈層結構透過該第一導孔與該第一半導體晶片電性連接。
  23. 如申請專利範圍第22項所述之半導體封裝組件的製造方法，其中該模塑料圍繞該第一導孔而未覆蓋該第一導孔之一頂表面。
  24. 如申請專利範圍第22項所述之半導體封裝組件的製造方法，更包括在形成該模塑料之前，將具有該主動或被動元件和該第一導孔於其上的該第一半導體晶片接合至一承載基底。
  25. 如申請專利範圍第24項所述之半導體封裝組件的製造方 法，更包括：在形成該第一重佈層結構之後，剝離該承載基底；以及切割該第一重佈層結構、第二重佈層結構和該模塑料，以形成該第一半導體封裝。
  26. 如申請專利範圍第24項所述之半導體封裝組件的製造方法，更包括在接合該第一半導體晶片之前，形成一第二導孔於該承載基底之上，其中該第二導孔和該第一半導體晶片並排設置。
  27. 如申請專利範圍第26項所述之半導體封裝組件的製造方法，其中該模塑料圍繞該第二導孔而未覆蓋該第二導孔之一頂表面。
  28. 如申請專利範圍第26項所述之半導體封裝組件的製造方法，更包括在形成該第二導孔之前，形成一第二重佈層結構於該承載基底之上，其中該第二重佈層結構位於該第一半導體晶片與該承載基底之間。
  29. 如申請專利範圍第28項所述之半導體封裝組件的製造方法，更包括：在形成該第一重佈層結構之後，剝離該承載基底，以露出該第二重佈層結構；以及堆疊一第二半導體封裝於該第一半導體封裝之上，其中該第一半導體晶片位於該主動或被動元件與該第二半導體封裝之間。
  30. 如申請專利範圍第29項所述之半導體封裝組件的製造方法，更包括： 在剝離該承載基底之後，形成一開口於該第二重佈層結構中；以及形成一導電元件於該開口中，以電性連接該第一半導體封裝和該第二半導體封裝。
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