TW201622074A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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TW201622074A
TW201622074A TW103142314A TW103142314A TW201622074A TW 201622074 A TW201622074 A TW 201622074A TW 103142314 A TW103142314 A TW 103142314A TW 103142314 A TW103142314 A TW 103142314A TW 201622074 A TW201622074 A TW 201622074A
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Taiwan
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electronic
carrier
electronic package
conductive elements
manufacturing
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TW103142314A
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TWI560818B (en
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蔣靜雯
陳光欣
盧勝利
鄭凱如
陳賢文
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矽品精密工業股份有限公司
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Priority to TW103142314A priority Critical patent/TWI560818B/zh
Priority to CN201510026659.9A priority patent/CN105870074A/zh
Priority to US14/817,233 priority patent/US9818683B2/en
Publication of TW201622074A publication Critical patent/TW201622074A/zh
Application granted granted Critical
Publication of TWI560818B publication Critical patent/TWI560818B/zh
Priority to US15/784,782 priority patent/US10199320B2/en

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Abstract

一種電子封裝件之製法，係先提供一具有相對之第一表面及第二表面之承載體，且該第一表面上具有複數連通至該第二表面之凹部，再設置電子結構於該承載體之第一表面上，該電子結構設有複數導電元件，且該些導電元件對應容置於各該凹部中，之後自該第二表面移除該承載體之部分材質，使該些導電元件外露於該承載體之第二表面，藉以保留該承載體，因而沒有暫時性材料，故能降低之製作成本。本發明復提供該電子封裝件。

Description

電子封裝件及其製法
本發明係有關一種電子封裝件，尤指一種降低成本之電子封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術，例如晶片尺寸構裝(Chip Scale Package,CSP)、晶片直接貼附封裝(Direct Chip Attached,DCA)或多晶片模組封裝(Multi-Chip Module,MCM)等覆晶型態的封裝模組、或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等。
第1圖係為習知3D晶片堆疊之半導體封裝件1之製法之剖面示意圖。如第1圖所示，提供一矽中介板(Through Silicon interposer,TSI)10，該矽中介板10具有相對之置晶側10a與轉接側10b、及連通該置晶側10a與轉接側10b之複數導電矽穿孔(Through-silicon via,TSV)100，且該轉接側10b上具有一線路重佈結構(Redistribution layer,RDL)101。將間距較小之半導體晶片19之電極墊190係藉由複數銲錫凸塊102電性結合至該置晶側10a上，再以 底膠192包覆該些銲錫凸塊102，且形成封裝膠體18於該矽中介板10上，以覆蓋該半導體晶片19。於該線路重佈結構101上藉由複數如凸塊之導電元件103電性結合間距較大之封裝基板17之銲墊170，並以底膠172包覆該些導電元件103。
目前製作該半導體封裝件1時，會先將該矽中介板10設置於具有複數凹部(圖略)之第一承載件(如晶圓，圖略)上，該凹部係藉由黏膠對應容置該些導電元件103，以利於將該矽中介板10定位；接著，將該半導體晶片19置放至該矽中介板10上，以藉由該些銲錫凸塊102完成該半導體晶片19與該矽中介板10之電性連接；接著藉由黏膠結合一第二承載件(圖略)於該半導體晶片19上，再進行翻轉步驟，之後移除該第一承載件及黏膠；接著，先進行翻轉製程，再將該矽中介板10以該些導電元件103接置於該封裝基板17上，再移除該第二承載件及黏膠，之後形成該封裝膠體18。
惟，前述半導體封裝件1之製法中，需多次進行結合/移除承載件及黏膠之步驟與翻轉之步驟，致使製程步驟繁多，不僅耗時，且需消耗承載件之料數，而增加產品之製作成本。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電 子封裝件，係包括：承載體，係具有相對之第一表面及第二表面，且該第一表面上具有複數連通至該第二表面之凹部；電子結構，係設於該承載體之第一表面上；以及複數導電元件，係設於該電子結構上並對應容置於各該凹部中，且使該些導電元件外露於該承載體之第二表面。
本發明復提供一種電子封裝件之製法，係包括：提供一具有相對之第一表面及第二表面之承載體，且該第一表面上具有複數凹部；設置電子結構於該承載體之第一表面上，其中，該電子結構具有複數導電元件，使該電子結構設置於該承載體上後，該些導電元件係對應容置於各該凹部中；以及自該第二表面移除部分該承載體，使該些導電元件外露於該承載體之第二表面。
前述之電子封裝件及其製法中，該承載體係為半導體板體。
前述之電子封裝件及其製法中，該電子結構係包含至少一設有該些導電元件之中介板、設於該中介板上之電子元件、及包覆該中介板與該電子元件之絕緣層，且該些導電元件凸出該絕緣層。
前述之電子封裝件及其製法中，該些導電元件藉由結合材固定於各該凹部中。
前述之電子封裝件及其製法中，自該第二表面移除部分該承載體係以整平方式為之，使該些導電元件之表面齊平於該承載體之第二表面。
前述之電子封裝件及其製法中，自該第二表面移除部 分該承載體的方式係在該承載體中形成對應各該凹部之複數開孔，以令該些導電元件外露於該些開孔。復包括形成導電體於各該開孔中。
前述之電子封裝件及其製法中，該電子結構係為主動元件、被動元件或其組合者。
前述之電子封裝件及其製法中，該承載體之第一表面上形成有供設置該電子結構之開口，且該些凹部形成於該開口之底部上。復包括形成絕緣層於該開口中，以令該絕緣層包覆該電子結構。
前述之電子封裝件及其製法中，復包括形成複數導電通孔於該承載體中。
另外，前述之電子封裝件及其製法中，復包括形成線路結構於該承載體之第一表面上。
由上可知，本發明之電子封裝件之製法，主要藉由將該電子結構上之導電元件對應容置於各該凹部中，且保留該承載體，因而不需移除該承載體，亦即沒有暫時性材料(如習知承載件及黏膠)，故相較於習知技術，本發明不僅能減少製程步驟以縮短製程時間，且無需消耗承載件之料數，而能降低之製作成本。
1‧‧‧半導體封裝件
10‧‧‧矽中介板
10a‧‧‧置晶側
10b‧‧‧轉接側
100‧‧‧導電矽穿孔
101‧‧‧線路重佈結構
102,240‧‧‧銲錫凸塊
103,22,42,48‧‧‧導電元件
17‧‧‧封裝基板
170‧‧‧銲墊
172,192‧‧‧底膠
18‧‧‧封裝膠體
19‧‧‧半導體晶片
190,410‧‧‧電極墊
2,3,3’,4,4’‧‧‧電子封裝件
20‧‧‧承載體
20a‧‧‧第一表面
20b‧‧‧第二表面
200‧‧‧凹部
21,41‧‧‧電子結構
22a‧‧‧表面
220‧‧‧凸塊底下金屬層
23‧‧‧中介板
230‧‧‧導電穿孔
231‧‧‧重佈線路層
24‧‧‧電子元件
25,45‧‧‧絕緣層
26‧‧‧結合材
29,49‧‧‧電子裝置
290‧‧‧電性接觸墊
300‧‧‧開孔
37,37’,47‧‧‧導電體
400‧‧‧開口
41a‧‧‧作用面
41b‧‧‧非作用面
43‧‧‧導電通孔
44‧‧‧線路結構
S‧‧‧切割路徑
第1圖係為習知半導體封裝件之剖面示意圖；第2A至2D圖係為本發明之電子封裝件之製法之第一實施例的剖面示意圖；第2E圖係為第2D圖之後續製程的剖面示意圖； 第3A至3B圖係為第2C至2D圖之另一方法；其中，第3B’圖係為第3B圖之另一態樣；以及第4A至4E圖係為本發明之電子封裝件之製法之第二實施例的剖面示意圖；其中，第4E’圖係為第4E圖之另一態樣。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2D圖係為本發明之電子封裝件2之製法之第一實施例的剖面示意圖。
如第2A圖所示，提供一設有複數導電元件22之電子結構21、及一具有相對之第一表面20a及第二表面20b之承載體20，且該承載體20之第一表面20a上具有複數凹 部200。
於本實施例中，該承載體20係為半導體板體，例如矽晶圓(Si wafer)型式，且該電子結構21係包含複數設有該些導電元件22之中介板23、設於各該中介板23上之複數電子元件24、及包覆該些中介板23與該些電子元件24之絕緣層25，而該些導電元件22係凸出該絕緣層25。
再者，該中介板23具有複數導電穿孔230與電性連接該導電穿孔230之至少一重佈線路層(redistribution layer，簡稱RDL)231，且該電子元件24係為主動元件、被動元件或其組合者，其中，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。於此，該電子元件24係為半導體晶片，其藉由銲錫凸塊240電性結合該重佈線路層231。
又，形成該絕緣層25之材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(expoxy)或封裝材。
另外，可依需求形成凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)220於該導電穿孔230與該導電元件22之間，即該些導電元件22對應設於各該導電穿孔230之端面上，且該導電元件22如銲球或其它金屬塊體(如銅柱)，並無特別限制。
如第2B圖所示，將該電子結構21設於該承載體20之第一表面20a上，且該些導電元件22對應容置於各該凹部200中。
於本實施例中，藉由如底膠之結合材26將該些導電元件22固定於各該凹部200中，以固定該電子結構21於該承載體20之第一表面20a上。
如第2C圖所示，自該第二表面20b移除該承載體20之部分材質，使該些導電元件22外露於該承載體20之第二表面20b。
於本實施例中，自該第二表面20b移除該承載體20之部分材質的方式係為整平方式，例如研磨製程，使該些導電元件22之表面22a齊平該承載體20之第二表面20b。
或者，自該第二表面移除該承載體20之部分材質的方式係為鑽孔製程，如第3A圖所示，即形成對應各該凹部200之複數開孔300，令該些導電元件22外露於各該開孔300。其中，有關鑽孔製程之方式繁多，例如蝕刻、雷射等，並無特別限制。
如第2D圖所示，接續第2C圖之製程，沿如第2C圖所示之切割路徑S進行切單製程，以獲得複數電子封裝件2。
再者，若接續第3A圖之製程，將得到如第3B及3B’圖所示之電子封裝件3,3’，且可形成複數導電體37,37’於各該開孔300中，且各該導電體37,37’係為線路(如第3B圖所示)或如銲錫材料之導電凸塊(如第3B’圖所示)。
另外，於後續製程中，如第2E圖所示，該電子封裝件2可藉由該些導電元件22結合至一如封裝基板之電子裝置29，且該電子裝置29具有複數電性接觸墊290以結合 該些導電元件22。
本發明之製法，係將該電子結構21上之導電元件22對應容置於各該凹部200中，且保留該承載體20及結合材26，因而不需進行移除該承載體20及結合材26之製程，亦即沒有暫時性材料(如習知承載件及黏膠)，故不僅能減少製程步驟以縮短製程時間，且無需消耗承載件之料數，而能降低之製作成本。
再者，因需移除該承載體20及結合材26，故不會產生殘膠之問題。
第4A至4E圖係為本發明之電子封裝件4之製法之第二實施例的剖面示意圖。以下僅詳細說明本實施例與第一實施例之差異處，兩者之相同處將省略或簡述。
如第4A圖所示，提供一設有複數導電元件22之電子結構41、及一具有相對之第一表面20a及第二表面20b之承載體20，且該承載體20之第一表面20a上具有複數凹部200。
於本實施例中，該承載體20之第一表面20a上形成有供設置該電子結構41之開口400，且該些凹部200形成於該開口400之底部上。
再者，該電子結構41係為主動元件、被動元件或其組合者，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。於此，該電子結構41係為半導體晶片，其具有相對之作用面41a與非作用面41b，且該作用面41a具有複數電極墊410，而該些電極墊410電性結合 該些導電元件22。
如第4B圖所示，將該電子結構41設於該開口400中，且該些導電元件22對應容置於各該凹部200中。接著，形成一絕緣層45於該開口400中，以令該絕緣層45包覆該電子結構41。
於本實施例中，藉由如底膠之結合材26將該些導電元件22固定於各該凹部200中，以固定該電子結構41於該開口400中。
再者，該絕緣層45復形成於該開口400外之第一表面20a上，且形成該絕緣層45之材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(expoxy)或封裝材。
如第4C圖所示，進行鑽孔製程，以形成對應各該凹部200之複數開孔300，使該些導電元件22外露於各該開孔300。
如第4D圖所示，形成一導電體47於該承載體20之第二表面20b上與各該開孔300中，以令該導電體47電性連接該些導電元件22。
於本實施例中，該導電體47係為線路重佈層(RDL)。
如第4E圖所示，形成複數如銲球之導電元件48於該導電體47上，並沿如第4D圖所示之切割路徑S進行切單製程，以獲得該電子封裝件4。
於本實施例中，於後續製程中，如第4E’圖所示，該電子封裝件4可藉由該些導電元件48結合至該電子裝置 29之電性接觸墊290上
再者，於其它實施例中，如第4E’圖所示，可形成複數導電通孔43於該承載體20與該絕緣層45中，且形成一線路結構44於該承載體20之第一表面20a上，且該些導電通孔43連通該承載體20之第一與第二表面20a,20b，使該些導電通孔43能電性連接該線路結構44與該導電體47。
又，該線路結構44係以線路重佈層(RDL)製程製作之結構，且該線路結構44可藉由複數如銲球之導電元件42堆疊如封裝件或晶片之另一電子裝置49。
本發明之製法，係將該電子結構41上之導電元件22對應容置於各該凹部200中，且保留該承載體20及結合材26，因而不需進行移除該承載體20及結合材26之製程，亦即沒有暫時性材料(如習知承載件及黏膠)，故不僅能減少製程步驟以縮短製程時間，且無需消耗承載件之料數，而能降低之製作成本。
再者，因需移除該承載體20及結合材26，故不會產生殘膠之問題。
本發明提供一種電子封裝件2,3,3’,4,4’，係包括：一承載體20、一電子結構21,41以及複數導電元件22。
所述之承載體20係具有相對之第一表面20a及第二表面20b，且該第一表面20a上具有複數連通至該第二表面20b之凹部200。例如，該承載體20係為半導體板體。
所述之電子結構21,41係設於該承載體20之第一表面20a上。
所述之導電元件22係設於該電子結構21,41上並對應容置於各該凹部200中，且使該些導電元件22外露於該承載體20之第二表面20b。
於一實施例中，該電子結構21係包含至少一設有該些導電元件22之中介板23、設於該中介板23上之電子元件24、及包覆該中介板23與該電子元件24之絕緣層25。
於一實施例中，該些導電元件22藉由結合材26固定於各該凹部200中。
於一實施例中，該些導電元件22之表面22a齊平該承載體20之第二表面20b。
於一實施例中，該承載體20之第二表面20b上形成有對應各該凹部200之複數開孔300，令該些導電元件22外露於該些開孔300，且導電體37,37’,47形成於各該開孔300中。
於一實施例中，該電子結構41係為主動元件、被動元件或其組合者。
於一實施例中，該承載體20之第一表面20a上形成有供設置該電子結構41之開口400，且該些凹部200形成於該開口400之底部上。所述之電子封裝件4,4’復包括一絕緣層45，係形成於該開口400中，以令該絕緣層45包覆該電子結構41。
於一實施例中，所述之電子封裝件4’復包括複數導電通孔43，係形成於該承載體20中。
於一實施例中，所述之電子封裝件4’復包括一線路結 構44，係形成於該承載體20之第一表面20a上。
綜上所述，本發明之電子封裝件及其製法，係藉由將該電子結構上之導電元件對應容置於各該凹部中，且保留該承載體，因而不需進行移除該承載體之製程，亦即沒有暫時性材料，故不僅能減少製程步驟以縮短製程時間，且無需消耗承載件之料數，而能降低之製作成本。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
20‧‧‧承載體
20a‧‧‧第一表面
20b‧‧‧第二表面
200‧‧‧凹部
21‧‧‧電子結構
22‧‧‧導電元件
22a‧‧‧表面

Claims (26)

  1. 一種電子封裝件，係包括：承載體，係具有相對之第一表面及第二表面，且該第一表面上具有複數連通至該第二表面之凹部；電子結構，係設於該承載體之第一表面上；以及複數導電元件，係設於該電子結構上並對應容置於各該凹部中，且使該些導電元件外露於該承載體之第二表面。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該承載體係為半導體板體。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該電子結構係包含至少一設有該些導電元件之中介板、及設於該中介板上之電子元件。
  4. 如申請專利範圍第3項所述之電子封裝件，其中，該電子結構復包含包覆該中介板與該電子元件之絕緣層。
  5. 如申請專利範圍第1項所述之電子封裝件，其中，該些導電元件藉由結合材固定於各該凹部中。
  6. 如申請專利範圍第1項所述之電子封裝件，其中，該些導電元件之表面齊平該承載體之第二表面。
  7. 如申請專利範圍第1項所述之電子封裝件，其中，該第二表面上形成有對應各該凹部之複數開孔，令該些導電元件外露於該些開孔。
  8. 如申請專利範圍第7項所述之電子封裝件，復包括導 電體，係形成於各該開孔中。
  9. 如申請專利範圍第1項所述之電子封裝件，其中，該電子結構係為主動元件、被動元件或其組合者。
  10. 如申請專利範圍第1項所述之電子封裝件，其中，該承載體之第一表面上形成有供設置該電子結構之開口，且該些凹部形成於該開口之底部上。
  11. 如申請專利範圍第10項所述之電子封裝件，復包括絕緣層，係形成於該開口中，以令該絕緣層包覆該電子結構。
  12. 如申請專利範圍第1項所述之電子封裝件，復包括複數導電通孔，係形成於該承載體中。
  13. 如申請專利範圍第1項所述之電子封裝件，復包括線路結構，係形成於該承載體之第一表面上。
  14. 一種電子封裝件之製法，係包括：提供一具有相對之第一表面及第二表面之承載體，其中，該第一表面上形成有複數凹部；設置電子結構於該承載體之第一表面上，其中，該電子結構具有複數導電元件，使該電子結構設置於該承載體上後，該些導電元件係對應容置於各該凹部中；以及自該第二表面移除部分該承載體，使該些導電元件外露於該承載體之第二表面。
  15. 如申請專利範圍第14項所述之電子封裝件之製法，其中，該承載體係為半導體板體。
  16. 如申請專利範圍第14項所述之電子封裝件之製法，其中，該電子結構係包含至少一設有該些導電元件之中介板、及設於該中介板上之電子元件。
  17. 如申請專利範圍第16項所述之電子封裝件之製法，其中，該電子結構復包含包覆該中介板與該電子元件之絕緣層，且該些導電元件凸出該絕緣層。
  18. 如申請專利範圍第14項所述之電子封裝件之製法，其中，該些導電元件藉由結合材固定於各該凹部中。
  19. 如申請專利範圍第14項所述之電子封裝件之製法，其中，自該第二表面移除部分該承載體係以整平方式為之，使該些導電元件之表面齊平於該承載體之第二表面。
  20. 如申請專利範圍第14項所述之電子封裝件之製法，其中，自該第二表面移除部分該承載體的方式係在該承載體中形成對應各該凹部之複數開孔，以令該些導電元件外露於該些開孔。
  21. 如申請專利範圍第20項所述之電子封裝件之製法，復包括形成導電體於各該開孔中。
  22. 如申請專利範圍第14項所述之電子封裝件之製法，其中，該電子結構係為主動元件、被動元件或其組合者。
  23. 如申請專利範圍第14項所述之電子封裝件之製法，其中，該承載體之第一表面上形成有供設置該電子結構之開口，且該些凹部形成於該開口之底部上。
  24. 如申請專利範圍第23項所述之電子封裝件之製法，復 包括形成絕緣層於該開口中，以令該絕緣層包覆該電子結構。
  25. 如申請專利範圍第14項所述之電子封裝件之製法，復包括形成複數導電通孔於該承載體中。
  26. 如申請專利範圍第14項所述之電子封裝件之製法，復包括形成線路結構於該承載體之第一表面上。
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